src/gallium/drivers/radeon/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #ifndef RADEON_WINSYS_H
  25 #define RADEON_WINSYS_H
  26
  27 /* The public winsys interface header for the radeon driver. */
  28
  29 /* R300 features in DRM.
  30  *
  31  * 2.6.0:
  32  * - Hyper-Z
  33  * - GB_Z_PEQ_CONFIG on rv350->r4xx
  34  * - R500 FG_ALPHA_VALUE
  35  *
  36  * 2.8.0:
  37  * - R500 US_FORMAT regs
  38  * - R500 ARGB2101010 colorbuffer
  39  * - CMask and AA regs
  40  * - R16F/RG16F
  41  */
  42
  43 #include "pipebuffer/pb_buffer.h"
  44
  45 #define RADEON_FLUSH_ASYNC              (1 << 0)
  46 #define RADEON_FLUSH_KEEP_TILING_FLAGS  (1 << 1) /* needs DRM 2.12.0 */
  47 #define RADEON_FLUSH_END_OF_FRAME       (1 << 2)
  48
  49 /* Tiling flags. */
  50 enum radeon_bo_layout {
  51     RADEON_LAYOUT_LINEAR = 0,
  52     RADEON_LAYOUT_TILED,
  53     RADEON_LAYOUT_SQUARETILED,
  54
  55     RADEON_LAYOUT_UNKNOWN
  56 };
  57
  58 enum radeon_bo_domain { /* bitfield */
  59     RADEON_DOMAIN_GTT  = 2,
  60     RADEON_DOMAIN_VRAM = 4,
  61     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  62 };
  63
  64 enum radeon_bo_flag { /* bitfield */
  65     RADEON_FLAG_GTT_WC =        (1 << 0),
  66     RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  67     RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  68 };
  69
  70 enum radeon_bo_usage { /* bitfield */
  71     RADEON_USAGE_READ = 2,
  72     RADEON_USAGE_WRITE = 4,
  73     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
  74 };
  75
  76 enum radeon_family {
  77     CHIP_UNKNOWN = 0,
  78     CHIP_R300, /* R3xx-based cores. */
  79     CHIP_R350,
  80     CHIP_RV350,
  81     CHIP_RV370,
  82     CHIP_RV380,
  83     CHIP_RS400,
  84     CHIP_RC410,
  85     CHIP_RS480,
  86     CHIP_R420,     /* R4xx-based cores. */
  87     CHIP_R423,
  88     CHIP_R430,
  89     CHIP_R480,
  90     CHIP_R481,
  91     CHIP_RV410,
  92     CHIP_RS600,
  93     CHIP_RS690,
  94     CHIP_RS740,
  95     CHIP_RV515,    /* R5xx-based cores. */
  96     CHIP_R520,
  97     CHIP_RV530,
  98     CHIP_R580,
  99     CHIP_RV560,
 100     CHIP_RV570,
 101     CHIP_R600,
 102     CHIP_RV610,
 103     CHIP_RV630,
 104     CHIP_RV670,
 105     CHIP_RV620,
 106     CHIP_RV635,
 107     CHIP_RS780,
 108     CHIP_RS880,
 109     CHIP_RV770,
 110     CHIP_RV730,
 111     CHIP_RV710,
 112     CHIP_RV740,
 113     CHIP_CEDAR,
 114     CHIP_REDWOOD,
 115     CHIP_JUNIPER,
 116     CHIP_CYPRESS,
 117     CHIP_HEMLOCK,
 118     CHIP_PALM,
 119     CHIP_SUMO,
 120     CHIP_SUMO2,
 121     CHIP_BARTS,
 122     CHIP_TURKS,
 123     CHIP_CAICOS,
 124     CHIP_CAYMAN,
 125     CHIP_ARUBA,
 126     CHIP_TAHITI,
 127     CHIP_PITCAIRN,
 128     CHIP_VERDE,
 129     CHIP_OLAND,
 130     CHIP_HAINAN,
 131     CHIP_BONAIRE,
 132     CHIP_KAVERI,
 133     CHIP_KABINI,
 134     CHIP_HAWAII,
 135     CHIP_MULLINS,
 136     CHIP_TONGA,
 137     CHIP_ICELAND,
 138     CHIP_CARRIZO,
 139     CHIP_FIJI,
 140     CHIP_LAST,
 141 };
 142
 143 enum chip_class {
 144     CLASS_UNKNOWN = 0,
 145     R300,
 146     R400,
 147     R500,
 148     R600,
 149     R700,
 150     EVERGREEN,
 151     CAYMAN,
 152     SI,
 153     CIK,
 154     VI,
 155 };
 156
 157 enum ring_type {
 158     RING_GFX = 0,
 159     RING_COMPUTE,
 160     RING_DMA,
 161     RING_UVD,
 162     RING_VCE,
 163     RING_LAST,
 164 };
 165
 166 enum radeon_value_id {
 167     RADEON_REQUESTED_VRAM_MEMORY,
 168     RADEON_REQUESTED_GTT_MEMORY,
 169     RADEON_BUFFER_WAIT_TIME_NS,
 170     RADEON_TIMESTAMP,
 171     RADEON_NUM_CS_FLUSHES,
 172     RADEON_NUM_BYTES_MOVED,
 173     RADEON_VRAM_USAGE,
 174     RADEON_GTT_USAGE,
 175     RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
 176     RADEON_CURRENT_SCLK,
 177     RADEON_CURRENT_MCLK,
 178     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
 179 };
 180
 181 enum radeon_bo_priority {
 182     RADEON_PRIO_MIN,
 183     RADEON_PRIO_SHADER_DATA, /* shader code, resource descriptors */
 184     RADEON_PRIO_SHADER_BUFFER_RO, /* read-only */
 185     RADEON_PRIO_SHADER_TEXTURE_RO, /* read-only */
 186     RADEON_PRIO_SHADER_RESOURCE_RW, /* buffers, textures, streamout, GS rings, RATs; read/write */
 187     RADEON_PRIO_COLOR_BUFFER,
 188     RADEON_PRIO_DEPTH_BUFFER,
 189     RADEON_PRIO_SHADER_TEXTURE_MSAA,
 190     RADEON_PRIO_COLOR_BUFFER_MSAA,
 191     RADEON_PRIO_DEPTH_BUFFER_MSAA,
 192     RADEON_PRIO_COLOR_META,
 193     RADEON_PRIO_DEPTH_META,
 194     RADEON_PRIO_MAX /* must be <= 15 */
 195 };
 196
 197 struct winsys_handle;
 198 struct radeon_winsys_cs_handle;
 199 struct radeon_winsys_ctx;
 200
 201 struct radeon_winsys_cs {
 202     unsigned                    cdw;  /* Number of used dwords. */
 203     unsigned                    max_dw; /* Maximum number of dwords. */
 204     uint32_t                    *buf; /* The command buffer. */
 205     enum ring_type              ring_type;
 206 };
 207
 208 struct radeon_info {
 209     uint32_t                    pci_id;
 210     enum radeon_family          family;
 211     enum chip_class             chip_class;
 212     uint64_t                    gart_size;
 213     uint64_t                    vram_size;
 214     uint32_t                    max_sclk;
 215     uint32_t                    max_compute_units;
 216     uint32_t                    max_se;
 217     uint32_t                    max_sh_per_se;
 218
 219     uint32_t                    drm_major; /* version */
 220     uint32_t                    drm_minor;
 221     uint32_t                    drm_patchlevel;
 222
 223     boolean                     has_uvd;
 224     uint32_t                    vce_fw_version;
 225     boolean                     has_userptr;
 226
 227     uint32_t                    r300_num_gb_pipes;
 228     uint32_t                    r300_num_z_pipes;
 229
 230     uint32_t                    r600_num_backends;
 231     uint32_t                    r600_clock_crystal_freq;
 232     uint32_t                    r600_tiling_config;
 233     uint32_t                    r600_num_tile_pipes;
 234     uint32_t                    r600_max_pipes;
 235     boolean                     r600_virtual_address;
 236     boolean                     r600_has_dma;
 237
 238     uint32_t                    r600_backend_map;
 239     boolean                     r600_backend_map_valid;
 240
 241     boolean                     si_tile_mode_array_valid;
 242     uint32_t                    si_tile_mode_array[32];
 243     uint32_t                    si_backend_enabled_mask;
 244
 245     boolean                     cik_macrotile_mode_array_valid;
 246     uint32_t                    cik_macrotile_mode_array[16];
 247     uint32_t                    vce_harvest_config;
 248 };
 249
 250 enum radeon_feature_id {
 251     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 252     RADEON_FID_R300_CMASK_ACCESS,
 253 };
 254
 255 #define RADEON_SURF_MAX_LEVEL                   32
 256
 257 #define RADEON_SURF_TYPE_MASK                   0xFF
 258 #define RADEON_SURF_TYPE_SHIFT                  0
 259 #define     RADEON_SURF_TYPE_1D                     0
 260 #define     RADEON_SURF_TYPE_2D                     1
 261 #define     RADEON_SURF_TYPE_3D                     2
 262 #define     RADEON_SURF_TYPE_CUBEMAP                3
 263 #define     RADEON_SURF_TYPE_1D_ARRAY               4
 264 #define     RADEON_SURF_TYPE_2D_ARRAY               5
 265 #define RADEON_SURF_MODE_MASK                   0xFF
 266 #define RADEON_SURF_MODE_SHIFT                  8
 267 #define     RADEON_SURF_MODE_LINEAR                 0
 268 #define     RADEON_SURF_MODE_LINEAR_ALIGNED         1
 269 #define     RADEON_SURF_MODE_1D                     2
 270 #define     RADEON_SURF_MODE_2D                     3
 271 #define RADEON_SURF_SCANOUT                     (1 << 16)
 272 #define RADEON_SURF_ZBUFFER                     (1 << 17)
 273 #define RADEON_SURF_SBUFFER                     (1 << 18)
 274 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
 275 #define RADEON_SURF_HAS_SBUFFER_MIPTREE         (1 << 19)
 276 #define RADEON_SURF_HAS_TILE_MODE_INDEX         (1 << 20)
 277 #define RADEON_SURF_FMASK                       (1 << 21)
 278
 279 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
 280 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
 281 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
 282
 283 struct radeon_surf_level {
 284     uint64_t                    offset;
 285     uint64_t                    slice_size;
 286     uint32_t                    npix_x;
 287     uint32_t                    npix_y;
 288     uint32_t                    npix_z;
 289     uint32_t                    nblk_x;
 290     uint32_t                    nblk_y;
 291     uint32_t                    nblk_z;
 292     uint32_t                    pitch_bytes;
 293     uint32_t                    mode;
 294 };
 295
 296 struct radeon_surf {
 297     /* These are inputs to the calculator. */
 298     uint32_t                    npix_x;
 299     uint32_t                    npix_y;
 300     uint32_t                    npix_z;
 301     uint32_t                    blk_w;
 302     uint32_t                    blk_h;
 303     uint32_t                    blk_d;
 304     uint32_t                    array_size;
 305     uint32_t                    last_level;
 306     uint32_t                    bpe;
 307     uint32_t                    nsamples;
 308     uint32_t                    flags;
 309
 310     /* These are return values. Some of them can be set by the caller, but
 311      * they will be treated as hints (e.g. bankw, bankh) and might be
 312      * changed by the calculator.
 313      */
 314     uint64_t                    bo_size;
 315     uint64_t                    bo_alignment;
 316     /* This applies to EG and later. */
 317     uint32_t                    bankw;
 318     uint32_t                    bankh;
 319     uint32_t                    mtilea;
 320     uint32_t                    tile_split;
 321     uint32_t                    stencil_tile_split;
 322     uint64_t                    stencil_offset;
 323     struct radeon_surf_level    level[RADEON_SURF_MAX_LEVEL];
 324     struct radeon_surf_level    stencil_level[RADEON_SURF_MAX_LEVEL];
 325     uint32_t                    tiling_index[RADEON_SURF_MAX_LEVEL];
 326     uint32_t                    stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
 327     uint32_t                    pipe_config;
 328     uint32_t                    num_banks;
 329 };
 330
 331 struct radeon_winsys {
 332     /**
 333      * The screen object this winsys was created for
 334      */
 335     struct pipe_screen *screen;
 336
 337     /**
 338      * Decrement the winsys reference count.
 339      *
 340      * \param ws  The winsys this function is called for.
 341      * \return    True if the winsys and screen should be destroyed.
 342      */
 343     bool (*unref)(struct radeon_winsys *ws);
 344
 345     /**
 346      * Destroy this winsys.
 347      *
 348      * \param ws        The winsys this function is called from.
 349      */
 350     void (*destroy)(struct radeon_winsys *ws);
 351
 352     /**
 353      * Query an info structure from winsys.
 354      *
 355      * \param ws        The winsys this function is called from.
 356      * \param info      Return structure
 357      */
 358     void (*query_info)(struct radeon_winsys *ws,
 359                        struct radeon_info *info);
 360
 361     /**************************************************************************
 362      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 363      *
 364      * Remember that gallium gets to choose the interface it needs, and the
 365      * window systems must then implement that interface (rather than the
 366      * other way around...).
 367      *************************************************************************/
 368
 369     /**
 370      * Create a buffer object.
 371      *
 372      * \param ws        The winsys this function is called from.
 373      * \param size      The size to allocate.
 374      * \param alignment An alignment of the buffer in memory.
 375      * \param use_reusable_pool Whether the cache buffer manager should be used.
 376      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 377      * \return          The created buffer object.
 378      */
 379     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 380                                        unsigned size,
 381                                        unsigned alignment,
 382                                        boolean use_reusable_pool,
 383                                        enum radeon_bo_domain domain,
 384                                        enum radeon_bo_flag flags);
 385
 386     struct radeon_winsys_cs_handle *(*buffer_get_cs_handle)(
 387             struct pb_buffer *buf);
 388
 389     /**
 390      * Map the entire data store of a buffer object into the client's address
 391      * space.
 392      *
 393      * \param buf       A winsys buffer object to map.
 394      * \param cs        A command stream to flush if the buffer is referenced by it.
 395      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 396      * \return          The pointer at the beginning of the buffer.
 397      */
 398     void *(*buffer_map)(struct radeon_winsys_cs_handle *buf,
 399                         struct radeon_winsys_cs *cs,
 400                         enum pipe_transfer_usage usage);
 401
 402     /**
 403      * Unmap a buffer object from the client's address space.
 404      *
 405      * \param buf       A winsys buffer object to unmap.
 406      */
 407     void (*buffer_unmap)(struct radeon_winsys_cs_handle *buf);
 408
 409     /**
 410      * Wait for the buffer and return true if the buffer is not used
 411      * by the device.
 412      *
 413      * The timeout of 0 will only return the status.
 414      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
 415      * is idle.
 416      */
 417     bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
 418                         enum radeon_bo_usage usage);
 419
 420     /**
 421      * Return tiling flags describing a memory layout of a buffer object.
 422      *
 423      * \param buf       A winsys buffer object to get the flags from.
 424      * \param macrotile A pointer to the return value of the microtile flag.
 425      * \param microtile A pointer to the return value of the macrotile flag.
 426      *
 427      * \note microtile and macrotile are not bitmasks!
 428      */
 429     void (*buffer_get_tiling)(struct pb_buffer *buf,
 430                               enum radeon_bo_layout *microtile,
 431                               enum radeon_bo_layout *macrotile,
 432                               unsigned *bankw, unsigned *bankh,
 433                               unsigned *tile_split,
 434                               unsigned *stencil_tile_split,
 435                               unsigned *mtilea,
 436                               bool *scanout);
 437
 438     /**
 439      * Set tiling flags describing a memory layout of a buffer object.
 440      *
 441      * \param buf       A winsys buffer object to set the flags for.
 442      * \param cs        A command stream to flush if the buffer is referenced by it.
 443      * \param macrotile A macrotile flag.
 444      * \param microtile A microtile flag.
 445      * \param stride    A stride of the buffer in bytes, for texturing.
 446      *
 447      * \note microtile and macrotile are not bitmasks!
 448      */
 449     void (*buffer_set_tiling)(struct pb_buffer *buf,
 450                               struct radeon_winsys_cs *rcs,
 451                               enum radeon_bo_layout microtile,
 452                               enum radeon_bo_layout macrotile,
 453                               unsigned pipe_config,
 454                               unsigned bankw, unsigned bankh,
 455                               unsigned tile_split,
 456                               unsigned stencil_tile_split,
 457                               unsigned mtilea, unsigned num_banks,
 458                               unsigned stride,
 459                               bool scanout);
 460
 461     /**
 462      * Get a winsys buffer from a winsys handle. The internal structure
 463      * of the handle is platform-specific and only a winsys should access it.
 464      *
 465      * \param ws        The winsys this function is called from.
 466      * \param whandle   A winsys handle pointer as was received from a state
 467      *                  tracker.
 468      * \param stride    The returned buffer stride in bytes.
 469      */
 470     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 471                                             struct winsys_handle *whandle,
 472                                             unsigned *stride);
 473
 474     /**
 475      * Get a winsys buffer from a user pointer. The resulting buffer can't
 476      * be exported. Both pointer and size must be page aligned.
 477      *
 478      * \param ws        The winsys this function is called from.
 479      * \param pointer   User pointer to turn into a buffer object.
 480      * \param Size      Size in bytes for the new buffer.
 481      */
 482     struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
 483                                          void *pointer, unsigned size);
 484
 485     /**
 486      * Get a winsys handle from a winsys buffer. The internal structure
 487      * of the handle is platform-specific and only a winsys should access it.
 488      *
 489      * \param buf       A winsys buffer object to get the handle from.
 490      * \param whandle   A winsys handle pointer.
 491      * \param stride    A stride of the buffer in bytes, for texturing.
 492      * \return          TRUE on success.
 493      */
 494     boolean (*buffer_get_handle)(struct pb_buffer *buf,
 495                                  unsigned stride,
 496                                  struct winsys_handle *whandle);
 497
 498     /**
 499      * Return the virtual address of a buffer.
 500      *
 501      * \param buf       A winsys buffer object
 502      * \return          virtual address
 503      */
 504     uint64_t (*buffer_get_virtual_address)(struct radeon_winsys_cs_handle *buf);
 505
 506     /**
 507      * Query the initial placement of the buffer from the kernel driver.
 508      */
 509     enum radeon_bo_domain (*buffer_get_initial_domain)(struct radeon_winsys_cs_handle *buf);
 510
 511     /**************************************************************************
 512      * Command submission.
 513      *
 514      * Each pipe context should create its own command stream and submit
 515      * commands independently of other contexts.
 516      *************************************************************************/
 517
 518     /**
 519      * Create a command submission context.
 520      * Various command streams can be submitted to the same context.
 521      */
 522     struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 523
 524     /**
 525      * Destroy a context.
 526      */
 527     void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 528
 529     /**
 530      * Query a GPU reset status.
 531      */
 532     enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
 533
 534     /**
 535      * Create a command stream.
 536      *
 537      * \param ctx       The submission context
 538      * \param ring_type The ring type (GFX, DMA, UVD)
 539      * \param flush     Flush callback function associated with the command stream.
 540      * \param user      User pointer that will be passed to the flush callback.
 541      * \param trace_buf Trace buffer when tracing is enabled
 542      */
 543     struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys_ctx *ctx,
 544                                           enum ring_type ring_type,
 545                                           void (*flush)(void *ctx, unsigned flags,
 546                                                         struct pipe_fence_handle **fence),
 547                                           void *flush_ctx,
 548                                           struct radeon_winsys_cs_handle *trace_buf);
 549
 550     /**
 551      * Destroy a command stream.
 552      *
 553      * \param cs        A command stream to destroy.
 554      */
 555     void (*cs_destroy)(struct radeon_winsys_cs *cs);
 556
 557     /**
 558      * Add a new buffer relocation. Every relocation must first be added
 559      * before it can be written.
 560      *
 561      * \param cs  A command stream to add buffer for validation against.
 562      * \param buf A winsys buffer to validate.
 563      * \param usage   Whether the buffer is used for read and/or write.
 564      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 565      * \param priority  A higher number means a greater chance of being
 566      *                  placed in the requested domain. 15 is the maximum.
 567      * \return Relocation index.
 568      */
 569     unsigned (*cs_add_reloc)(struct radeon_winsys_cs *cs,
 570                              struct radeon_winsys_cs_handle *buf,
 571                              enum radeon_bo_usage usage,
 572                              enum radeon_bo_domain domain,
 573                              enum radeon_bo_priority priority);
 574
 575     /**
 576      * Return the index of an already-added buffer.
 577      *
 578      * \param cs        Command stream
 579      * \param buf       Buffer
 580      * \return          The buffer index, or -1 if the buffer has not been added.
 581      */
 582     int (*cs_get_reloc)(struct radeon_winsys_cs *cs,
 583                         struct radeon_winsys_cs_handle *buf);
 584
 585     /**
 586      * Return TRUE if there is enough memory in VRAM and GTT for the relocs
 587      * added so far. If the validation fails, all the relocations which have
 588      * been added since the last call of cs_validate will be removed and
 589      * the CS will be flushed (provided there are still any relocations).
 590      *
 591      * \param cs        A command stream to validate.
 592      */
 593     boolean (*cs_validate)(struct radeon_winsys_cs *cs);
 594
 595     /**
 596      * Return TRUE if there is enough memory in VRAM and GTT for the relocs
 597      * added so far.
 598      *
 599      * \param cs        A command stream to validate.
 600      * \param vram      VRAM memory size pending to be use
 601      * \param gtt       GTT memory size pending to be use
 602      */
 603     boolean (*cs_memory_below_limit)(struct radeon_winsys_cs *cs, uint64_t vram, uint64_t gtt);
 604
 605     /**
 606      * Flush a command stream.
 607      *
 608      * \param cs          A command stream to flush.
 609      * \param flags,      RADEON_FLUSH_ASYNC or 0.
 610      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 611      *                    after the CS and is returned through this parameter.
 612      * \param cs_trace_id A unique identifier of the cs, used for tracing.
 613      */
 614     void (*cs_flush)(struct radeon_winsys_cs *cs,
 615                      unsigned flags,
 616                      struct pipe_fence_handle **fence,
 617                      uint32_t cs_trace_id);
 618
 619     /**
 620      * Return TRUE if a buffer is referenced by a command stream.
 621      *
 622      * \param cs        A command stream.
 623      * \param buf       A winsys buffer.
 624      */
 625     boolean (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
 626                                        struct radeon_winsys_cs_handle *buf,
 627                                        enum radeon_bo_usage usage);
 628
 629     /**
 630      * Request access to a feature for a command stream.
 631      *
 632      * \param cs        A command stream.
 633      * \param fid       Feature ID, one of RADEON_FID_*
 634      * \param enable    Whether to enable or disable the feature.
 635      */
 636     boolean (*cs_request_feature)(struct radeon_winsys_cs *cs,
 637                                   enum radeon_feature_id fid,
 638                                   boolean enable);
 639      /**
 640       * Make sure all asynchronous flush of the cs have completed
 641       *
 642       * \param cs        A command stream.
 643       */
 644     void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
 645
 646     /**
 647      * Wait for the fence and return true if the fence has been signalled.
 648      * The timeout of 0 will only return the status.
 649      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 650      * is signalled.
 651      */
 652     bool (*fence_wait)(struct radeon_winsys *ws,
 653                        struct pipe_fence_handle *fence,
 654                        uint64_t timeout);
 655
 656     /**
 657      * Reference counting for fences.
 658      */
 659     void (*fence_reference)(struct pipe_fence_handle **dst,
 660                             struct pipe_fence_handle *src);
 661
 662     /**
 663      * Initialize surface
 664      *
 665      * \param ws        The winsys this function is called from.
 666      * \param surf      Surface structure ptr
 667      */
 668     int (*surface_init)(struct radeon_winsys *ws,
 669                         struct radeon_surf *surf);
 670
 671     /**
 672      * Find best values for a surface
 673      *
 674      * \param ws        The winsys this function is called from.
 675      * \param surf      Surface structure ptr
 676      */
 677     int (*surface_best)(struct radeon_winsys *ws,
 678                         struct radeon_surf *surf);
 679
 680     uint64_t (*query_value)(struct radeon_winsys *ws,
 681                             enum radeon_value_id value);
 682
 683     void (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 684                            unsigned num_registers, uint32_t *out);
 685 };
 686
 687
 688 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 689 {
 690     cs->buf[cs->cdw++] = value;
 691 }
 692
 693 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 694                                      const uint32_t *values, unsigned count)
 695 {
 696     memcpy(cs->buf+cs->cdw, values, count * 4);
 697     cs->cdw += count;
 698 }
 699
 700 #endif