2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
4 * Copyright 2018 Advanced Micro Devices, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * on the rights to use, copy, modify, merge, publish, distribute, sub
11 * license, and/or sell copies of the Software, and to permit persons to whom
12 * the Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
26 #ifndef RADEON_WINSYS_H
27 #define RADEON_WINSYS_H
29 /* The public winsys interface header for the radeon driver. */
31 /* Whether the next IB can start immediately and not wait for draws and
32 * dispatches from the current IB to finish. */
33 #define RADEON_FLUSH_START_NEXT_GFX_IB_NOW (1u << 31)
35 #define RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW \
36 (PIPE_FLUSH_ASYNC | RADEON_FLUSH_START_NEXT_GFX_IB_NOW)
38 #include "pipebuffer/pb_buffer.h"
40 #include "amd/common/ac_gpu_info.h"
41 #include "amd/common/ac_surface.h"
44 enum radeon_bo_layout
{
45 RADEON_LAYOUT_LINEAR
= 0,
47 RADEON_LAYOUT_SQUARETILED
,
52 enum radeon_bo_domain
{ /* bitfield */
53 RADEON_DOMAIN_GTT
= 2,
54 RADEON_DOMAIN_VRAM
= 4,
55 RADEON_DOMAIN_VRAM_GTT
= RADEON_DOMAIN_VRAM
| RADEON_DOMAIN_GTT
,
56 RADEON_DOMAIN_GDS
= 8,
57 RADEON_DOMAIN_OA
= 16,
60 enum radeon_bo_flag
{ /* bitfield */
61 RADEON_FLAG_GTT_WC
= (1 << 0),
62 RADEON_FLAG_NO_CPU_ACCESS
= (1 << 1),
63 RADEON_FLAG_NO_SUBALLOC
= (1 << 2),
64 RADEON_FLAG_SPARSE
= (1 << 3),
65 RADEON_FLAG_NO_INTERPROCESS_SHARING
= (1 << 4),
66 RADEON_FLAG_READ_ONLY
= (1 << 5),
67 RADEON_FLAG_32BIT
= (1 << 6),
70 enum radeon_bo_usage
{ /* bitfield */
71 RADEON_USAGE_READ
= 2,
72 RADEON_USAGE_WRITE
= 4,
73 RADEON_USAGE_READWRITE
= RADEON_USAGE_READ
| RADEON_USAGE_WRITE
,
75 /* The winsys ensures that the CS submission will be scheduled after
76 * previously flushed CSs referencing this BO in a conflicting way.
78 RADEON_USAGE_SYNCHRONIZED
= 8
81 enum radeon_transfer_flags
{
82 /* Indicates that the caller will unmap the buffer.
84 * Not unmapping buffers is an important performance optimization for
85 * OpenGL (avoids kernel overhead for frequently mapped buffers).
87 RADEON_TRANSFER_TEMPORARY
= (PIPE_TRANSFER_DRV_PRV
<< 0),
90 #define RADEON_SPARSE_PAGE_SIZE (64 * 1024)
105 enum radeon_value_id
{
106 RADEON_REQUESTED_VRAM_MEMORY
,
107 RADEON_REQUESTED_GTT_MEMORY
,
110 RADEON_BUFFER_WAIT_TIME_NS
,
111 RADEON_NUM_MAPPED_BUFFERS
,
115 RADEON_GFX_BO_LIST_COUNTER
, /* number of BOs submitted in gfx IBs */
116 RADEON_GFX_IB_SIZE_COUNTER
,
117 RADEON_NUM_BYTES_MOVED
,
118 RADEON_NUM_EVICTIONS
,
119 RADEON_NUM_VRAM_CPU_PAGE_FAULTS
,
121 RADEON_VRAM_VIS_USAGE
,
123 RADEON_GPU_TEMPERATURE
, /* DRM 2.42.0 */
126 RADEON_GPU_RESET_COUNTER
, /* DRM 2.43.0 */
127 RADEON_CS_THREAD_TIME
,
130 enum radeon_bo_priority
{
131 /* Each group of two has the same priority. */
132 RADEON_PRIO_FENCE
= 0,
135 RADEON_PRIO_SO_FILLED_SIZE
= 2,
138 RADEON_PRIO_IB1
= 4, /* main IB submitted to the kernel */
139 RADEON_PRIO_IB2
, /* IB executed with INDIRECT_BUFFER */
141 RADEON_PRIO_DRAW_INDIRECT
= 6,
142 RADEON_PRIO_INDEX_BUFFER
,
144 RADEON_PRIO_CP_DMA
= 8,
145 RADEON_PRIO_BORDER_COLORS
,
147 RADEON_PRIO_CONST_BUFFER
= 10,
148 RADEON_PRIO_DESCRIPTORS
,
150 RADEON_PRIO_SAMPLER_BUFFER
= 12,
151 RADEON_PRIO_VERTEX_BUFFER
,
153 RADEON_PRIO_SHADER_RW_BUFFER
= 14,
154 RADEON_PRIO_COMPUTE_GLOBAL
,
156 RADEON_PRIO_SAMPLER_TEXTURE
= 16,
157 RADEON_PRIO_SHADER_RW_IMAGE
,
159 RADEON_PRIO_SAMPLER_TEXTURE_MSAA
= 18,
160 RADEON_PRIO_COLOR_BUFFER
,
162 RADEON_PRIO_DEPTH_BUFFER
= 20,
164 RADEON_PRIO_COLOR_BUFFER_MSAA
= 22,
166 RADEON_PRIO_DEPTH_BUFFER_MSAA
= 24,
168 RADEON_PRIO_SEPARATE_META
= 26,
169 RADEON_PRIO_SHADER_BINARY
, /* the hw can't hide instruction cache misses */
171 RADEON_PRIO_SHADER_RINGS
= 28,
173 RADEON_PRIO_SCRATCH_BUFFER
= 30,
174 /* 31 is the maximum value */
177 struct winsys_handle
;
178 struct radeon_winsys_ctx
;
180 struct radeon_cmdbuf_chunk
{
181 unsigned cdw
; /* Number of used dwords. */
182 unsigned max_dw
; /* Maximum number of dwords. */
183 uint32_t *buf
; /* The base pointer of the chunk. */
186 struct radeon_cmdbuf
{
187 struct radeon_cmdbuf_chunk current
;
188 struct radeon_cmdbuf_chunk
*prev
;
189 unsigned num_prev
; /* Number of previous chunks. */
190 unsigned max_prev
; /* Space in array pointed to by prev. */
191 unsigned prev_dw
; /* Total number of dwords in previous chunks. */
193 /* Memory usage of the buffer list. These are always 0 for preamble IBs. */
198 /* Tiling info for display code, DRI sharing, and other data. */
199 struct radeon_bo_metadata
{
200 /* Tiling flags describing the texture layout for display code
205 enum radeon_bo_layout microtile
;
206 enum radeon_bo_layout macrotile
;
207 unsigned pipe_config
;
219 unsigned swizzle_mode
:5;
223 /* Additional metadata associated with the buffer, in bytes.
224 * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
225 * Supported by amdgpu only.
227 uint32_t size_metadata
;
228 uint32_t metadata
[64];
231 enum radeon_feature_id
{
232 RADEON_FID_R300_HYPERZ_ACCESS
, /* ZMask + HiZ */
233 RADEON_FID_R300_CMASK_ACCESS
,
236 struct radeon_bo_list_item
{
239 uint32_t priority_usage
; /* mask of (1 << RADEON_PRIO_*) */
242 struct radeon_winsys
{
244 * The screen object this winsys was created for
246 struct pipe_screen
*screen
;
249 * Decrement the winsys reference count.
251 * \param ws The winsys this function is called for.
252 * \return True if the winsys and screen should be destroyed.
254 bool (*unref
)(struct radeon_winsys
*ws
);
257 * Destroy this winsys.
259 * \param ws The winsys this function is called from.
261 void (*destroy
)(struct radeon_winsys
*ws
);
264 * Query an info structure from winsys.
266 * \param ws The winsys this function is called from.
267 * \param info Return structure
269 void (*query_info
)(struct radeon_winsys
*ws
,
270 struct radeon_info
*info
);
273 * A hint for the winsys that it should pin its execution threads to
274 * a group of cores sharing a specific L3 cache if the CPU has multiple
275 * L3 caches. This is needed for good multithreading performance on
278 void (*pin_threads_to_L3_cache
)(struct radeon_winsys
*ws
, unsigned cache
);
280 /**************************************************************************
281 * Buffer management. Buffer attributes are mostly fixed over its lifetime.
283 * Remember that gallium gets to choose the interface it needs, and the
284 * window systems must then implement that interface (rather than the
285 * other way around...).
286 *************************************************************************/
289 * Create a buffer object.
291 * \param ws The winsys this function is called from.
292 * \param size The size to allocate.
293 * \param alignment An alignment of the buffer in memory.
294 * \param use_reusable_pool Whether the cache buffer manager should be used.
295 * \param domain A bitmask of the RADEON_DOMAIN_* flags.
296 * \return The created buffer object.
298 struct pb_buffer
*(*buffer_create
)(struct radeon_winsys
*ws
,
301 enum radeon_bo_domain domain
,
302 enum radeon_bo_flag flags
);
305 * Map the entire data store of a buffer object into the client's address
308 * Callers are expected to unmap buffers again if and only if the
309 * RADEON_TRANSFER_TEMPORARY flag is set in \p usage.
311 * \param buf A winsys buffer object to map.
312 * \param cs A command stream to flush if the buffer is referenced by it.
313 * \param usage A bitmask of the PIPE_TRANSFER_* and RADEON_TRANSFER_* flags.
314 * \return The pointer at the beginning of the buffer.
316 void *(*buffer_map
)(struct pb_buffer
*buf
,
317 struct radeon_cmdbuf
*cs
,
318 enum pipe_transfer_usage usage
);
321 * Unmap a buffer object from the client's address space.
323 * \param buf A winsys buffer object to unmap.
325 void (*buffer_unmap
)(struct pb_buffer
*buf
);
328 * Wait for the buffer and return true if the buffer is not used
331 * The timeout of 0 will only return the status.
332 * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
335 bool (*buffer_wait
)(struct pb_buffer
*buf
, uint64_t timeout
,
336 enum radeon_bo_usage usage
);
339 * Return buffer metadata.
340 * (tiling info for display code, DRI sharing, and other data)
342 * \param buf A winsys buffer object to get the flags from.
345 void (*buffer_get_metadata
)(struct pb_buffer
*buf
,
346 struct radeon_bo_metadata
*md
);
349 * Set buffer metadata.
350 * (tiling info for display code, DRI sharing, and other data)
352 * \param buf A winsys buffer object to set the flags for.
355 void (*buffer_set_metadata
)(struct pb_buffer
*buf
,
356 struct radeon_bo_metadata
*md
);
359 * Get a winsys buffer from a winsys handle. The internal structure
360 * of the handle is platform-specific and only a winsys should access it.
362 * \param ws The winsys this function is called from.
363 * \param whandle A winsys handle pointer as was received from a state
365 * \param stride The returned buffer stride in bytes.
367 struct pb_buffer
*(*buffer_from_handle
)(struct radeon_winsys
*ws
,
368 struct winsys_handle
*whandle
,
369 unsigned vm_alignment
,
370 unsigned *stride
, unsigned *offset
);
373 * Get a winsys buffer from a user pointer. The resulting buffer can't
374 * be exported. Both pointer and size must be page aligned.
376 * \param ws The winsys this function is called from.
377 * \param pointer User pointer to turn into a buffer object.
378 * \param Size Size in bytes for the new buffer.
380 struct pb_buffer
*(*buffer_from_ptr
)(struct radeon_winsys
*ws
,
381 void *pointer
, uint64_t size
);
384 * Whether the buffer was created from a user pointer.
386 * \param buf A winsys buffer object
387 * \return whether \p buf was created via buffer_from_ptr
389 bool (*buffer_is_user_ptr
)(struct pb_buffer
*buf
);
391 /** Whether the buffer was suballocated. */
392 bool (*buffer_is_suballocated
)(struct pb_buffer
*buf
);
395 * Get a winsys handle from a winsys buffer. The internal structure
396 * of the handle is platform-specific and only a winsys should access it.
398 * \param buf A winsys buffer object to get the handle from.
399 * \param whandle A winsys handle pointer.
400 * \param stride A stride of the buffer in bytes, for texturing.
401 * \return true on success.
403 bool (*buffer_get_handle
)(struct pb_buffer
*buf
,
404 unsigned stride
, unsigned offset
,
406 struct winsys_handle
*whandle
);
409 * Change the commitment of a (64KB-page aligned) region of the given
412 * \warning There is no automatic synchronization with command submission.
414 * \note Only implemented by the amdgpu winsys.
416 * \return false on out of memory or other failure, true on success.
418 bool (*buffer_commit
)(struct pb_buffer
*buf
,
419 uint64_t offset
, uint64_t size
,
423 * Return the virtual address of a buffer.
425 * When virtual memory is not in use, this is the offset relative to the
426 * relocation base (non-zero for sub-allocated buffers).
428 * \param buf A winsys buffer object
429 * \return virtual address
431 uint64_t (*buffer_get_virtual_address
)(struct pb_buffer
*buf
);
434 * Return the offset of this buffer relative to the relocation base.
435 * This is only non-zero for sub-allocated buffers.
437 * This is only supported in the radeon winsys, since amdgpu uses virtual
438 * addresses in submissions even for the video engines.
440 * \param buf A winsys buffer object
441 * \return the offset for relocations
443 unsigned (*buffer_get_reloc_offset
)(struct pb_buffer
*buf
);
446 * Query the initial placement of the buffer from the kernel driver.
448 enum radeon_bo_domain (*buffer_get_initial_domain
)(struct pb_buffer
*buf
);
450 /**************************************************************************
451 * Command submission.
453 * Each pipe context should create its own command stream and submit
454 * commands independently of other contexts.
455 *************************************************************************/
458 * Create a command submission context.
459 * Various command streams can be submitted to the same context.
461 struct radeon_winsys_ctx
*(*ctx_create
)(struct radeon_winsys
*ws
);
466 void (*ctx_destroy
)(struct radeon_winsys_ctx
*ctx
);
469 * Query a GPU reset status.
471 enum pipe_reset_status (*ctx_query_reset_status
)(struct radeon_winsys_ctx
*ctx
);
474 * Create a command stream.
476 * \param ctx The submission context
477 * \param ring_type The ring type (GFX, DMA, UVD)
478 * \param flush Flush callback function associated with the command stream.
479 * \param user User pointer that will be passed to the flush callback.
481 struct radeon_cmdbuf
*(*cs_create
)(struct radeon_winsys_ctx
*ctx
,
482 enum ring_type ring_type
,
483 void (*flush
)(void *ctx
, unsigned flags
,
484 struct pipe_fence_handle
**fence
),
486 bool stop_exec_on_failure
);
489 * Destroy a command stream.
491 * \param cs A command stream to destroy.
493 void (*cs_destroy
)(struct radeon_cmdbuf
*cs
);
496 * Add a buffer. Each buffer used by a CS must be added using this function.
498 * \param cs Command stream
500 * \param usage Whether the buffer is used for read and/or write.
501 * \param domain Bitmask of the RADEON_DOMAIN_* flags.
502 * \param priority A higher number means a greater chance of being
503 * placed in the requested domain. 15 is the maximum.
504 * \return Buffer index.
506 unsigned (*cs_add_buffer
)(struct radeon_cmdbuf
*cs
,
507 struct pb_buffer
*buf
,
508 enum radeon_bo_usage usage
,
509 enum radeon_bo_domain domain
,
510 enum radeon_bo_priority priority
);
513 * Return the index of an already-added buffer.
515 * Not supported on amdgpu. Drivers with GPUVM should not care about
518 * \param cs Command stream
520 * \return The buffer index, or -1 if the buffer has not been added.
522 int (*cs_lookup_buffer
)(struct radeon_cmdbuf
*cs
,
523 struct pb_buffer
*buf
);
526 * Return true if there is enough memory in VRAM and GTT for the buffers
527 * added so far. If the validation fails, all buffers which have
528 * been added since the last call of cs_validate will be removed and
529 * the CS will be flushed (provided there are still any buffers).
531 * \param cs A command stream to validate.
533 bool (*cs_validate
)(struct radeon_cmdbuf
*cs
);
536 * Check whether the given number of dwords is available in the IB.
537 * Optionally chain a new chunk of the IB if necessary and supported.
539 * \param cs A command stream.
540 * \param dw Number of CS dwords requested by the caller.
542 bool (*cs_check_space
)(struct radeon_cmdbuf
*cs
, unsigned dw
);
545 * Return the buffer list.
547 * This is the buffer list as passed to the kernel, i.e. it only contains
548 * the parent buffers of sub-allocated buffers.
550 * \param cs Command stream
551 * \param list Returned buffer list. Set to NULL to query the count only.
552 * \return The buffer count.
554 unsigned (*cs_get_buffer_list
)(struct radeon_cmdbuf
*cs
,
555 struct radeon_bo_list_item
*list
);
558 * Flush a command stream.
560 * \param cs A command stream to flush.
561 * \param flags, PIPE_FLUSH_* flags.
562 * \param fence Pointer to a fence. If non-NULL, a fence is inserted
563 * after the CS and is returned through this parameter.
564 * \return Negative POSIX error code or 0 for success.
565 * Asynchronous submissions never return an error.
567 int (*cs_flush
)(struct radeon_cmdbuf
*cs
,
569 struct pipe_fence_handle
**fence
);
572 * Create a fence before the CS is flushed.
573 * The user must flush manually to complete the initializaton of the fence.
575 * The fence must not be used for anything except \ref cs_add_fence_dependency
578 struct pipe_fence_handle
*(*cs_get_next_fence
)(struct radeon_cmdbuf
*cs
);
581 * Return true if a buffer is referenced by a command stream.
583 * \param cs A command stream.
584 * \param buf A winsys buffer.
586 bool (*cs_is_buffer_referenced
)(struct radeon_cmdbuf
*cs
,
587 struct pb_buffer
*buf
,
588 enum radeon_bo_usage usage
);
591 * Request access to a feature for a command stream.
593 * \param cs A command stream.
594 * \param fid Feature ID, one of RADEON_FID_*
595 * \param enable Whether to enable or disable the feature.
597 bool (*cs_request_feature
)(struct radeon_cmdbuf
*cs
,
598 enum radeon_feature_id fid
,
601 * Make sure all asynchronous flush of the cs have completed
603 * \param cs A command stream.
605 void (*cs_sync_flush
)(struct radeon_cmdbuf
*cs
);
608 * Add a fence dependency to the CS, so that the CS will wait for
609 * the fence before execution.
611 void (*cs_add_fence_dependency
)(struct radeon_cmdbuf
*cs
,
612 struct pipe_fence_handle
*fence
);
615 * Signal a syncobj when the CS finishes execution.
617 void (*cs_add_syncobj_signal
)(struct radeon_cmdbuf
*cs
,
618 struct pipe_fence_handle
*fence
);
621 * Wait for the fence and return true if the fence has been signalled.
622 * The timeout of 0 will only return the status.
623 * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
626 bool (*fence_wait
)(struct radeon_winsys
*ws
,
627 struct pipe_fence_handle
*fence
,
631 * Reference counting for fences.
633 void (*fence_reference
)(struct pipe_fence_handle
**dst
,
634 struct pipe_fence_handle
*src
);
637 * Create a new fence object corresponding to the given syncobj fd.
639 struct pipe_fence_handle
*(*fence_import_syncobj
)(struct radeon_winsys
*ws
,
643 * Create a new fence object corresponding to the given sync_file.
645 struct pipe_fence_handle
*(*fence_import_sync_file
)(struct radeon_winsys
*ws
,
649 * Return a sync_file FD corresponding to the given fence object.
651 int (*fence_export_sync_file
)(struct radeon_winsys
*ws
,
652 struct pipe_fence_handle
*fence
);
655 * Return a sync file FD that is already signalled.
657 int (*export_signalled_sync_file
)(struct radeon_winsys
*ws
);
662 * \param ws The winsys this function is called from.
663 * \param tex Input texture description
664 * \param flags Bitmask of RADEON_SURF_* flags
665 * \param bpe Bytes per pixel, it can be different for Z buffers.
666 * \param mode Preferred tile mode. (linear, 1D, or 2D)
667 * \param surf Output structure
669 int (*surface_init
)(struct radeon_winsys
*ws
,
670 const struct pipe_resource
*tex
,
671 unsigned flags
, unsigned bpe
,
672 enum radeon_surf_mode mode
,
673 struct radeon_surf
*surf
);
675 uint64_t (*query_value
)(struct radeon_winsys
*ws
,
676 enum radeon_value_id value
);
678 bool (*read_registers
)(struct radeon_winsys
*ws
, unsigned reg_offset
,
679 unsigned num_registers
, uint32_t *out
);
681 const char* (*get_chip_name
)(struct radeon_winsys
*ws
);
684 static inline bool radeon_emitted(struct radeon_cmdbuf
*cs
, unsigned num_dw
)
686 return cs
&& (cs
->prev_dw
+ cs
->current
.cdw
> num_dw
);
689 static inline void radeon_emit(struct radeon_cmdbuf
*cs
, uint32_t value
)
691 cs
->current
.buf
[cs
->current
.cdw
++] = value
;
694 static inline void radeon_emit_array(struct radeon_cmdbuf
*cs
,
695 const uint32_t *values
, unsigned count
)
697 memcpy(cs
->current
.buf
+ cs
->current
.cdw
, values
, count
* 4);
698 cs
->current
.cdw
+= count
;
702 RADEON_HEAP_VRAM_NO_CPU_ACCESS
,
703 RADEON_HEAP_VRAM_READ_ONLY
,
704 RADEON_HEAP_VRAM_READ_ONLY_32BIT
,
705 RADEON_HEAP_VRAM_32BIT
,
708 RADEON_HEAP_GTT_WC_READ_ONLY
,
709 RADEON_HEAP_GTT_WC_READ_ONLY_32BIT
,
710 RADEON_HEAP_GTT_WC_32BIT
,
712 RADEON_MAX_SLAB_HEAPS
,
713 RADEON_MAX_CACHED_HEAPS
= RADEON_MAX_SLAB_HEAPS
,
716 static inline enum radeon_bo_domain
radeon_domain_from_heap(enum radeon_heap heap
)
719 case RADEON_HEAP_VRAM_NO_CPU_ACCESS
:
720 case RADEON_HEAP_VRAM_READ_ONLY
:
721 case RADEON_HEAP_VRAM_READ_ONLY_32BIT
:
722 case RADEON_HEAP_VRAM_32BIT
:
723 case RADEON_HEAP_VRAM
:
724 return RADEON_DOMAIN_VRAM
;
725 case RADEON_HEAP_GTT_WC
:
726 case RADEON_HEAP_GTT_WC_READ_ONLY
:
727 case RADEON_HEAP_GTT_WC_READ_ONLY_32BIT
:
728 case RADEON_HEAP_GTT_WC_32BIT
:
729 case RADEON_HEAP_GTT
:
730 return RADEON_DOMAIN_GTT
;
733 return (enum radeon_bo_domain
)0;
737 static inline unsigned radeon_flags_from_heap(enum radeon_heap heap
)
739 unsigned flags
= RADEON_FLAG_NO_INTERPROCESS_SHARING
|
740 (heap
!= RADEON_HEAP_GTT
? RADEON_FLAG_GTT_WC
: 0);
743 case RADEON_HEAP_VRAM_NO_CPU_ACCESS
:
745 RADEON_FLAG_NO_CPU_ACCESS
;
747 case RADEON_HEAP_VRAM_READ_ONLY
:
748 case RADEON_HEAP_GTT_WC_READ_ONLY
:
750 RADEON_FLAG_READ_ONLY
;
752 case RADEON_HEAP_VRAM_READ_ONLY_32BIT
:
753 case RADEON_HEAP_GTT_WC_READ_ONLY_32BIT
:
755 RADEON_FLAG_READ_ONLY
|
758 case RADEON_HEAP_VRAM_32BIT
:
759 case RADEON_HEAP_GTT_WC_32BIT
:
763 case RADEON_HEAP_VRAM
:
764 case RADEON_HEAP_GTT_WC
:
765 case RADEON_HEAP_GTT
:
771 /* Return the heap index for winsys allocators, or -1 on failure. */
772 static inline int radeon_get_heap_index(enum radeon_bo_domain domain
,
773 enum radeon_bo_flag flags
)
775 /* VRAM implies WC (write combining) */
776 assert(!(domain
& RADEON_DOMAIN_VRAM
) || flags
& RADEON_FLAG_GTT_WC
);
777 /* NO_CPU_ACCESS implies VRAM only. */
778 assert(!(flags
& RADEON_FLAG_NO_CPU_ACCESS
) || domain
== RADEON_DOMAIN_VRAM
);
780 /* Resources with interprocess sharing don't use any winsys allocators. */
781 if (!(flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
))
784 /* Unsupported flags: NO_SUBALLOC, SPARSE. */
785 if (flags
& ~(RADEON_FLAG_GTT_WC
|
786 RADEON_FLAG_NO_CPU_ACCESS
|
787 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
788 RADEON_FLAG_READ_ONLY
|
793 case RADEON_DOMAIN_VRAM
:
794 switch (flags
& (RADEON_FLAG_NO_CPU_ACCESS
|
795 RADEON_FLAG_READ_ONLY
|
796 RADEON_FLAG_32BIT
)) {
797 case RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_READ_ONLY
| RADEON_FLAG_32BIT
:
798 case RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_READ_ONLY
:
799 assert(!"NO_CPU_ACCESS | READ_ONLY doesn't make sense");
801 case RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_32BIT
:
802 assert(!"NO_CPU_ACCESS with 32BIT is disallowed");
804 case RADEON_FLAG_NO_CPU_ACCESS
:
805 return RADEON_HEAP_VRAM_NO_CPU_ACCESS
;
806 case RADEON_FLAG_READ_ONLY
| RADEON_FLAG_32BIT
:
807 return RADEON_HEAP_VRAM_READ_ONLY_32BIT
;
808 case RADEON_FLAG_READ_ONLY
:
809 return RADEON_HEAP_VRAM_READ_ONLY
;
810 case RADEON_FLAG_32BIT
:
811 return RADEON_HEAP_VRAM_32BIT
;
813 return RADEON_HEAP_VRAM
;
816 case RADEON_DOMAIN_GTT
:
817 switch (flags
& (RADEON_FLAG_GTT_WC
|
818 RADEON_FLAG_READ_ONLY
|
819 RADEON_FLAG_32BIT
)) {
820 case RADEON_FLAG_GTT_WC
| RADEON_FLAG_READ_ONLY
| RADEON_FLAG_32BIT
:
821 return RADEON_HEAP_GTT_WC_READ_ONLY_32BIT
;
822 case RADEON_FLAG_GTT_WC
| RADEON_FLAG_READ_ONLY
:
823 return RADEON_HEAP_GTT_WC_READ_ONLY
;
824 case RADEON_FLAG_GTT_WC
| RADEON_FLAG_32BIT
:
825 return RADEON_HEAP_GTT_WC_32BIT
;
826 case RADEON_FLAG_GTT_WC
:
827 return RADEON_HEAP_GTT_WC
;
828 case RADEON_FLAG_READ_ONLY
| RADEON_FLAG_32BIT
:
829 case RADEON_FLAG_READ_ONLY
:
830 assert(!"READ_ONLY without WC is disallowed");
832 case RADEON_FLAG_32BIT
:
833 assert(!"32BIT without WC is disallowed");
836 return RADEON_HEAP_GTT
;