src/gallium/drivers/radeon/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #ifndef RADEON_WINSYS_H
  25 #define RADEON_WINSYS_H
  26
  27 /* The public winsys interface header for the radeon driver. */
  28
  29 /* R300 features in DRM.
  30  *
  31  * 2.6.0:
  32  * - Hyper-Z
  33  * - GB_Z_PEQ_CONFIG on rv350->r4xx
  34  * - R500 FG_ALPHA_VALUE
  35  *
  36  * 2.8.0:
  37  * - R500 US_FORMAT regs
  38  * - R500 ARGB2101010 colorbuffer
  39  * - CMask and AA regs
  40  * - R16F/RG16F
  41  */
  42
  43 #include "pipebuffer/pb_buffer.h"
  44
  45 #define RADEON_FLUSH_ASYNC              (1 << 0)
  46 #define RADEON_FLUSH_KEEP_TILING_FLAGS  (1 << 1) /* needs DRM 2.12.0 */
  47 #define RADEON_FLUSH_COMPUTE            (1 << 2)
  48 #define RADEON_FLUSH_END_OF_FRAME       (1 << 3)
  49
  50 /* Tiling flags. */
  51 enum radeon_bo_layout {
  52     RADEON_LAYOUT_LINEAR = 0,
  53     RADEON_LAYOUT_TILED,
  54     RADEON_LAYOUT_SQUARETILED,
  55
  56     RADEON_LAYOUT_UNKNOWN
  57 };
  58
  59 enum radeon_bo_domain { /* bitfield */
  60     RADEON_DOMAIN_GTT  = 2,
  61     RADEON_DOMAIN_VRAM = 4,
  62     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  63 };
  64
  65 enum radeon_bo_flag { /* bitfield */
  66     RADEON_FLAG_GTT_WC =        (1 << 0),
  67     RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  68     RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  69 };
  70
  71 enum radeon_bo_usage { /* bitfield */
  72     RADEON_USAGE_READ = 2,
  73     RADEON_USAGE_WRITE = 4,
  74     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
  75 };
  76
  77 enum radeon_family {
  78     CHIP_UNKNOWN = 0,
  79     CHIP_R300, /* R3xx-based cores. */
  80     CHIP_R350,
  81     CHIP_RV350,
  82     CHIP_RV370,
  83     CHIP_RV380,
  84     CHIP_RS400,
  85     CHIP_RC410,
  86     CHIP_RS480,
  87     CHIP_R420,     /* R4xx-based cores. */
  88     CHIP_R423,
  89     CHIP_R430,
  90     CHIP_R480,
  91     CHIP_R481,
  92     CHIP_RV410,
  93     CHIP_RS600,
  94     CHIP_RS690,
  95     CHIP_RS740,
  96     CHIP_RV515,    /* R5xx-based cores. */
  97     CHIP_R520,
  98     CHIP_RV530,
  99     CHIP_R580,
 100     CHIP_RV560,
 101     CHIP_RV570,
 102     CHIP_R600,
 103     CHIP_RV610,
 104     CHIP_RV630,
 105     CHIP_RV670,
 106     CHIP_RV620,
 107     CHIP_RV635,
 108     CHIP_RS780,
 109     CHIP_RS880,
 110     CHIP_RV770,
 111     CHIP_RV730,
 112     CHIP_RV710,
 113     CHIP_RV740,
 114     CHIP_CEDAR,
 115     CHIP_REDWOOD,
 116     CHIP_JUNIPER,
 117     CHIP_CYPRESS,
 118     CHIP_HEMLOCK,
 119     CHIP_PALM,
 120     CHIP_SUMO,
 121     CHIP_SUMO2,
 122     CHIP_BARTS,
 123     CHIP_TURKS,
 124     CHIP_CAICOS,
 125     CHIP_CAYMAN,
 126     CHIP_ARUBA,
 127     CHIP_TAHITI,
 128     CHIP_PITCAIRN,
 129     CHIP_VERDE,
 130     CHIP_OLAND,
 131     CHIP_HAINAN,
 132     CHIP_BONAIRE,
 133     CHIP_KAVERI,
 134     CHIP_KABINI,
 135     CHIP_HAWAII,
 136     CHIP_MULLINS,
 137     CHIP_LAST,
 138 };
 139
 140 enum chip_class {
 141     CLASS_UNKNOWN = 0,
 142     R300,
 143     R400,
 144     R500,
 145     R600,
 146     R700,
 147     EVERGREEN,
 148     CAYMAN,
 149     SI,
 150     CIK,
 151 };
 152
 153 enum ring_type {
 154     RING_GFX = 0,
 155     RING_DMA,
 156     RING_UVD,
 157     RING_VCE,
 158     RING_LAST,
 159 };
 160
 161 enum radeon_value_id {
 162     RADEON_REQUESTED_VRAM_MEMORY,
 163     RADEON_REQUESTED_GTT_MEMORY,
 164     RADEON_BUFFER_WAIT_TIME_NS,
 165     RADEON_TIMESTAMP,
 166     RADEON_NUM_CS_FLUSHES,
 167     RADEON_NUM_BYTES_MOVED,
 168     RADEON_VRAM_USAGE,
 169     RADEON_GTT_USAGE,
 170     RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
 171     RADEON_CURRENT_SCLK,
 172     RADEON_CURRENT_MCLK,
 173     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
 174 };
 175
 176 enum radeon_bo_priority {
 177     RADEON_PRIO_MIN,
 178     RADEON_PRIO_SHADER_DATA, /* shader code, resource descriptors */
 179     RADEON_PRIO_SHADER_BUFFER_RO, /* read-only */
 180     RADEON_PRIO_SHADER_TEXTURE_RO, /* read-only */
 181     RADEON_PRIO_SHADER_RESOURCE_RW, /* buffers, textures, streamout, GS rings, RATs; read/write */
 182     RADEON_PRIO_COLOR_BUFFER,
 183     RADEON_PRIO_DEPTH_BUFFER,
 184     RADEON_PRIO_SHADER_TEXTURE_MSAA,
 185     RADEON_PRIO_COLOR_BUFFER_MSAA,
 186     RADEON_PRIO_DEPTH_BUFFER_MSAA,
 187     RADEON_PRIO_COLOR_META,
 188     RADEON_PRIO_DEPTH_META,
 189     RADEON_PRIO_MAX /* must be <= 15 */
 190 };
 191
 192 struct winsys_handle;
 193 struct radeon_winsys_cs_handle;
 194 struct radeon_winsys_ctx;
 195
 196 struct radeon_winsys_cs {
 197     unsigned                    cdw;  /* Number of used dwords. */
 198     unsigned                    max_dw; /* Maximum number of dwords. */
 199     uint32_t                    *buf; /* The command buffer. */
 200     enum ring_type              ring_type;
 201 };
 202
 203 struct radeon_info {
 204     uint32_t                    pci_id;
 205     enum radeon_family          family;
 206     enum chip_class             chip_class;
 207     uint64_t                    gart_size;
 208     uint64_t                    vram_size;
 209     uint32_t                    max_sclk;
 210     uint32_t                    max_compute_units;
 211     uint32_t                    max_se;
 212     uint32_t                    max_sh_per_se;
 213
 214     uint32_t                    drm_major; /* version */
 215     uint32_t                    drm_minor;
 216     uint32_t                    drm_patchlevel;
 217
 218     boolean                     has_uvd;
 219     uint32_t                    vce_fw_version;
 220     boolean                     has_userptr;
 221
 222     uint32_t                    r300_num_gb_pipes;
 223     uint32_t                    r300_num_z_pipes;
 224
 225     uint32_t                    r600_num_backends;
 226     uint32_t                    r600_clock_crystal_freq;
 227     uint32_t                    r600_tiling_config;
 228     uint32_t                    r600_num_tile_pipes;
 229     uint32_t                    r600_max_pipes;
 230     boolean                     r600_virtual_address;
 231     boolean                     r600_has_dma;
 232
 233     uint32_t                    r600_backend_map;
 234     boolean                     r600_backend_map_valid;
 235
 236     boolean                     si_tile_mode_array_valid;
 237     uint32_t                    si_tile_mode_array[32];
 238     uint32_t                    si_backend_enabled_mask;
 239
 240     boolean                     cik_macrotile_mode_array_valid;
 241     uint32_t                    cik_macrotile_mode_array[16];
 242 };
 243
 244 enum radeon_feature_id {
 245     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 246     RADEON_FID_R300_CMASK_ACCESS,
 247 };
 248
 249 #define RADEON_SURF_MAX_LEVEL                   32
 250
 251 #define RADEON_SURF_TYPE_MASK                   0xFF
 252 #define RADEON_SURF_TYPE_SHIFT                  0
 253 #define     RADEON_SURF_TYPE_1D                     0
 254 #define     RADEON_SURF_TYPE_2D                     1
 255 #define     RADEON_SURF_TYPE_3D                     2
 256 #define     RADEON_SURF_TYPE_CUBEMAP                3
 257 #define     RADEON_SURF_TYPE_1D_ARRAY               4
 258 #define     RADEON_SURF_TYPE_2D_ARRAY               5
 259 #define RADEON_SURF_MODE_MASK                   0xFF
 260 #define RADEON_SURF_MODE_SHIFT                  8
 261 #define     RADEON_SURF_MODE_LINEAR                 0
 262 #define     RADEON_SURF_MODE_LINEAR_ALIGNED         1
 263 #define     RADEON_SURF_MODE_1D                     2
 264 #define     RADEON_SURF_MODE_2D                     3
 265 #define RADEON_SURF_SCANOUT                     (1 << 16)
 266 #define RADEON_SURF_ZBUFFER                     (1 << 17)
 267 #define RADEON_SURF_SBUFFER                     (1 << 18)
 268 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
 269 #define RADEON_SURF_HAS_SBUFFER_MIPTREE         (1 << 19)
 270 #define RADEON_SURF_HAS_TILE_MODE_INDEX         (1 << 20)
 271 #define RADEON_SURF_FMASK                       (1 << 21)
 272
 273 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
 274 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
 275 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
 276
 277 struct radeon_surf_level {
 278     uint64_t                    offset;
 279     uint64_t                    slice_size;
 280     uint32_t                    npix_x;
 281     uint32_t                    npix_y;
 282     uint32_t                    npix_z;
 283     uint32_t                    nblk_x;
 284     uint32_t                    nblk_y;
 285     uint32_t                    nblk_z;
 286     uint32_t                    pitch_bytes;
 287     uint32_t                    mode;
 288 };
 289
 290 struct radeon_surf {
 291     /* These are inputs to the calculator. */
 292     uint32_t                    npix_x;
 293     uint32_t                    npix_y;
 294     uint32_t                    npix_z;
 295     uint32_t                    blk_w;
 296     uint32_t                    blk_h;
 297     uint32_t                    blk_d;
 298     uint32_t                    array_size;
 299     uint32_t                    last_level;
 300     uint32_t                    bpe;
 301     uint32_t                    nsamples;
 302     uint32_t                    flags;
 303
 304     /* These are return values. Some of them can be set by the caller, but
 305      * they will be treated as hints (e.g. bankw, bankh) and might be
 306      * changed by the calculator.
 307      */
 308     uint64_t                    bo_size;
 309     uint64_t                    bo_alignment;
 310     /* This applies to EG and later. */
 311     uint32_t                    bankw;
 312     uint32_t                    bankh;
 313     uint32_t                    mtilea;
 314     uint32_t                    tile_split;
 315     uint32_t                    stencil_tile_split;
 316     uint64_t                    stencil_offset;
 317     struct radeon_surf_level    level[RADEON_SURF_MAX_LEVEL];
 318     struct radeon_surf_level    stencil_level[RADEON_SURF_MAX_LEVEL];
 319     uint32_t                    tiling_index[RADEON_SURF_MAX_LEVEL];
 320     uint32_t                    stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
 321 };
 322
 323 struct radeon_winsys {
 324     /**
 325      * The screen object this winsys was created for
 326      */
 327     struct pipe_screen *screen;
 328
 329     /**
 330      * Decrement the winsys reference count.
 331      *
 332      * \param ws  The winsys this function is called for.
 333      * \return    True if the winsys and screen should be destroyed.
 334      */
 335     bool (*unref)(struct radeon_winsys *ws);
 336
 337     /**
 338      * Destroy this winsys.
 339      *
 340      * \param ws        The winsys this function is called from.
 341      */
 342     void (*destroy)(struct radeon_winsys *ws);
 343
 344     /**
 345      * Query an info structure from winsys.
 346      *
 347      * \param ws        The winsys this function is called from.
 348      * \param info      Return structure
 349      */
 350     void (*query_info)(struct radeon_winsys *ws,
 351                        struct radeon_info *info);
 352
 353     /**************************************************************************
 354      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 355      *
 356      * Remember that gallium gets to choose the interface it needs, and the
 357      * window systems must then implement that interface (rather than the
 358      * other way around...).
 359      *************************************************************************/
 360
 361     /**
 362      * Create a buffer object.
 363      *
 364      * \param ws        The winsys this function is called from.
 365      * \param size      The size to allocate.
 366      * \param alignment An alignment of the buffer in memory.
 367      * \param use_reusable_pool Whether the cache buffer manager should be used.
 368      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 369      * \return          The created buffer object.
 370      */
 371     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 372                                        unsigned size,
 373                                        unsigned alignment,
 374                                        boolean use_reusable_pool,
 375                                        enum radeon_bo_domain domain,
 376                                        enum radeon_bo_flag flags);
 377
 378     struct radeon_winsys_cs_handle *(*buffer_get_cs_handle)(
 379             struct pb_buffer *buf);
 380
 381     /**
 382      * Map the entire data store of a buffer object into the client's address
 383      * space.
 384      *
 385      * \param buf       A winsys buffer object to map.
 386      * \param cs        A command stream to flush if the buffer is referenced by it.
 387      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 388      * \return          The pointer at the beginning of the buffer.
 389      */
 390     void *(*buffer_map)(struct radeon_winsys_cs_handle *buf,
 391                         struct radeon_winsys_cs *cs,
 392                         enum pipe_transfer_usage usage);
 393
 394     /**
 395      * Unmap a buffer object from the client's address space.
 396      *
 397      * \param buf       A winsys buffer object to unmap.
 398      */
 399     void (*buffer_unmap)(struct radeon_winsys_cs_handle *buf);
 400
 401     /**
 402      * Wait for the buffer and return true if the buffer is not used
 403      * by the device.
 404      *
 405      * The timeout of 0 will only return the status.
 406      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
 407      * is idle.
 408      */
 409     bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
 410                         enum radeon_bo_usage usage);
 411
 412     /**
 413      * Return tiling flags describing a memory layout of a buffer object.
 414      *
 415      * \param buf       A winsys buffer object to get the flags from.
 416      * \param macrotile A pointer to the return value of the microtile flag.
 417      * \param microtile A pointer to the return value of the macrotile flag.
 418      *
 419      * \note microtile and macrotile are not bitmasks!
 420      */
 421     void (*buffer_get_tiling)(struct pb_buffer *buf,
 422                               enum radeon_bo_layout *microtile,
 423                               enum radeon_bo_layout *macrotile,
 424                               unsigned *bankw, unsigned *bankh,
 425                               unsigned *tile_split,
 426                               unsigned *stencil_tile_split,
 427                               unsigned *mtilea,
 428                               bool *scanout);
 429
 430     /**
 431      * Set tiling flags describing a memory layout of a buffer object.
 432      *
 433      * \param buf       A winsys buffer object to set the flags for.
 434      * \param cs        A command stream to flush if the buffer is referenced by it.
 435      * \param macrotile A macrotile flag.
 436      * \param microtile A microtile flag.
 437      * \param stride    A stride of the buffer in bytes, for texturing.
 438      *
 439      * \note microtile and macrotile are not bitmasks!
 440      */
 441     void (*buffer_set_tiling)(struct pb_buffer *buf,
 442                               struct radeon_winsys_cs *rcs,
 443                               enum radeon_bo_layout microtile,
 444                               enum radeon_bo_layout macrotile,
 445                               unsigned bankw, unsigned bankh,
 446                               unsigned tile_split,
 447                               unsigned stencil_tile_split,
 448                               unsigned mtilea,
 449                               unsigned stride,
 450                               bool scanout);
 451
 452     /**
 453      * Get a winsys buffer from a winsys handle. The internal structure
 454      * of the handle is platform-specific and only a winsys should access it.
 455      *
 456      * \param ws        The winsys this function is called from.
 457      * \param whandle   A winsys handle pointer as was received from a state
 458      *                  tracker.
 459      * \param stride    The returned buffer stride in bytes.
 460      */
 461     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 462                                             struct winsys_handle *whandle,
 463                                             unsigned *stride);
 464
 465     /**
 466      * Get a winsys buffer from a user pointer. The resulting buffer can't
 467      * be exported. Both pointer and size must be page aligned.
 468      *
 469      * \param ws        The winsys this function is called from.
 470      * \param pointer   User pointer to turn into a buffer object.
 471      * \param Size      Size in bytes for the new buffer.
 472      */
 473     struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
 474                                          void *pointer, unsigned size);
 475
 476     /**
 477      * Get a winsys handle from a winsys buffer. The internal structure
 478      * of the handle is platform-specific and only a winsys should access it.
 479      *
 480      * \param buf       A winsys buffer object to get the handle from.
 481      * \param whandle   A winsys handle pointer.
 482      * \param stride    A stride of the buffer in bytes, for texturing.
 483      * \return          TRUE on success.
 484      */
 485     boolean (*buffer_get_handle)(struct pb_buffer *buf,
 486                                  unsigned stride,
 487                                  struct winsys_handle *whandle);
 488
 489     /**
 490      * Return the virtual address of a buffer.
 491      *
 492      * \param buf       A winsys buffer object
 493      * \return          virtual address
 494      */
 495     uint64_t (*buffer_get_virtual_address)(struct radeon_winsys_cs_handle *buf);
 496
 497     /**
 498      * Query the initial placement of the buffer from the kernel driver.
 499      */
 500     enum radeon_bo_domain (*buffer_get_initial_domain)(struct radeon_winsys_cs_handle *buf);
 501
 502     /**************************************************************************
 503      * Command submission.
 504      *
 505      * Each pipe context should create its own command stream and submit
 506      * commands independently of other contexts.
 507      *************************************************************************/
 508
 509     /**
 510      * Create a command submission context.
 511      * Various command streams can be submitted to the same context.
 512      */
 513     struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 514
 515     /**
 516      * Destroy a context.
 517      */
 518     void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 519
 520     /**
 521      * Create a command stream.
 522      *
 523      * \param ctx       The submission context
 524      * \param ring_type The ring type (GFX, DMA, UVD)
 525      * \param flush     Flush callback function associated with the command stream.
 526      * \param user      User pointer that will be passed to the flush callback.
 527      * \param trace_buf Trace buffer when tracing is enabled
 528      */
 529     struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys_ctx *ctx,
 530                                           enum ring_type ring_type,
 531                                           void (*flush)(void *ctx, unsigned flags,
 532                                                         struct pipe_fence_handle **fence),
 533                                           void *flush_ctx,
 534                                           struct radeon_winsys_cs_handle *trace_buf);
 535
 536     /**
 537      * Destroy a command stream.
 538      *
 539      * \param cs        A command stream to destroy.
 540      */
 541     void (*cs_destroy)(struct radeon_winsys_cs *cs);
 542
 543     /**
 544      * Add a new buffer relocation. Every relocation must first be added
 545      * before it can be written.
 546      *
 547      * \param cs  A command stream to add buffer for validation against.
 548      * \param buf A winsys buffer to validate.
 549      * \param usage   Whether the buffer is used for read and/or write.
 550      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 551      * \param priority  A higher number means a greater chance of being
 552      *                  placed in the requested domain. 15 is the maximum.
 553      * \return Relocation index.
 554      */
 555     unsigned (*cs_add_reloc)(struct radeon_winsys_cs *cs,
 556                              struct radeon_winsys_cs_handle *buf,
 557                              enum radeon_bo_usage usage,
 558                              enum radeon_bo_domain domain,
 559                              enum radeon_bo_priority priority);
 560
 561     /**
 562      * Return the index of an already-added buffer.
 563      *
 564      * \param cs        Command stream
 565      * \param buf       Buffer
 566      * \return          The buffer index, or -1 if the buffer has not been added.
 567      */
 568     int (*cs_get_reloc)(struct radeon_winsys_cs *cs,
 569                         struct radeon_winsys_cs_handle *buf);
 570
 571     /**
 572      * Return TRUE if there is enough memory in VRAM and GTT for the relocs
 573      * added so far. If the validation fails, all the relocations which have
 574      * been added since the last call of cs_validate will be removed and
 575      * the CS will be flushed (provided there are still any relocations).
 576      *
 577      * \param cs        A command stream to validate.
 578      */
 579     boolean (*cs_validate)(struct radeon_winsys_cs *cs);
 580
 581     /**
 582      * Return TRUE if there is enough memory in VRAM and GTT for the relocs
 583      * added so far.
 584      *
 585      * \param cs        A command stream to validate.
 586      * \param vram      VRAM memory size pending to be use
 587      * \param gtt       GTT memory size pending to be use
 588      */
 589     boolean (*cs_memory_below_limit)(struct radeon_winsys_cs *cs, uint64_t vram, uint64_t gtt);
 590
 591     /**
 592      * Flush a command stream.
 593      *
 594      * \param cs          A command stream to flush.
 595      * \param flags,      RADEON_FLUSH_ASYNC or 0.
 596      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 597      *                    after the CS and is returned through this parameter.
 598      * \param cs_trace_id A unique identifier of the cs, used for tracing.
 599      */
 600     void (*cs_flush)(struct radeon_winsys_cs *cs,
 601                      unsigned flags,
 602                      struct pipe_fence_handle **fence,
 603                      uint32_t cs_trace_id);
 604
 605     /**
 606      * Return TRUE if a buffer is referenced by a command stream.
 607      *
 608      * \param cs        A command stream.
 609      * \param buf       A winsys buffer.
 610      */
 611     boolean (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
 612                                        struct radeon_winsys_cs_handle *buf,
 613                                        enum radeon_bo_usage usage);
 614
 615     /**
 616      * Request access to a feature for a command stream.
 617      *
 618      * \param cs        A command stream.
 619      * \param fid       Feature ID, one of RADEON_FID_*
 620      * \param enable    Whether to enable or disable the feature.
 621      */
 622     boolean (*cs_request_feature)(struct radeon_winsys_cs *cs,
 623                                   enum radeon_feature_id fid,
 624                                   boolean enable);
 625      /**
 626       * Make sure all asynchronous flush of the cs have completed
 627       *
 628       * \param cs        A command stream.
 629       */
 630     void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
 631
 632     /**
 633      * Wait for the fence and return true if the fence has been signalled.
 634      * The timeout of 0 will only return the status.
 635      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 636      * is signalled.
 637      */
 638     bool (*fence_wait)(struct radeon_winsys *ws,
 639                        struct pipe_fence_handle *fence,
 640                        uint64_t timeout);
 641
 642     /**
 643      * Reference counting for fences.
 644      */
 645     void (*fence_reference)(struct pipe_fence_handle **dst,
 646                             struct pipe_fence_handle *src);
 647
 648     /**
 649      * Initialize surface
 650      *
 651      * \param ws        The winsys this function is called from.
 652      * \param surf      Surface structure ptr
 653      */
 654     int (*surface_init)(struct radeon_winsys *ws,
 655                         struct radeon_surf *surf);
 656
 657     /**
 658      * Find best values for a surface
 659      *
 660      * \param ws        The winsys this function is called from.
 661      * \param surf      Surface structure ptr
 662      */
 663     int (*surface_best)(struct radeon_winsys *ws,
 664                         struct radeon_surf *surf);
 665
 666     uint64_t (*query_value)(struct radeon_winsys *ws,
 667                             enum radeon_value_id value);
 668
 669     void (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 670                            unsigned num_registers, uint32_t *out);
 671 };
 672
 673
 674 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 675 {
 676     cs->buf[cs->cdw++] = value;
 677 }
 678
 679 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 680                                      const uint32_t *values, unsigned count)
 681 {
 682     memcpy(cs->buf+cs->cdw, values, count * 4);
 683     cs->cdw += count;
 684 }
 685
 686 #endif