src/gallium/drivers/radeon/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #ifndef RADEON_WINSYS_H
  25 #define RADEON_WINSYS_H
  26
  27 /* The public winsys interface header for the radeon driver. */
  28
  29 #include "pipebuffer/pb_buffer.h"
  30
  31 #define RADEON_FLUSH_ASYNC              (1 << 0)
  32 #define RADEON_FLUSH_KEEP_TILING_FLAGS  (1 << 1)
  33 #define RADEON_FLUSH_END_OF_FRAME       (1 << 2)
  34
  35 /* Tiling flags. */
  36 enum radeon_bo_layout {
  37     RADEON_LAYOUT_LINEAR = 0,
  38     RADEON_LAYOUT_TILED,
  39     RADEON_LAYOUT_SQUARETILED,
  40
  41     RADEON_LAYOUT_UNKNOWN
  42 };
  43
  44 enum radeon_bo_domain { /* bitfield */
  45     RADEON_DOMAIN_GTT  = 2,
  46     RADEON_DOMAIN_VRAM = 4,
  47     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  48 };
  49
  50 enum radeon_bo_flag { /* bitfield */
  51     RADEON_FLAG_GTT_WC =        (1 << 0),
  52     RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  53     RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  54 };
  55
  56 enum radeon_bo_usage { /* bitfield */
  57     RADEON_USAGE_READ = 2,
  58     RADEON_USAGE_WRITE = 4,
  59     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
  60 };
  61
  62 enum radeon_family {
  63     CHIP_UNKNOWN = 0,
  64     CHIP_R300, /* R3xx-based cores. */
  65     CHIP_R350,
  66     CHIP_RV350,
  67     CHIP_RV370,
  68     CHIP_RV380,
  69     CHIP_RS400,
  70     CHIP_RC410,
  71     CHIP_RS480,
  72     CHIP_R420,     /* R4xx-based cores. */
  73     CHIP_R423,
  74     CHIP_R430,
  75     CHIP_R480,
  76     CHIP_R481,
  77     CHIP_RV410,
  78     CHIP_RS600,
  79     CHIP_RS690,
  80     CHIP_RS740,
  81     CHIP_RV515,    /* R5xx-based cores. */
  82     CHIP_R520,
  83     CHIP_RV530,
  84     CHIP_R580,
  85     CHIP_RV560,
  86     CHIP_RV570,
  87     CHIP_R600,
  88     CHIP_RV610,
  89     CHIP_RV630,
  90     CHIP_RV670,
  91     CHIP_RV620,
  92     CHIP_RV635,
  93     CHIP_RS780,
  94     CHIP_RS880,
  95     CHIP_RV770,
  96     CHIP_RV730,
  97     CHIP_RV710,
  98     CHIP_RV740,
  99     CHIP_CEDAR,
 100     CHIP_REDWOOD,
 101     CHIP_JUNIPER,
 102     CHIP_CYPRESS,
 103     CHIP_HEMLOCK,
 104     CHIP_PALM,
 105     CHIP_SUMO,
 106     CHIP_SUMO2,
 107     CHIP_BARTS,
 108     CHIP_TURKS,
 109     CHIP_CAICOS,
 110     CHIP_CAYMAN,
 111     CHIP_ARUBA,
 112     CHIP_TAHITI,
 113     CHIP_PITCAIRN,
 114     CHIP_VERDE,
 115     CHIP_OLAND,
 116     CHIP_HAINAN,
 117     CHIP_BONAIRE,
 118     CHIP_KAVERI,
 119     CHIP_KABINI,
 120     CHIP_HAWAII,
 121     CHIP_MULLINS,
 122     CHIP_TONGA,
 123     CHIP_ICELAND,
 124     CHIP_CARRIZO,
 125     CHIP_FIJI,
 126     CHIP_STONEY,
 127     CHIP_POLARIS10,
 128     CHIP_POLARIS11,
 129     CHIP_LAST,
 130 };
 131
 132 enum chip_class {
 133     CLASS_UNKNOWN = 0,
 134     R300,
 135     R400,
 136     R500,
 137     R600,
 138     R700,
 139     EVERGREEN,
 140     CAYMAN,
 141     SI,
 142     CIK,
 143     VI,
 144 };
 145
 146 enum ring_type {
 147     RING_GFX = 0,
 148     RING_COMPUTE,
 149     RING_DMA,
 150     RING_UVD,
 151     RING_VCE,
 152     RING_LAST,
 153 };
 154
 155 enum radeon_value_id {
 156     RADEON_REQUESTED_VRAM_MEMORY,
 157     RADEON_REQUESTED_GTT_MEMORY,
 158     RADEON_BUFFER_WAIT_TIME_NS,
 159     RADEON_TIMESTAMP,
 160     RADEON_NUM_CS_FLUSHES,
 161     RADEON_NUM_BYTES_MOVED,
 162     RADEON_VRAM_USAGE,
 163     RADEON_GTT_USAGE,
 164     RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
 165     RADEON_CURRENT_SCLK,
 166     RADEON_CURRENT_MCLK,
 167     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
 168 };
 169
 170 /* Each group of four has the same priority. */
 171 enum radeon_bo_priority {
 172     RADEON_PRIO_FENCE = 0,
 173     RADEON_PRIO_TRACE,
 174     RADEON_PRIO_SO_FILLED_SIZE,
 175     RADEON_PRIO_QUERY,
 176
 177     RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
 178     RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
 179     RADEON_PRIO_DRAW_INDIRECT,
 180     RADEON_PRIO_INDEX_BUFFER,
 181
 182     RADEON_PRIO_CP_DMA = 8,
 183
 184     RADEON_PRIO_VCE = 12,
 185     RADEON_PRIO_UVD,
 186     RADEON_PRIO_SDMA_BUFFER,
 187     RADEON_PRIO_SDMA_TEXTURE,
 188
 189     RADEON_PRIO_USER_SHADER = 16,
 190     RADEON_PRIO_INTERNAL_SHADER, /* fetch shader, etc. */
 191
 192     /* gap: 20 */
 193
 194     RADEON_PRIO_CONST_BUFFER = 24,
 195     RADEON_PRIO_DESCRIPTORS,
 196     RADEON_PRIO_BORDER_COLORS,
 197
 198     RADEON_PRIO_SAMPLER_BUFFER = 28,
 199     RADEON_PRIO_VERTEX_BUFFER,
 200
 201     RADEON_PRIO_SHADER_RW_BUFFER = 32,
 202     RADEON_PRIO_RINGS_STREAMOUT,
 203     RADEON_PRIO_SCRATCH_BUFFER,
 204     RADEON_PRIO_COMPUTE_GLOBAL,
 205
 206     RADEON_PRIO_SAMPLER_TEXTURE = 36,
 207     RADEON_PRIO_SHADER_RW_IMAGE,
 208
 209     RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 40,
 210
 211     RADEON_PRIO_COLOR_BUFFER = 44,
 212
 213     RADEON_PRIO_DEPTH_BUFFER = 48,
 214
 215     RADEON_PRIO_COLOR_BUFFER_MSAA = 52,
 216
 217     RADEON_PRIO_DEPTH_BUFFER_MSAA = 56,
 218
 219     RADEON_PRIO_CMASK = 60,
 220     RADEON_PRIO_DCC,
 221     RADEON_PRIO_HTILE,
 222     /* 63 is the maximum value */
 223 };
 224
 225 struct winsys_handle;
 226 struct radeon_winsys_ctx;
 227
 228 struct radeon_winsys_cs_chunk {
 229     unsigned cdw;  /* Number of used dwords. */
 230     unsigned max_dw; /* Maximum number of dwords. */
 231     uint32_t *buf; /* The base pointer of the chunk. */
 232 };
 233
 234 struct radeon_winsys_cs {
 235     struct radeon_winsys_cs_chunk current;
 236     struct radeon_winsys_cs_chunk *prev;
 237     unsigned                      num_prev; /* Number of previous chunks. */
 238     unsigned                      max_prev; /* Space in array pointed to by prev. */
 239     unsigned                      prev_dw; /* Total number of dwords in previous chunks. */
 240 };
 241
 242 struct radeon_info {
 243     /* PCI info: domain:bus:dev:func */
 244     uint32_t                    pci_domain;
 245     uint32_t                    pci_bus;
 246     uint32_t                    pci_dev;
 247     uint32_t                    pci_func;
 248
 249     /* Device info. */
 250     uint32_t                    pci_id;
 251     enum radeon_family          family;
 252     enum chip_class             chip_class;
 253     uint32_t                    gart_page_size;
 254     uint64_t                    gart_size;
 255     uint64_t                    vram_size;
 256     bool                        has_dedicated_vram;
 257     boolean                     has_virtual_memory;
 258     bool                        gfx_ib_pad_with_type2;
 259     boolean                     has_sdma;
 260     boolean                     has_uvd;
 261     uint32_t                    vce_fw_version;
 262     uint32_t                    vce_harvest_config;
 263     uint32_t                    clock_crystal_freq;
 264
 265     /* Kernel info. */
 266     uint32_t                    drm_major; /* version */
 267     uint32_t                    drm_minor;
 268     uint32_t                    drm_patchlevel;
 269     boolean                     has_userptr;
 270
 271     /* Shader cores. */
 272     uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
 273     uint32_t                    max_shader_clock;
 274     uint32_t                    num_good_compute_units;
 275     uint32_t                    max_se; /* shader engines */
 276     uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 277
 278     /* Render backends (color + depth blocks). */
 279     uint32_t                    r300_num_gb_pipes;
 280     uint32_t                    r300_num_z_pipes;
 281     uint32_t                    r600_gb_backend_map; /* R600 harvest config */
 282     boolean                     r600_gb_backend_map_valid;
 283     uint32_t                    r600_num_banks;
 284     uint32_t                    num_render_backends;
 285     uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
 286     uint32_t                    pipe_interleave_bytes;
 287     uint32_t                    enabled_rb_mask; /* GCN harvest config */
 288
 289     /* Tile modes. */
 290     uint32_t                    si_tile_mode_array[32];
 291     uint32_t                    cik_macrotile_mode_array[16];
 292 };
 293
 294 /* Tiling info for display code, DRI sharing, and other data. */
 295 struct radeon_bo_metadata {
 296     /* Tiling flags describing the texture layout for display code
 297      * and DRI sharing.
 298      */
 299     enum radeon_bo_layout   microtile;
 300     enum radeon_bo_layout   macrotile;
 301     unsigned                pipe_config;
 302     unsigned                bankw;
 303     unsigned                bankh;
 304     unsigned                tile_split;
 305     unsigned                mtilea;
 306     unsigned                num_banks;
 307     unsigned                stride;
 308     bool                    scanout;
 309
 310     /* Additional metadata associated with the buffer, in bytes.
 311      * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 312      * Supported by amdgpu only.
 313      */
 314     uint32_t                size_metadata;
 315     uint32_t                metadata[64];
 316 };
 317
 318 enum radeon_feature_id {
 319     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 320     RADEON_FID_R300_CMASK_ACCESS,
 321 };
 322
 323 #define RADEON_SURF_MAX_LEVEL                   32
 324
 325 #define RADEON_SURF_TYPE_MASK                   0xFF
 326 #define RADEON_SURF_TYPE_SHIFT                  0
 327 #define     RADEON_SURF_TYPE_1D                     0
 328 #define     RADEON_SURF_TYPE_2D                     1
 329 #define     RADEON_SURF_TYPE_3D                     2
 330 #define     RADEON_SURF_TYPE_CUBEMAP                3
 331 #define     RADEON_SURF_TYPE_1D_ARRAY               4
 332 #define     RADEON_SURF_TYPE_2D_ARRAY               5
 333 #define RADEON_SURF_MODE_MASK                   0xFF
 334 #define RADEON_SURF_MODE_SHIFT                  8
 335 #define     RADEON_SURF_MODE_LINEAR_ALIGNED         1
 336 #define     RADEON_SURF_MODE_1D                     2
 337 #define     RADEON_SURF_MODE_2D                     3
 338 #define RADEON_SURF_SCANOUT                     (1 << 16)
 339 #define RADEON_SURF_ZBUFFER                     (1 << 17)
 340 #define RADEON_SURF_SBUFFER                     (1 << 18)
 341 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
 342 #define RADEON_SURF_HAS_SBUFFER_MIPTREE         (1 << 19)
 343 #define RADEON_SURF_HAS_TILE_MODE_INDEX         (1 << 20)
 344 #define RADEON_SURF_FMASK                       (1 << 21)
 345 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
 346
 347 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
 348 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
 349 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
 350
 351 struct radeon_surf_level {
 352     uint64_t                    offset;
 353     uint64_t                    slice_size;
 354     uint32_t                    npix_x;
 355     uint32_t                    npix_y;
 356     uint32_t                    npix_z;
 357     uint32_t                    nblk_x;
 358     uint32_t                    nblk_y;
 359     uint32_t                    nblk_z;
 360     uint32_t                    pitch_bytes;
 361     uint32_t                    mode;
 362     uint64_t                    dcc_offset;
 363 };
 364
 365 struct radeon_surf {
 366     /* These are inputs to the calculator. */
 367     uint32_t                    npix_x;
 368     uint32_t                    npix_y;
 369     uint32_t                    npix_z;
 370     uint32_t                    blk_w;
 371     uint32_t                    blk_h;
 372     uint32_t                    blk_d;
 373     uint32_t                    array_size;
 374     uint32_t                    last_level;
 375     uint32_t                    bpe;
 376     uint32_t                    nsamples;
 377     uint32_t                    flags;
 378
 379     /* These are return values. Some of them can be set by the caller, but
 380      * they will be treated as hints (e.g. bankw, bankh) and might be
 381      * changed by the calculator.
 382      */
 383     uint64_t                    bo_size;
 384     uint64_t                    bo_alignment;
 385     /* This applies to EG and later. */
 386     uint32_t                    bankw;
 387     uint32_t                    bankh;
 388     uint32_t                    mtilea;
 389     uint32_t                    tile_split;
 390     uint32_t                    stencil_tile_split;
 391     uint64_t                    stencil_offset;
 392     struct radeon_surf_level    level[RADEON_SURF_MAX_LEVEL];
 393     struct radeon_surf_level    stencil_level[RADEON_SURF_MAX_LEVEL];
 394     uint32_t                    tiling_index[RADEON_SURF_MAX_LEVEL];
 395     uint32_t                    stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
 396     uint32_t                    pipe_config;
 397     uint32_t                    num_banks;
 398     uint32_t                    macro_tile_index;
 399
 400     uint64_t                    dcc_size;
 401     uint64_t                    dcc_alignment;
 402 };
 403
 404 struct radeon_bo_list_item {
 405     struct pb_buffer *buf;
 406     uint64_t vm_address;
 407     uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
 408 };
 409
 410 struct radeon_winsys {
 411     /**
 412      * The screen object this winsys was created for
 413      */
 414     struct pipe_screen *screen;
 415
 416     /**
 417      * Decrement the winsys reference count.
 418      *
 419      * \param ws  The winsys this function is called for.
 420      * \return    True if the winsys and screen should be destroyed.
 421      */
 422     bool (*unref)(struct radeon_winsys *ws);
 423
 424     /**
 425      * Destroy this winsys.
 426      *
 427      * \param ws        The winsys this function is called from.
 428      */
 429     void (*destroy)(struct radeon_winsys *ws);
 430
 431     /**
 432      * Query an info structure from winsys.
 433      *
 434      * \param ws        The winsys this function is called from.
 435      * \param info      Return structure
 436      */
 437     void (*query_info)(struct radeon_winsys *ws,
 438                        struct radeon_info *info);
 439
 440     /**************************************************************************
 441      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 442      *
 443      * Remember that gallium gets to choose the interface it needs, and the
 444      * window systems must then implement that interface (rather than the
 445      * other way around...).
 446      *************************************************************************/
 447
 448     /**
 449      * Create a buffer object.
 450      *
 451      * \param ws        The winsys this function is called from.
 452      * \param size      The size to allocate.
 453      * \param alignment An alignment of the buffer in memory.
 454      * \param use_reusable_pool Whether the cache buffer manager should be used.
 455      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 456      * \return          The created buffer object.
 457      */
 458     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 459                                        uint64_t size,
 460                                        unsigned alignment,
 461                                        enum radeon_bo_domain domain,
 462                                        enum radeon_bo_flag flags);
 463
 464     /**
 465      * Map the entire data store of a buffer object into the client's address
 466      * space.
 467      *
 468      * \param buf       A winsys buffer object to map.
 469      * \param cs        A command stream to flush if the buffer is referenced by it.
 470      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 471      * \return          The pointer at the beginning of the buffer.
 472      */
 473     void *(*buffer_map)(struct pb_buffer *buf,
 474                         struct radeon_winsys_cs *cs,
 475                         enum pipe_transfer_usage usage);
 476
 477     /**
 478      * Unmap a buffer object from the client's address space.
 479      *
 480      * \param buf       A winsys buffer object to unmap.
 481      */
 482     void (*buffer_unmap)(struct pb_buffer *buf);
 483
 484     /**
 485      * Wait for the buffer and return true if the buffer is not used
 486      * by the device.
 487      *
 488      * The timeout of 0 will only return the status.
 489      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
 490      * is idle.
 491      */
 492     bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
 493                         enum radeon_bo_usage usage);
 494
 495     /**
 496      * Return buffer metadata.
 497      * (tiling info for display code, DRI sharing, and other data)
 498      *
 499      * \param buf       A winsys buffer object to get the flags from.
 500      * \param md        Metadata
 501      */
 502     void (*buffer_get_metadata)(struct pb_buffer *buf,
 503                                 struct radeon_bo_metadata *md);
 504
 505     /**
 506      * Set buffer metadata.
 507      * (tiling info for display code, DRI sharing, and other data)
 508      *
 509      * \param buf       A winsys buffer object to set the flags for.
 510      * \param md        Metadata
 511      */
 512     void (*buffer_set_metadata)(struct pb_buffer *buf,
 513                                 struct radeon_bo_metadata *md);
 514
 515     /**
 516      * Get a winsys buffer from a winsys handle. The internal structure
 517      * of the handle is platform-specific and only a winsys should access it.
 518      *
 519      * \param ws        The winsys this function is called from.
 520      * \param whandle   A winsys handle pointer as was received from a state
 521      *                  tracker.
 522      * \param stride    The returned buffer stride in bytes.
 523      */
 524     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 525                                             struct winsys_handle *whandle,
 526                                             unsigned *stride, unsigned *offset);
 527
 528     /**
 529      * Get a winsys buffer from a user pointer. The resulting buffer can't
 530      * be exported. Both pointer and size must be page aligned.
 531      *
 532      * \param ws        The winsys this function is called from.
 533      * \param pointer   User pointer to turn into a buffer object.
 534      * \param Size      Size in bytes for the new buffer.
 535      */
 536     struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
 537                                          void *pointer, uint64_t size);
 538
 539     /**
 540      * Whether the buffer was created from a user pointer.
 541      *
 542      * \param buf       A winsys buffer object
 543      * \return          whether \p buf was created via buffer_from_ptr
 544      */
 545     bool (*buffer_is_user_ptr)(struct pb_buffer *buf);
 546
 547     /**
 548      * Get a winsys handle from a winsys buffer. The internal structure
 549      * of the handle is platform-specific and only a winsys should access it.
 550      *
 551      * \param buf       A winsys buffer object to get the handle from.
 552      * \param whandle   A winsys handle pointer.
 553      * \param stride    A stride of the buffer in bytes, for texturing.
 554      * \return          TRUE on success.
 555      */
 556     boolean (*buffer_get_handle)(struct pb_buffer *buf,
 557                                  unsigned stride, unsigned offset,
 558                                  unsigned slice_size,
 559                                  struct winsys_handle *whandle);
 560
 561     /**
 562      * Return the virtual address of a buffer.
 563      *
 564      * \param buf       A winsys buffer object
 565      * \return          virtual address
 566      */
 567     uint64_t (*buffer_get_virtual_address)(struct pb_buffer *buf);
 568
 569     /**
 570      * Query the initial placement of the buffer from the kernel driver.
 571      */
 572     enum radeon_bo_domain (*buffer_get_initial_domain)(struct pb_buffer *buf);
 573
 574     /**************************************************************************
 575      * Command submission.
 576      *
 577      * Each pipe context should create its own command stream and submit
 578      * commands independently of other contexts.
 579      *************************************************************************/
 580
 581     /**
 582      * Create a command submission context.
 583      * Various command streams can be submitted to the same context.
 584      */
 585     struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 586
 587     /**
 588      * Destroy a context.
 589      */
 590     void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 591
 592     /**
 593      * Query a GPU reset status.
 594      */
 595     enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
 596
 597     /**
 598      * Create a command stream.
 599      *
 600      * \param ctx       The submission context
 601      * \param ring_type The ring type (GFX, DMA, UVD)
 602      * \param flush     Flush callback function associated with the command stream.
 603      * \param user      User pointer that will be passed to the flush callback.
 604      */
 605     struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys_ctx *ctx,
 606                                           enum ring_type ring_type,
 607                                           void (*flush)(void *ctx, unsigned flags,
 608                                                         struct pipe_fence_handle **fence),
 609                                           void *flush_ctx);
 610
 611     /**
 612      * Add a constant engine IB to a graphics CS. This makes the graphics CS
 613      * from "cs_create" a group of two IBs that share a buffer list and are
 614      * flushed together.
 615      *
 616      * The returned constant CS is only a stream for writing packets to the new
 617      * IB. Calling other winsys functions with it is not allowed, not even
 618      * "cs_destroy".
 619      *
 620      * In order to add buffers and check memory usage, use the graphics CS.
 621      * In order to flush it, use the graphics CS, which will flush both IBs.
 622      * Destroying the graphics CS will destroy both of them.
 623      *
 624      * \param cs  The graphics CS from "cs_create" that will hold the buffer
 625      *            list and will be used for flushing.
 626      */
 627     struct radeon_winsys_cs *(*cs_add_const_ib)(struct radeon_winsys_cs *cs);
 628
 629      /**
 630      * Add a constant engine preamble IB to a graphics CS. This add an extra IB
 631      * in similar manner to cs_add_const_ib. This should always be called after
 632      * cs_add_const_ib.
 633      *
 634      * The returned IB is a constant engine IB that only gets flushed if the
 635      * context changed.
 636      *
 637      * \param cs  The graphics CS from "cs_create" that will hold the buffer
 638      *            list and will be used for flushing.
 639      */
 640     struct radeon_winsys_cs *(*cs_add_const_preamble_ib)(struct radeon_winsys_cs *cs);
 641     /**
 642      * Destroy a command stream.
 643      *
 644      * \param cs        A command stream to destroy.
 645      */
 646     void (*cs_destroy)(struct radeon_winsys_cs *cs);
 647
 648     /**
 649      * Add a buffer. Each buffer used by a CS must be added using this function.
 650      *
 651      * \param cs      Command stream
 652      * \param buf     Buffer
 653      * \param usage   Whether the buffer is used for read and/or write.
 654      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 655      * \param priority  A higher number means a greater chance of being
 656      *                  placed in the requested domain. 15 is the maximum.
 657      * \return Buffer index.
 658      */
 659     unsigned (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 660                              struct pb_buffer *buf,
 661                              enum radeon_bo_usage usage,
 662                              enum radeon_bo_domain domain,
 663                              enum radeon_bo_priority priority);
 664
 665     /**
 666      * Return the index of an already-added buffer.
 667      *
 668      * \param cs        Command stream
 669      * \param buf       Buffer
 670      * \return          The buffer index, or -1 if the buffer has not been added.
 671      */
 672     int (*cs_lookup_buffer)(struct radeon_winsys_cs *cs,
 673                             struct pb_buffer *buf);
 674
 675     /**
 676      * Return TRUE if there is enough memory in VRAM and GTT for the buffers
 677      * added so far. If the validation fails, all buffers which have
 678      * been added since the last call of cs_validate will be removed and
 679      * the CS will be flushed (provided there are still any buffers).
 680      *
 681      * \param cs        A command stream to validate.
 682      */
 683     boolean (*cs_validate)(struct radeon_winsys_cs *cs);
 684
 685     /**
 686      * Check whether the given number of dwords is available in the IB.
 687      * Optionally chain a new chunk of the IB if necessary and supported.
 688      *
 689      * \param cs        A command stream.
 690      * \param dw        Number of CS dwords requested by the caller.
 691      */
 692     bool (*cs_check_space)(struct radeon_winsys_cs *cs, unsigned dw);
 693
 694     /**
 695      * Return TRUE if there is enough memory in VRAM and GTT for the buffers
 696      * added so far.
 697      *
 698      * \param cs        A command stream to validate.
 699      * \param vram      VRAM memory size pending to be use
 700      * \param gtt       GTT memory size pending to be use
 701      */
 702     boolean (*cs_memory_below_limit)(struct radeon_winsys_cs *cs, uint64_t vram, uint64_t gtt);
 703
 704     uint64_t (*cs_query_memory_usage)(struct radeon_winsys_cs *cs);
 705
 706     /**
 707      * Return the buffer list.
 708      *
 709      * \param cs    Command stream
 710      * \param list  Returned buffer list. Set to NULL to query the count only.
 711      * \return      The buffer count.
 712      */
 713     unsigned (*cs_get_buffer_list)(struct radeon_winsys_cs *cs,
 714                                    struct radeon_bo_list_item *list);
 715
 716     /**
 717      * Flush a command stream.
 718      *
 719      * \param cs          A command stream to flush.
 720      * \param flags,      RADEON_FLUSH_ASYNC or 0.
 721      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 722      *                    after the CS and is returned through this parameter.
 723      */
 724     void (*cs_flush)(struct radeon_winsys_cs *cs,
 725                      unsigned flags,
 726                      struct pipe_fence_handle **fence);
 727
 728     /**
 729      * Return TRUE if a buffer is referenced by a command stream.
 730      *
 731      * \param cs        A command stream.
 732      * \param buf       A winsys buffer.
 733      */
 734     boolean (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
 735                                        struct pb_buffer *buf,
 736                                        enum radeon_bo_usage usage);
 737
 738     /**
 739      * Request access to a feature for a command stream.
 740      *
 741      * \param cs        A command stream.
 742      * \param fid       Feature ID, one of RADEON_FID_*
 743      * \param enable    Whether to enable or disable the feature.
 744      */
 745     boolean (*cs_request_feature)(struct radeon_winsys_cs *cs,
 746                                   enum radeon_feature_id fid,
 747                                   boolean enable);
 748      /**
 749       * Make sure all asynchronous flush of the cs have completed
 750       *
 751       * \param cs        A command stream.
 752       */
 753     void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
 754
 755     /**
 756      * Wait for the fence and return true if the fence has been signalled.
 757      * The timeout of 0 will only return the status.
 758      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 759      * is signalled.
 760      */
 761     bool (*fence_wait)(struct radeon_winsys *ws,
 762                        struct pipe_fence_handle *fence,
 763                        uint64_t timeout);
 764
 765     /**
 766      * Reference counting for fences.
 767      */
 768     void (*fence_reference)(struct pipe_fence_handle **dst,
 769                             struct pipe_fence_handle *src);
 770
 771     /**
 772      * Initialize surface
 773      *
 774      * \param ws        The winsys this function is called from.
 775      * \param surf      Surface structure ptr
 776      */
 777     int (*surface_init)(struct radeon_winsys *ws,
 778                         struct radeon_surf *surf);
 779
 780     /**
 781      * Find best values for a surface
 782      *
 783      * \param ws        The winsys this function is called from.
 784      * \param surf      Surface structure ptr
 785      */
 786     int (*surface_best)(struct radeon_winsys *ws,
 787                         struct radeon_surf *surf);
 788
 789     uint64_t (*query_value)(struct radeon_winsys *ws,
 790                             enum radeon_value_id value);
 791
 792     bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 793                            unsigned num_registers, uint32_t *out);
 794 };
 795
 796 static inline bool radeon_emitted(struct radeon_winsys_cs *cs, unsigned num_dw)
 797 {
 798     return cs && (cs->prev_dw + cs->current.cdw > num_dw);
 799 }
 800
 801 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 802 {
 803     cs->current.buf[cs->current.cdw++] = value;
 804 }
 805
 806 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 807                                      const uint32_t *values, unsigned count)
 808 {
 809     memcpy(cs->current.buf + cs->current.cdw, values, count * 4);
 810     cs->current.cdw += count;
 811 }
 812
 813 #endif