src/gallium/drivers/radeon/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  * Copyright 2018 Advanced Micro Devices, Inc.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * on the rights to use, copy, modify, merge, publish, distribute, sub
  11  * license, and/or sell copies of the Software, and to permit persons to whom
  12  * the Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  25
  26 #ifndef RADEON_WINSYS_H
  27 #define RADEON_WINSYS_H
  28
  29 /* The public winsys interface header for the radeon driver. */
  30
  31 /* Whether the next IB can start immediately and not wait for draws and
  32  * dispatches from the current IB to finish. */
  33 #define RADEON_FLUSH_START_NEXT_GFX_IB_NOW      (1u << 31)
  34
  35 #define RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW \
  36         (PIPE_FLUSH_ASYNC | RADEON_FLUSH_START_NEXT_GFX_IB_NOW)
  37
  38 #include "pipebuffer/pb_buffer.h"
  39
  40 #include "amd/common/ac_gpu_info.h"
  41 #include "amd/common/ac_surface.h"
  42
  43 /* Tiling flags. */
  44 enum radeon_bo_layout {
  45     RADEON_LAYOUT_LINEAR = 0,
  46     RADEON_LAYOUT_TILED,
  47     RADEON_LAYOUT_SQUARETILED,
  48
  49     RADEON_LAYOUT_UNKNOWN
  50 };
  51
  52 enum radeon_bo_domain { /* bitfield */
  53     RADEON_DOMAIN_GTT  = 2,
  54     RADEON_DOMAIN_VRAM = 4,
  55     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  56 };
  57
  58 enum radeon_bo_flag { /* bitfield */
  59     RADEON_FLAG_GTT_WC =        (1 << 0),
  60     RADEON_FLAG_NO_CPU_ACCESS = (1 << 1),
  61     RADEON_FLAG_NO_SUBALLOC =   (1 << 2),
  62     RADEON_FLAG_SPARSE =        (1 << 3),
  63     RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 4),
  64     RADEON_FLAG_READ_ONLY =     (1 << 5),
  65     RADEON_FLAG_32BIT =    (1 << 6),
  66 };
  67
  68 enum radeon_bo_usage { /* bitfield */
  69     RADEON_USAGE_READ = 2,
  70     RADEON_USAGE_WRITE = 4,
  71     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE,
  72
  73     /* The winsys ensures that the CS submission will be scheduled after
  74      * previously flushed CSs referencing this BO in a conflicting way.
  75      */
  76     RADEON_USAGE_SYNCHRONIZED = 8
  77 };
  78
  79 #define RADEON_SPARSE_PAGE_SIZE (64 * 1024)
  80
  81 enum ring_type {
  82     RING_GFX = 0,
  83     RING_COMPUTE,
  84     RING_DMA,
  85     RING_UVD,
  86     RING_VCE,
  87     RING_UVD_ENC,
  88     RING_VCN_DEC,
  89     RING_VCN_ENC,
  90     RING_LAST,
  91 };
  92
  93 enum radeon_value_id {
  94     RADEON_REQUESTED_VRAM_MEMORY,
  95     RADEON_REQUESTED_GTT_MEMORY,
  96     RADEON_MAPPED_VRAM,
  97     RADEON_MAPPED_GTT,
  98     RADEON_BUFFER_WAIT_TIME_NS,
  99     RADEON_NUM_MAPPED_BUFFERS,
 100     RADEON_TIMESTAMP,
 101     RADEON_NUM_GFX_IBS,
 102     RADEON_NUM_SDMA_IBS,
 103     RADEON_GFX_BO_LIST_COUNTER, /* number of BOs submitted in gfx IBs */
 104     RADEON_GFX_IB_SIZE_COUNTER,
 105     RADEON_NUM_BYTES_MOVED,
 106     RADEON_NUM_EVICTIONS,
 107     RADEON_NUM_VRAM_CPU_PAGE_FAULTS,
 108     RADEON_VRAM_USAGE,
 109     RADEON_VRAM_VIS_USAGE,
 110     RADEON_GTT_USAGE,
 111     RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
 112     RADEON_CURRENT_SCLK,
 113     RADEON_CURRENT_MCLK,
 114     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
 115     RADEON_CS_THREAD_TIME,
 116 };
 117
 118 /* Each group of four has the same priority. */
 119 enum radeon_bo_priority {
 120     RADEON_PRIO_FENCE = 0,
 121     RADEON_PRIO_TRACE,
 122     RADEON_PRIO_SO_FILLED_SIZE,
 123     RADEON_PRIO_QUERY,
 124
 125     RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
 126     RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
 127     RADEON_PRIO_DRAW_INDIRECT,
 128     RADEON_PRIO_INDEX_BUFFER,
 129
 130     RADEON_PRIO_VCE = 8,
 131     RADEON_PRIO_UVD,
 132     RADEON_PRIO_SDMA_BUFFER,
 133     RADEON_PRIO_SDMA_TEXTURE,
 134
 135     RADEON_PRIO_CP_DMA = 12,
 136
 137     RADEON_PRIO_CONST_BUFFER = 16,
 138     RADEON_PRIO_DESCRIPTORS,
 139     RADEON_PRIO_BORDER_COLORS,
 140
 141     RADEON_PRIO_SAMPLER_BUFFER = 20,
 142     RADEON_PRIO_VERTEX_BUFFER,
 143
 144     RADEON_PRIO_SHADER_RW_BUFFER = 24,
 145     RADEON_PRIO_COMPUTE_GLOBAL,
 146
 147     RADEON_PRIO_SAMPLER_TEXTURE = 28,
 148     RADEON_PRIO_SHADER_RW_IMAGE,
 149
 150     RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 32,
 151
 152     RADEON_PRIO_COLOR_BUFFER = 36,
 153
 154     RADEON_PRIO_DEPTH_BUFFER = 40,
 155
 156     RADEON_PRIO_COLOR_BUFFER_MSAA = 44,
 157
 158     RADEON_PRIO_DEPTH_BUFFER_MSAA = 48,
 159
 160     RADEON_PRIO_CMASK = 52,
 161     RADEON_PRIO_DCC,
 162     RADEON_PRIO_HTILE,
 163     RADEON_PRIO_SHADER_BINARY, /* the hw can't hide instruction cache misses */
 164
 165     RADEON_PRIO_SHADER_RINGS = 56,
 166
 167     RADEON_PRIO_SCRATCH_BUFFER = 60,
 168     /* 63 is the maximum value */
 169 };
 170
 171 struct winsys_handle;
 172 struct radeon_winsys_ctx;
 173
 174 struct radeon_winsys_cs_chunk {
 175     unsigned cdw;  /* Number of used dwords. */
 176     unsigned max_dw; /* Maximum number of dwords. */
 177     uint32_t *buf; /* The base pointer of the chunk. */
 178 };
 179
 180 struct radeon_winsys_cs {
 181     struct radeon_winsys_cs_chunk current;
 182     struct radeon_winsys_cs_chunk *prev;
 183     unsigned                      num_prev; /* Number of previous chunks. */
 184     unsigned                      max_prev; /* Space in array pointed to by prev. */
 185     unsigned                      prev_dw; /* Total number of dwords in previous chunks. */
 186
 187     /* Memory usage of the buffer list. These are always 0 for preamble IBs. */
 188     uint64_t                      used_vram;
 189     uint64_t                      used_gart;
 190 };
 191
 192 /* Tiling info for display code, DRI sharing, and other data. */
 193 struct radeon_bo_metadata {
 194     /* Tiling flags describing the texture layout for display code
 195      * and DRI sharing.
 196      */
 197     union {
 198         struct {
 199             enum radeon_bo_layout   microtile;
 200             enum radeon_bo_layout   macrotile;
 201             unsigned                pipe_config;
 202             unsigned                bankw;
 203             unsigned                bankh;
 204             unsigned                tile_split;
 205             unsigned                mtilea;
 206             unsigned                num_banks;
 207             unsigned                stride;
 208             bool                    scanout;
 209         } legacy;
 210
 211         struct {
 212             /* surface flags */
 213             unsigned swizzle_mode:5;
 214         } gfx9;
 215     } u;
 216
 217     /* Additional metadata associated with the buffer, in bytes.
 218      * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 219      * Supported by amdgpu only.
 220      */
 221     uint32_t                size_metadata;
 222     uint32_t                metadata[64];
 223 };
 224
 225 enum radeon_feature_id {
 226     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 227     RADEON_FID_R300_CMASK_ACCESS,
 228 };
 229
 230 struct radeon_bo_list_item {
 231     uint64_t bo_size;
 232     uint64_t vm_address;
 233     uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
 234 };
 235
 236 struct radeon_winsys {
 237     /**
 238      * The screen object this winsys was created for
 239      */
 240     struct pipe_screen *screen;
 241
 242     /**
 243      * Decrement the winsys reference count.
 244      *
 245      * \param ws  The winsys this function is called for.
 246      * \return    True if the winsys and screen should be destroyed.
 247      */
 248     bool (*unref)(struct radeon_winsys *ws);
 249
 250     /**
 251      * Destroy this winsys.
 252      *
 253      * \param ws        The winsys this function is called from.
 254      */
 255     void (*destroy)(struct radeon_winsys *ws);
 256
 257     /**
 258      * Query an info structure from winsys.
 259      *
 260      * \param ws        The winsys this function is called from.
 261      * \param info      Return structure
 262      */
 263     void (*query_info)(struct radeon_winsys *ws,
 264                        struct radeon_info *info);
 265
 266     /**************************************************************************
 267      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 268      *
 269      * Remember that gallium gets to choose the interface it needs, and the
 270      * window systems must then implement that interface (rather than the
 271      * other way around...).
 272      *************************************************************************/
 273
 274     /**
 275      * Create a buffer object.
 276      *
 277      * \param ws        The winsys this function is called from.
 278      * \param size      The size to allocate.
 279      * \param alignment An alignment of the buffer in memory.
 280      * \param use_reusable_pool Whether the cache buffer manager should be used.
 281      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 282      * \return          The created buffer object.
 283      */
 284     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 285                                        uint64_t size,
 286                                        unsigned alignment,
 287                                        enum radeon_bo_domain domain,
 288                                        enum radeon_bo_flag flags);
 289
 290     /**
 291      * Map the entire data store of a buffer object into the client's address
 292      * space.
 293      *
 294      * \param buf       A winsys buffer object to map.
 295      * \param cs        A command stream to flush if the buffer is referenced by it.
 296      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 297      * \return          The pointer at the beginning of the buffer.
 298      */
 299     void *(*buffer_map)(struct pb_buffer *buf,
 300                         struct radeon_winsys_cs *cs,
 301                         enum pipe_transfer_usage usage);
 302
 303     /**
 304      * Unmap a buffer object from the client's address space.
 305      *
 306      * \param buf       A winsys buffer object to unmap.
 307      */
 308     void (*buffer_unmap)(struct pb_buffer *buf);
 309
 310     /**
 311      * Wait for the buffer and return true if the buffer is not used
 312      * by the device.
 313      *
 314      * The timeout of 0 will only return the status.
 315      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
 316      * is idle.
 317      */
 318     bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
 319                         enum radeon_bo_usage usage);
 320
 321     /**
 322      * Return buffer metadata.
 323      * (tiling info for display code, DRI sharing, and other data)
 324      *
 325      * \param buf       A winsys buffer object to get the flags from.
 326      * \param md        Metadata
 327      */
 328     void (*buffer_get_metadata)(struct pb_buffer *buf,
 329                                 struct radeon_bo_metadata *md);
 330
 331     /**
 332      * Set buffer metadata.
 333      * (tiling info for display code, DRI sharing, and other data)
 334      *
 335      * \param buf       A winsys buffer object to set the flags for.
 336      * \param md        Metadata
 337      */
 338     void (*buffer_set_metadata)(struct pb_buffer *buf,
 339                                 struct radeon_bo_metadata *md);
 340
 341     /**
 342      * Get a winsys buffer from a winsys handle. The internal structure
 343      * of the handle is platform-specific and only a winsys should access it.
 344      *
 345      * \param ws        The winsys this function is called from.
 346      * \param whandle   A winsys handle pointer as was received from a state
 347      *                  tracker.
 348      * \param stride    The returned buffer stride in bytes.
 349      */
 350     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 351                                             struct winsys_handle *whandle,
 352                                             unsigned *stride, unsigned *offset);
 353
 354     /**
 355      * Get a winsys buffer from a user pointer. The resulting buffer can't
 356      * be exported. Both pointer and size must be page aligned.
 357      *
 358      * \param ws        The winsys this function is called from.
 359      * \param pointer   User pointer to turn into a buffer object.
 360      * \param Size      Size in bytes for the new buffer.
 361      */
 362     struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
 363                                          void *pointer, uint64_t size);
 364
 365     /**
 366      * Whether the buffer was created from a user pointer.
 367      *
 368      * \param buf       A winsys buffer object
 369      * \return          whether \p buf was created via buffer_from_ptr
 370      */
 371     bool (*buffer_is_user_ptr)(struct pb_buffer *buf);
 372
 373     /** Whether the buffer was suballocated. */
 374     bool (*buffer_is_suballocated)(struct pb_buffer *buf);
 375
 376     /**
 377      * Get a winsys handle from a winsys buffer. The internal structure
 378      * of the handle is platform-specific and only a winsys should access it.
 379      *
 380      * \param buf       A winsys buffer object to get the handle from.
 381      * \param whandle   A winsys handle pointer.
 382      * \param stride    A stride of the buffer in bytes, for texturing.
 383      * \return          true on success.
 384      */
 385     bool (*buffer_get_handle)(struct pb_buffer *buf,
 386                               unsigned stride, unsigned offset,
 387                               unsigned slice_size,
 388                               struct winsys_handle *whandle);
 389
 390     /**
 391      * Change the commitment of a (64KB-page aligned) region of the given
 392      * sparse buffer.
 393      *
 394      * \warning There is no automatic synchronization with command submission.
 395      *
 396      * \note Only implemented by the amdgpu winsys.
 397      *
 398      * \return false on out of memory or other failure, true on success.
 399      */
 400     bool (*buffer_commit)(struct pb_buffer *buf,
 401                           uint64_t offset, uint64_t size,
 402                           bool commit);
 403
 404     /**
 405      * Return the virtual address of a buffer.
 406      *
 407      * When virtual memory is not in use, this is the offset relative to the
 408      * relocation base (non-zero for sub-allocated buffers).
 409      *
 410      * \param buf       A winsys buffer object
 411      * \return          virtual address
 412      */
 413     uint64_t (*buffer_get_virtual_address)(struct pb_buffer *buf);
 414
 415     /**
 416      * Return the offset of this buffer relative to the relocation base.
 417      * This is only non-zero for sub-allocated buffers.
 418      *
 419      * This is only supported in the radeon winsys, since amdgpu uses virtual
 420      * addresses in submissions even for the video engines.
 421      *
 422      * \param buf      A winsys buffer object
 423      * \return         the offset for relocations
 424      */
 425     unsigned (*buffer_get_reloc_offset)(struct pb_buffer *buf);
 426
 427     /**
 428      * Query the initial placement of the buffer from the kernel driver.
 429      */
 430     enum radeon_bo_domain (*buffer_get_initial_domain)(struct pb_buffer *buf);
 431
 432     /**************************************************************************
 433      * Command submission.
 434      *
 435      * Each pipe context should create its own command stream and submit
 436      * commands independently of other contexts.
 437      *************************************************************************/
 438
 439     /**
 440      * Create a command submission context.
 441      * Various command streams can be submitted to the same context.
 442      */
 443     struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 444
 445     /**
 446      * Destroy a context.
 447      */
 448     void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 449
 450     /**
 451      * Query a GPU reset status.
 452      */
 453     enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
 454
 455     /**
 456      * Create a command stream.
 457      *
 458      * \param ctx       The submission context
 459      * \param ring_type The ring type (GFX, DMA, UVD)
 460      * \param flush     Flush callback function associated with the command stream.
 461      * \param user      User pointer that will be passed to the flush callback.
 462      */
 463     struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys_ctx *ctx,
 464                                           enum ring_type ring_type,
 465                                           void (*flush)(void *ctx, unsigned flags,
 466                                                         struct pipe_fence_handle **fence),
 467                                           void *flush_ctx);
 468
 469     /**
 470      * Destroy a command stream.
 471      *
 472      * \param cs        A command stream to destroy.
 473      */
 474     void (*cs_destroy)(struct radeon_winsys_cs *cs);
 475
 476     /**
 477      * Add a buffer. Each buffer used by a CS must be added using this function.
 478      *
 479      * \param cs      Command stream
 480      * \param buf     Buffer
 481      * \param usage   Whether the buffer is used for read and/or write.
 482      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 483      * \param priority  A higher number means a greater chance of being
 484      *                  placed in the requested domain. 15 is the maximum.
 485      * \return Buffer index.
 486      */
 487     unsigned (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 488                              struct pb_buffer *buf,
 489                              enum radeon_bo_usage usage,
 490                              enum radeon_bo_domain domain,
 491                              enum radeon_bo_priority priority);
 492
 493     /**
 494      * Return the index of an already-added buffer.
 495      *
 496      * Not supported on amdgpu. Drivers with GPUVM should not care about
 497      * buffer indices.
 498      *
 499      * \param cs        Command stream
 500      * \param buf       Buffer
 501      * \return          The buffer index, or -1 if the buffer has not been added.
 502      */
 503     int (*cs_lookup_buffer)(struct radeon_winsys_cs *cs,
 504                             struct pb_buffer *buf);
 505
 506     /**
 507      * Return true if there is enough memory in VRAM and GTT for the buffers
 508      * added so far. If the validation fails, all buffers which have
 509      * been added since the last call of cs_validate will be removed and
 510      * the CS will be flushed (provided there are still any buffers).
 511      *
 512      * \param cs        A command stream to validate.
 513      */
 514     bool (*cs_validate)(struct radeon_winsys_cs *cs);
 515
 516     /**
 517      * Check whether the given number of dwords is available in the IB.
 518      * Optionally chain a new chunk of the IB if necessary and supported.
 519      *
 520      * \param cs        A command stream.
 521      * \param dw        Number of CS dwords requested by the caller.
 522      */
 523     bool (*cs_check_space)(struct radeon_winsys_cs *cs, unsigned dw);
 524
 525     /**
 526      * Return the buffer list.
 527      *
 528      * This is the buffer list as passed to the kernel, i.e. it only contains
 529      * the parent buffers of sub-allocated buffers.
 530      *
 531      * \param cs    Command stream
 532      * \param list  Returned buffer list. Set to NULL to query the count only.
 533      * \return      The buffer count.
 534      */
 535     unsigned (*cs_get_buffer_list)(struct radeon_winsys_cs *cs,
 536                                    struct radeon_bo_list_item *list);
 537
 538     /**
 539      * Flush a command stream.
 540      *
 541      * \param cs          A command stream to flush.
 542      * \param flags,      PIPE_FLUSH_* flags.
 543      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 544      *                    after the CS and is returned through this parameter.
 545      * \return Negative POSIX error code or 0 for success.
 546      *         Asynchronous submissions never return an error.
 547      */
 548     int (*cs_flush)(struct radeon_winsys_cs *cs,
 549                     unsigned flags,
 550                     struct pipe_fence_handle **fence);
 551
 552     /**
 553      * Create a fence before the CS is flushed.
 554      * The user must flush manually to complete the initializaton of the fence.
 555      *
 556      * The fence must not be used for anything except \ref cs_add_fence_dependency
 557      * before the flush.
 558      */
 559     struct pipe_fence_handle *(*cs_get_next_fence)(struct radeon_winsys_cs *cs);
 560
 561     /**
 562      * Return true if a buffer is referenced by a command stream.
 563      *
 564      * \param cs        A command stream.
 565      * \param buf       A winsys buffer.
 566      */
 567     bool (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
 568                                     struct pb_buffer *buf,
 569                                     enum radeon_bo_usage usage);
 570
 571     /**
 572      * Request access to a feature for a command stream.
 573      *
 574      * \param cs        A command stream.
 575      * \param fid       Feature ID, one of RADEON_FID_*
 576      * \param enable    Whether to enable or disable the feature.
 577      */
 578     bool (*cs_request_feature)(struct radeon_winsys_cs *cs,
 579                                enum radeon_feature_id fid,
 580                                bool enable);
 581      /**
 582       * Make sure all asynchronous flush of the cs have completed
 583       *
 584       * \param cs        A command stream.
 585       */
 586     void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
 587
 588     /**
 589      * Add a fence dependency to the CS, so that the CS will wait for
 590      * the fence before execution.
 591      */
 592     void (*cs_add_fence_dependency)(struct radeon_winsys_cs *cs,
 593                                     struct pipe_fence_handle *fence);
 594
 595     /**
 596      * Signal a syncobj when the CS finishes execution.
 597      */
 598     void (*cs_add_syncobj_signal)(struct radeon_winsys_cs *cs,
 599                                   struct pipe_fence_handle *fence);
 600
 601     /**
 602      * Wait for the fence and return true if the fence has been signalled.
 603      * The timeout of 0 will only return the status.
 604      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 605      * is signalled.
 606      */
 607     bool (*fence_wait)(struct radeon_winsys *ws,
 608                        struct pipe_fence_handle *fence,
 609                        uint64_t timeout);
 610
 611     /**
 612      * Reference counting for fences.
 613      */
 614     void (*fence_reference)(struct pipe_fence_handle **dst,
 615                             struct pipe_fence_handle *src);
 616
 617     /**
 618      * Create a new fence object corresponding to the given syncobj fd.
 619      */
 620     struct pipe_fence_handle *(*fence_import_syncobj)(struct radeon_winsys *ws,
 621                                                       int fd);
 622
 623     /**
 624      * Create a new fence object corresponding to the given sync_file.
 625      */
 626     struct pipe_fence_handle *(*fence_import_sync_file)(struct radeon_winsys *ws,
 627                                                         int fd);
 628
 629     /**
 630      * Return a sync_file FD corresponding to the given fence object.
 631      */
 632     int (*fence_export_sync_file)(struct radeon_winsys *ws,
 633                                   struct pipe_fence_handle *fence);
 634
 635     /**
 636      * Return a sync file FD that is already signalled.
 637      */
 638     int (*export_signalled_sync_file)(struct radeon_winsys *ws);
 639
 640     /**
 641      * Initialize surface
 642      *
 643      * \param ws        The winsys this function is called from.
 644      * \param tex       Input texture description
 645      * \param flags     Bitmask of RADEON_SURF_* flags
 646      * \param bpe       Bytes per pixel, it can be different for Z buffers.
 647      * \param mode      Preferred tile mode. (linear, 1D, or 2D)
 648      * \param surf      Output structure
 649      */
 650     int (*surface_init)(struct radeon_winsys *ws,
 651                         const struct pipe_resource *tex,
 652                         unsigned num_color_samples,
 653                         unsigned flags, unsigned bpe,
 654                         enum radeon_surf_mode mode,
 655                         struct radeon_surf *surf);
 656
 657     uint64_t (*query_value)(struct radeon_winsys *ws,
 658                             enum radeon_value_id value);
 659
 660     bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 661                            unsigned num_registers, uint32_t *out);
 662
 663     const char* (*get_chip_name)(struct radeon_winsys *ws);
 664 };
 665
 666 static inline bool radeon_emitted(struct radeon_winsys_cs *cs, unsigned num_dw)
 667 {
 668     return cs && (cs->prev_dw + cs->current.cdw > num_dw);
 669 }
 670
 671 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 672 {
 673     cs->current.buf[cs->current.cdw++] = value;
 674 }
 675
 676 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 677                                      const uint32_t *values, unsigned count)
 678 {
 679     memcpy(cs->current.buf + cs->current.cdw, values, count * 4);
 680     cs->current.cdw += count;
 681 }
 682
 683 enum radeon_heap {
 684     RADEON_HEAP_VRAM_NO_CPU_ACCESS,
 685     RADEON_HEAP_VRAM_READ_ONLY,
 686     RADEON_HEAP_VRAM_READ_ONLY_32BIT,
 687     RADEON_HEAP_VRAM_32BIT,
 688     RADEON_HEAP_VRAM,
 689     RADEON_HEAP_GTT_WC,
 690     RADEON_HEAP_GTT_WC_READ_ONLY,
 691     RADEON_HEAP_GTT_WC_READ_ONLY_32BIT,
 692     RADEON_HEAP_GTT_WC_32BIT,
 693     RADEON_HEAP_GTT,
 694     RADEON_MAX_SLAB_HEAPS,
 695     RADEON_MAX_CACHED_HEAPS = RADEON_MAX_SLAB_HEAPS,
 696 };
 697
 698 static inline enum radeon_bo_domain radeon_domain_from_heap(enum radeon_heap heap)
 699 {
 700     switch (heap) {
 701     case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
 702     case RADEON_HEAP_VRAM_READ_ONLY:
 703     case RADEON_HEAP_VRAM_READ_ONLY_32BIT:
 704     case RADEON_HEAP_VRAM_32BIT:
 705     case RADEON_HEAP_VRAM:
 706         return RADEON_DOMAIN_VRAM;
 707     case RADEON_HEAP_GTT_WC:
 708     case RADEON_HEAP_GTT_WC_READ_ONLY:
 709     case RADEON_HEAP_GTT_WC_READ_ONLY_32BIT:
 710     case RADEON_HEAP_GTT_WC_32BIT:
 711     case RADEON_HEAP_GTT:
 712         return RADEON_DOMAIN_GTT;
 713     default:
 714         assert(0);
 715         return (enum radeon_bo_domain)0;
 716     }
 717 }
 718
 719 static inline unsigned radeon_flags_from_heap(enum radeon_heap heap)
 720 {
 721     unsigned flags = RADEON_FLAG_NO_INTERPROCESS_SHARING |
 722                      (heap != RADEON_HEAP_GTT ? RADEON_FLAG_GTT_WC : 0);
 723
 724     switch (heap) {
 725     case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
 726         return flags |
 727                RADEON_FLAG_NO_CPU_ACCESS;
 728
 729     case RADEON_HEAP_VRAM_READ_ONLY:
 730     case RADEON_HEAP_GTT_WC_READ_ONLY:
 731         return flags |
 732                RADEON_FLAG_READ_ONLY;
 733
 734     case RADEON_HEAP_VRAM_READ_ONLY_32BIT:
 735     case RADEON_HEAP_GTT_WC_READ_ONLY_32BIT:
 736         return flags |
 737                RADEON_FLAG_READ_ONLY |
 738                RADEON_FLAG_32BIT;
 739
 740     case RADEON_HEAP_VRAM_32BIT:
 741     case RADEON_HEAP_GTT_WC_32BIT:
 742         return flags |
 743                RADEON_FLAG_32BIT;
 744
 745     case RADEON_HEAP_VRAM:
 746     case RADEON_HEAP_GTT_WC:
 747     case RADEON_HEAP_GTT:
 748     default:
 749         return flags;
 750     }
 751 }
 752
 753 /* Return the heap index for winsys allocators, or -1 on failure. */
 754 static inline int radeon_get_heap_index(enum radeon_bo_domain domain,
 755                                         enum radeon_bo_flag flags)
 756 {
 757     /* VRAM implies WC (write combining) */
 758     assert(!(domain & RADEON_DOMAIN_VRAM) || flags & RADEON_FLAG_GTT_WC);
 759     /* NO_CPU_ACCESS implies VRAM only. */
 760     assert(!(flags & RADEON_FLAG_NO_CPU_ACCESS) || domain == RADEON_DOMAIN_VRAM);
 761
 762     /* Resources with interprocess sharing don't use any winsys allocators. */
 763     if (!(flags & RADEON_FLAG_NO_INTERPROCESS_SHARING))
 764         return -1;
 765
 766     /* Unsupported flags: NO_SUBALLOC, SPARSE. */
 767     if (flags & ~(RADEON_FLAG_GTT_WC |
 768                   RADEON_FLAG_NO_CPU_ACCESS |
 769                   RADEON_FLAG_NO_INTERPROCESS_SHARING |
 770                   RADEON_FLAG_READ_ONLY |
 771                   RADEON_FLAG_32BIT))
 772         return -1;
 773
 774     switch (domain) {
 775     case RADEON_DOMAIN_VRAM:
 776         switch (flags & (RADEON_FLAG_NO_CPU_ACCESS |
 777                          RADEON_FLAG_READ_ONLY |
 778                          RADEON_FLAG_32BIT)) {
 779         case RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
 780         case RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_READ_ONLY:
 781             assert(!"NO_CPU_ACCESS | READ_ONLY doesn't make sense");
 782             return -1;
 783         case RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_32BIT:
 784             assert(!"NO_CPU_ACCESS with 32BIT is disallowed");
 785             return -1;
 786         case RADEON_FLAG_NO_CPU_ACCESS:
 787             return RADEON_HEAP_VRAM_NO_CPU_ACCESS;
 788         case RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
 789             return RADEON_HEAP_VRAM_READ_ONLY_32BIT;
 790         case RADEON_FLAG_READ_ONLY:
 791             return RADEON_HEAP_VRAM_READ_ONLY;
 792         case RADEON_FLAG_32BIT:
 793             return RADEON_HEAP_VRAM_32BIT;
 794         case 0:
 795             return RADEON_HEAP_VRAM;
 796         }
 797         break;
 798     case RADEON_DOMAIN_GTT:
 799         switch (flags & (RADEON_FLAG_GTT_WC |
 800                          RADEON_FLAG_READ_ONLY |
 801                          RADEON_FLAG_32BIT)) {
 802         case RADEON_FLAG_GTT_WC | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
 803             return RADEON_HEAP_GTT_WC_READ_ONLY_32BIT;
 804         case RADEON_FLAG_GTT_WC | RADEON_FLAG_READ_ONLY:
 805             return RADEON_HEAP_GTT_WC_READ_ONLY;
 806         case RADEON_FLAG_GTT_WC | RADEON_FLAG_32BIT:
 807             return RADEON_HEAP_GTT_WC_32BIT;
 808         case RADEON_FLAG_GTT_WC:
 809             return RADEON_HEAP_GTT_WC;
 810         case RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
 811         case RADEON_FLAG_READ_ONLY:
 812             assert(!"READ_ONLY without WC is disallowed");
 813             return -1;
 814         case RADEON_FLAG_32BIT:
 815             assert(!"32BIT without WC is disallowed");
 816             return -1;
 817         case 0:
 818             return RADEON_HEAP_GTT;
 819         }
 820         break;
 821     default:
 822         break;
 823     }
 824     return -1;
 825 }
 826
 827 #endif