src/gallium/drivers/radeon/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  * Copyright 2018 Advanced Micro Devices, Inc.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * on the rights to use, copy, modify, merge, publish, distribute, sub
  11  * license, and/or sell copies of the Software, and to permit persons to whom
  12  * the Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  25
  26 #ifndef RADEON_WINSYS_H
  27 #define RADEON_WINSYS_H
  28
  29 /* The public winsys interface header for the radeon driver. */
  30
  31 /* Whether the next IB can start immediately and not wait for draws and
  32  * dispatches from the current IB to finish. */
  33 #define RADEON_FLUSH_START_NEXT_GFX_IB_NOW      (1u << 31)
  34
  35 #define RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW \
  36         (PIPE_FLUSH_ASYNC | RADEON_FLUSH_START_NEXT_GFX_IB_NOW)
  37
  38 #include "pipebuffer/pb_buffer.h"
  39
  40 #include "amd/common/ac_gpu_info.h"
  41 #include "amd/common/ac_surface.h"
  42
  43 /* Tiling flags. */
  44 enum radeon_bo_layout {
  45     RADEON_LAYOUT_LINEAR = 0,
  46     RADEON_LAYOUT_TILED,
  47     RADEON_LAYOUT_SQUARETILED,
  48
  49     RADEON_LAYOUT_UNKNOWN
  50 };
  51
  52 enum radeon_bo_domain { /* bitfield */
  53     RADEON_DOMAIN_GTT  = 2,
  54     RADEON_DOMAIN_VRAM = 4,
  55     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  56 };
  57
  58 enum radeon_bo_flag { /* bitfield */
  59     RADEON_FLAG_GTT_WC =        (1 << 0),
  60     RADEON_FLAG_NO_CPU_ACCESS = (1 << 1),
  61     RADEON_FLAG_NO_SUBALLOC =   (1 << 2),
  62     RADEON_FLAG_SPARSE =        (1 << 3),
  63     RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 4),
  64     RADEON_FLAG_READ_ONLY =     (1 << 5),
  65     RADEON_FLAG_32BIT =    (1 << 6),
  66 };
  67
  68 enum radeon_bo_usage { /* bitfield */
  69     RADEON_USAGE_READ = 2,
  70     RADEON_USAGE_WRITE = 4,
  71     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE,
  72
  73     /* The winsys ensures that the CS submission will be scheduled after
  74      * previously flushed CSs referencing this BO in a conflicting way.
  75      */
  76     RADEON_USAGE_SYNCHRONIZED = 8
  77 };
  78
  79 #define RADEON_SPARSE_PAGE_SIZE (64 * 1024)
  80
  81 enum ring_type {
  82     RING_GFX = 0,
  83     RING_COMPUTE,
  84     RING_DMA,
  85     RING_UVD,
  86     RING_VCE,
  87     RING_UVD_ENC,
  88     RING_VCN_DEC,
  89     RING_VCN_ENC,
  90     RING_LAST,
  91 };
  92
  93 enum radeon_value_id {
  94     RADEON_REQUESTED_VRAM_MEMORY,
  95     RADEON_REQUESTED_GTT_MEMORY,
  96     RADEON_MAPPED_VRAM,
  97     RADEON_MAPPED_GTT,
  98     RADEON_BUFFER_WAIT_TIME_NS,
  99     RADEON_NUM_MAPPED_BUFFERS,
 100     RADEON_TIMESTAMP,
 101     RADEON_NUM_GFX_IBS,
 102     RADEON_NUM_SDMA_IBS,
 103     RADEON_GFX_BO_LIST_COUNTER, /* number of BOs submitted in gfx IBs */
 104     RADEON_GFX_IB_SIZE_COUNTER,
 105     RADEON_NUM_BYTES_MOVED,
 106     RADEON_NUM_EVICTIONS,
 107     RADEON_NUM_VRAM_CPU_PAGE_FAULTS,
 108     RADEON_VRAM_USAGE,
 109     RADEON_VRAM_VIS_USAGE,
 110     RADEON_GTT_USAGE,
 111     RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
 112     RADEON_CURRENT_SCLK,
 113     RADEON_CURRENT_MCLK,
 114     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
 115     RADEON_CS_THREAD_TIME,
 116 };
 117
 118 enum radeon_bo_priority {
 119     /* Each group of two has the same priority. */
 120     RADEON_PRIO_FENCE = 0,
 121     RADEON_PRIO_TRACE,
 122
 123     RADEON_PRIO_SO_FILLED_SIZE = 2,
 124     RADEON_PRIO_QUERY,
 125
 126     RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
 127     RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
 128
 129     RADEON_PRIO_DRAW_INDIRECT = 6,
 130     RADEON_PRIO_INDEX_BUFFER,
 131
 132     RADEON_PRIO_CP_DMA = 8,
 133     RADEON_PRIO_BORDER_COLORS,
 134
 135     RADEON_PRIO_CONST_BUFFER = 10,
 136     RADEON_PRIO_DESCRIPTORS,
 137
 138     RADEON_PRIO_SAMPLER_BUFFER = 12,
 139     RADEON_PRIO_VERTEX_BUFFER,
 140
 141     RADEON_PRIO_SHADER_RW_BUFFER = 14,
 142     RADEON_PRIO_COMPUTE_GLOBAL,
 143
 144     RADEON_PRIO_SAMPLER_TEXTURE = 16,
 145     RADEON_PRIO_SHADER_RW_IMAGE,
 146
 147     RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 18,
 148     RADEON_PRIO_COLOR_BUFFER,
 149
 150     RADEON_PRIO_DEPTH_BUFFER = 20,
 151
 152     RADEON_PRIO_COLOR_BUFFER_MSAA = 22,
 153
 154     RADEON_PRIO_DEPTH_BUFFER_MSAA = 24,
 155
 156     RADEON_PRIO_SEPARATE_META = 26,
 157     RADEON_PRIO_SHADER_BINARY, /* the hw can't hide instruction cache misses */
 158
 159     RADEON_PRIO_SHADER_RINGS = 28,
 160
 161     RADEON_PRIO_SCRATCH_BUFFER = 30,
 162     /* 31 is the maximum value */
 163 };
 164
 165 struct winsys_handle;
 166 struct radeon_winsys_ctx;
 167
 168 struct radeon_cmdbuf_chunk {
 169     unsigned cdw;  /* Number of used dwords. */
 170     unsigned max_dw; /* Maximum number of dwords. */
 171     uint32_t *buf; /* The base pointer of the chunk. */
 172 };
 173
 174 struct radeon_cmdbuf {
 175     struct radeon_cmdbuf_chunk current;
 176     struct radeon_cmdbuf_chunk *prev;
 177     unsigned                      num_prev; /* Number of previous chunks. */
 178     unsigned                      max_prev; /* Space in array pointed to by prev. */
 179     unsigned                      prev_dw; /* Total number of dwords in previous chunks. */
 180
 181     /* Memory usage of the buffer list. These are always 0 for preamble IBs. */
 182     uint64_t                      used_vram;
 183     uint64_t                      used_gart;
 184 };
 185
 186 /* Tiling info for display code, DRI sharing, and other data. */
 187 struct radeon_bo_metadata {
 188     /* Tiling flags describing the texture layout for display code
 189      * and DRI sharing.
 190      */
 191     union {
 192         struct {
 193             enum radeon_bo_layout   microtile;
 194             enum radeon_bo_layout   macrotile;
 195             unsigned                pipe_config;
 196             unsigned                bankw;
 197             unsigned                bankh;
 198             unsigned                tile_split;
 199             unsigned                mtilea;
 200             unsigned                num_banks;
 201             unsigned                stride;
 202             bool                    scanout;
 203         } legacy;
 204
 205         struct {
 206             /* surface flags */
 207             unsigned swizzle_mode:5;
 208         } gfx9;
 209     } u;
 210
 211     /* Additional metadata associated with the buffer, in bytes.
 212      * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 213      * Supported by amdgpu only.
 214      */
 215     uint32_t                size_metadata;
 216     uint32_t                metadata[64];
 217 };
 218
 219 enum radeon_feature_id {
 220     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 221     RADEON_FID_R300_CMASK_ACCESS,
 222 };
 223
 224 struct radeon_bo_list_item {
 225     uint64_t bo_size;
 226     uint64_t vm_address;
 227     uint32_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
 228 };
 229
 230 struct radeon_winsys {
 231     /**
 232      * The screen object this winsys was created for
 233      */
 234     struct pipe_screen *screen;
 235
 236     /**
 237      * Decrement the winsys reference count.
 238      *
 239      * \param ws  The winsys this function is called for.
 240      * \return    True if the winsys and screen should be destroyed.
 241      */
 242     bool (*unref)(struct radeon_winsys *ws);
 243
 244     /**
 245      * Destroy this winsys.
 246      *
 247      * \param ws        The winsys this function is called from.
 248      */
 249     void (*destroy)(struct radeon_winsys *ws);
 250
 251     /**
 252      * Query an info structure from winsys.
 253      *
 254      * \param ws        The winsys this function is called from.
 255      * \param info      Return structure
 256      */
 257     void (*query_info)(struct radeon_winsys *ws,
 258                        struct radeon_info *info);
 259
 260     /**
 261      * A hint for the winsys that it should pin its execution threads to
 262      * a group of cores sharing a specific L3 cache if the CPU has multiple
 263      * L3 caches. This is needed for good multithreading performance on
 264      * AMD Zen CPUs.
 265      */
 266     void (*pin_threads_to_L3_cache)(struct radeon_winsys *ws, unsigned cache);
 267
 268     /**************************************************************************
 269      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 270      *
 271      * Remember that gallium gets to choose the interface it needs, and the
 272      * window systems must then implement that interface (rather than the
 273      * other way around...).
 274      *************************************************************************/
 275
 276     /**
 277      * Create a buffer object.
 278      *
 279      * \param ws        The winsys this function is called from.
 280      * \param size      The size to allocate.
 281      * \param alignment An alignment of the buffer in memory.
 282      * \param use_reusable_pool Whether the cache buffer manager should be used.
 283      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 284      * \return          The created buffer object.
 285      */
 286     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 287                                        uint64_t size,
 288                                        unsigned alignment,
 289                                        enum radeon_bo_domain domain,
 290                                        enum radeon_bo_flag flags);
 291
 292     /**
 293      * Map the entire data store of a buffer object into the client's address
 294      * space.
 295      *
 296      * \param buf       A winsys buffer object to map.
 297      * \param cs        A command stream to flush if the buffer is referenced by it.
 298      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 299      * \return          The pointer at the beginning of the buffer.
 300      */
 301     void *(*buffer_map)(struct pb_buffer *buf,
 302                         struct radeon_cmdbuf *cs,
 303                         enum pipe_transfer_usage usage);
 304
 305     /**
 306      * Unmap a buffer object from the client's address space.
 307      *
 308      * \param buf       A winsys buffer object to unmap.
 309      */
 310     void (*buffer_unmap)(struct pb_buffer *buf);
 311
 312     /**
 313      * Wait for the buffer and return true if the buffer is not used
 314      * by the device.
 315      *
 316      * The timeout of 0 will only return the status.
 317      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
 318      * is idle.
 319      */
 320     bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
 321                         enum radeon_bo_usage usage);
 322
 323     /**
 324      * Return buffer metadata.
 325      * (tiling info for display code, DRI sharing, and other data)
 326      *
 327      * \param buf       A winsys buffer object to get the flags from.
 328      * \param md        Metadata
 329      */
 330     void (*buffer_get_metadata)(struct pb_buffer *buf,
 331                                 struct radeon_bo_metadata *md);
 332
 333     /**
 334      * Set buffer metadata.
 335      * (tiling info for display code, DRI sharing, and other data)
 336      *
 337      * \param buf       A winsys buffer object to set the flags for.
 338      * \param md        Metadata
 339      */
 340     void (*buffer_set_metadata)(struct pb_buffer *buf,
 341                                 struct radeon_bo_metadata *md);
 342
 343     /**
 344      * Get a winsys buffer from a winsys handle. The internal structure
 345      * of the handle is platform-specific and only a winsys should access it.
 346      *
 347      * \param ws        The winsys this function is called from.
 348      * \param whandle   A winsys handle pointer as was received from a state
 349      *                  tracker.
 350      * \param stride    The returned buffer stride in bytes.
 351      */
 352     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 353                                             struct winsys_handle *whandle,
 354                                             unsigned *stride, unsigned *offset);
 355
 356     /**
 357      * Get a winsys buffer from a user pointer. The resulting buffer can't
 358      * be exported. Both pointer and size must be page aligned.
 359      *
 360      * \param ws        The winsys this function is called from.
 361      * \param pointer   User pointer to turn into a buffer object.
 362      * \param Size      Size in bytes for the new buffer.
 363      */
 364     struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
 365                                          void *pointer, uint64_t size);
 366
 367     /**
 368      * Whether the buffer was created from a user pointer.
 369      *
 370      * \param buf       A winsys buffer object
 371      * \return          whether \p buf was created via buffer_from_ptr
 372      */
 373     bool (*buffer_is_user_ptr)(struct pb_buffer *buf);
 374
 375     /** Whether the buffer was suballocated. */
 376     bool (*buffer_is_suballocated)(struct pb_buffer *buf);
 377
 378     /**
 379      * Get a winsys handle from a winsys buffer. The internal structure
 380      * of the handle is platform-specific and only a winsys should access it.
 381      *
 382      * \param buf       A winsys buffer object to get the handle from.
 383      * \param whandle   A winsys handle pointer.
 384      * \param stride    A stride of the buffer in bytes, for texturing.
 385      * \return          true on success.
 386      */
 387     bool (*buffer_get_handle)(struct pb_buffer *buf,
 388                               unsigned stride, unsigned offset,
 389                               unsigned slice_size,
 390                               struct winsys_handle *whandle);
 391
 392     /**
 393      * Change the commitment of a (64KB-page aligned) region of the given
 394      * sparse buffer.
 395      *
 396      * \warning There is no automatic synchronization with command submission.
 397      *
 398      * \note Only implemented by the amdgpu winsys.
 399      *
 400      * \return false on out of memory or other failure, true on success.
 401      */
 402     bool (*buffer_commit)(struct pb_buffer *buf,
 403                           uint64_t offset, uint64_t size,
 404                           bool commit);
 405
 406     /**
 407      * Return the virtual address of a buffer.
 408      *
 409      * When virtual memory is not in use, this is the offset relative to the
 410      * relocation base (non-zero for sub-allocated buffers).
 411      *
 412      * \param buf       A winsys buffer object
 413      * \return          virtual address
 414      */
 415     uint64_t (*buffer_get_virtual_address)(struct pb_buffer *buf);
 416
 417     /**
 418      * Return the offset of this buffer relative to the relocation base.
 419      * This is only non-zero for sub-allocated buffers.
 420      *
 421      * This is only supported in the radeon winsys, since amdgpu uses virtual
 422      * addresses in submissions even for the video engines.
 423      *
 424      * \param buf      A winsys buffer object
 425      * \return         the offset for relocations
 426      */
 427     unsigned (*buffer_get_reloc_offset)(struct pb_buffer *buf);
 428
 429     /**
 430      * Query the initial placement of the buffer from the kernel driver.
 431      */
 432     enum radeon_bo_domain (*buffer_get_initial_domain)(struct pb_buffer *buf);
 433
 434     /**************************************************************************
 435      * Command submission.
 436      *
 437      * Each pipe context should create its own command stream and submit
 438      * commands independently of other contexts.
 439      *************************************************************************/
 440
 441     /**
 442      * Create a command submission context.
 443      * Various command streams can be submitted to the same context.
 444      */
 445     struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 446
 447     /**
 448      * Destroy a context.
 449      */
 450     void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 451
 452     /**
 453      * Query a GPU reset status.
 454      */
 455     enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
 456
 457     /**
 458      * Create a command stream.
 459      *
 460      * \param ctx       The submission context
 461      * \param ring_type The ring type (GFX, DMA, UVD)
 462      * \param flush     Flush callback function associated with the command stream.
 463      * \param user      User pointer that will be passed to the flush callback.
 464      */
 465     struct radeon_cmdbuf *(*cs_create)(struct radeon_winsys_ctx *ctx,
 466                                           enum ring_type ring_type,
 467                                           void (*flush)(void *ctx, unsigned flags,
 468                                                         struct pipe_fence_handle **fence),
 469                                           void *flush_ctx);
 470
 471     /**
 472      * Destroy a command stream.
 473      *
 474      * \param cs        A command stream to destroy.
 475      */
 476     void (*cs_destroy)(struct radeon_cmdbuf *cs);
 477
 478     /**
 479      * Add a buffer. Each buffer used by a CS must be added using this function.
 480      *
 481      * \param cs      Command stream
 482      * \param buf     Buffer
 483      * \param usage   Whether the buffer is used for read and/or write.
 484      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 485      * \param priority  A higher number means a greater chance of being
 486      *                  placed in the requested domain. 15 is the maximum.
 487      * \return Buffer index.
 488      */
 489     unsigned (*cs_add_buffer)(struct radeon_cmdbuf *cs,
 490                              struct pb_buffer *buf,
 491                              enum radeon_bo_usage usage,
 492                              enum radeon_bo_domain domain,
 493                              enum radeon_bo_priority priority);
 494
 495     /**
 496      * Return the index of an already-added buffer.
 497      *
 498      * Not supported on amdgpu. Drivers with GPUVM should not care about
 499      * buffer indices.
 500      *
 501      * \param cs        Command stream
 502      * \param buf       Buffer
 503      * \return          The buffer index, or -1 if the buffer has not been added.
 504      */
 505     int (*cs_lookup_buffer)(struct radeon_cmdbuf *cs,
 506                             struct pb_buffer *buf);
 507
 508     /**
 509      * Return true if there is enough memory in VRAM and GTT for the buffers
 510      * added so far. If the validation fails, all buffers which have
 511      * been added since the last call of cs_validate will be removed and
 512      * the CS will be flushed (provided there are still any buffers).
 513      *
 514      * \param cs        A command stream to validate.
 515      */
 516     bool (*cs_validate)(struct radeon_cmdbuf *cs);
 517
 518     /**
 519      * Check whether the given number of dwords is available in the IB.
 520      * Optionally chain a new chunk of the IB if necessary and supported.
 521      *
 522      * \param cs        A command stream.
 523      * \param dw        Number of CS dwords requested by the caller.
 524      */
 525     bool (*cs_check_space)(struct radeon_cmdbuf *cs, unsigned dw);
 526
 527     /**
 528      * Return the buffer list.
 529      *
 530      * This is the buffer list as passed to the kernel, i.e. it only contains
 531      * the parent buffers of sub-allocated buffers.
 532      *
 533      * \param cs    Command stream
 534      * \param list  Returned buffer list. Set to NULL to query the count only.
 535      * \return      The buffer count.
 536      */
 537     unsigned (*cs_get_buffer_list)(struct radeon_cmdbuf *cs,
 538                                    struct radeon_bo_list_item *list);
 539
 540     /**
 541      * Flush a command stream.
 542      *
 543      * \param cs          A command stream to flush.
 544      * \param flags,      PIPE_FLUSH_* flags.
 545      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 546      *                    after the CS and is returned through this parameter.
 547      * \return Negative POSIX error code or 0 for success.
 548      *         Asynchronous submissions never return an error.
 549      */
 550     int (*cs_flush)(struct radeon_cmdbuf *cs,
 551                     unsigned flags,
 552                     struct pipe_fence_handle **fence);
 553
 554     /**
 555      * Create a fence before the CS is flushed.
 556      * The user must flush manually to complete the initializaton of the fence.
 557      *
 558      * The fence must not be used for anything except \ref cs_add_fence_dependency
 559      * before the flush.
 560      */
 561     struct pipe_fence_handle *(*cs_get_next_fence)(struct radeon_cmdbuf *cs);
 562
 563     /**
 564      * Return true if a buffer is referenced by a command stream.
 565      *
 566      * \param cs        A command stream.
 567      * \param buf       A winsys buffer.
 568      */
 569     bool (*cs_is_buffer_referenced)(struct radeon_cmdbuf *cs,
 570                                     struct pb_buffer *buf,
 571                                     enum radeon_bo_usage usage);
 572
 573     /**
 574      * Request access to a feature for a command stream.
 575      *
 576      * \param cs        A command stream.
 577      * \param fid       Feature ID, one of RADEON_FID_*
 578      * \param enable    Whether to enable or disable the feature.
 579      */
 580     bool (*cs_request_feature)(struct radeon_cmdbuf *cs,
 581                                enum radeon_feature_id fid,
 582                                bool enable);
 583      /**
 584       * Make sure all asynchronous flush of the cs have completed
 585       *
 586       * \param cs        A command stream.
 587       */
 588     void (*cs_sync_flush)(struct radeon_cmdbuf *cs);
 589
 590     /**
 591      * Add a fence dependency to the CS, so that the CS will wait for
 592      * the fence before execution.
 593      */
 594     void (*cs_add_fence_dependency)(struct radeon_cmdbuf *cs,
 595                                     struct pipe_fence_handle *fence);
 596
 597     /**
 598      * Signal a syncobj when the CS finishes execution.
 599      */
 600     void (*cs_add_syncobj_signal)(struct radeon_cmdbuf *cs,
 601                                   struct pipe_fence_handle *fence);
 602
 603     /**
 604      * Wait for the fence and return true if the fence has been signalled.
 605      * The timeout of 0 will only return the status.
 606      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 607      * is signalled.
 608      */
 609     bool (*fence_wait)(struct radeon_winsys *ws,
 610                        struct pipe_fence_handle *fence,
 611                        uint64_t timeout);
 612
 613     /**
 614      * Reference counting for fences.
 615      */
 616     void (*fence_reference)(struct pipe_fence_handle **dst,
 617                             struct pipe_fence_handle *src);
 618
 619     /**
 620      * Create a new fence object corresponding to the given syncobj fd.
 621      */
 622     struct pipe_fence_handle *(*fence_import_syncobj)(struct radeon_winsys *ws,
 623                                                       int fd);
 624
 625     /**
 626      * Create a new fence object corresponding to the given sync_file.
 627      */
 628     struct pipe_fence_handle *(*fence_import_sync_file)(struct radeon_winsys *ws,
 629                                                         int fd);
 630
 631     /**
 632      * Return a sync_file FD corresponding to the given fence object.
 633      */
 634     int (*fence_export_sync_file)(struct radeon_winsys *ws,
 635                                   struct pipe_fence_handle *fence);
 636
 637     /**
 638      * Return a sync file FD that is already signalled.
 639      */
 640     int (*export_signalled_sync_file)(struct radeon_winsys *ws);
 641
 642     /**
 643      * Initialize surface
 644      *
 645      * \param ws        The winsys this function is called from.
 646      * \param tex       Input texture description
 647      * \param flags     Bitmask of RADEON_SURF_* flags
 648      * \param bpe       Bytes per pixel, it can be different for Z buffers.
 649      * \param mode      Preferred tile mode. (linear, 1D, or 2D)
 650      * \param surf      Output structure
 651      */
 652     int (*surface_init)(struct radeon_winsys *ws,
 653                         const struct pipe_resource *tex,
 654                         unsigned flags, unsigned bpe,
 655                         enum radeon_surf_mode mode,
 656                         struct radeon_surf *surf);
 657
 658     uint64_t (*query_value)(struct radeon_winsys *ws,
 659                             enum radeon_value_id value);
 660
 661     bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 662                            unsigned num_registers, uint32_t *out);
 663
 664     const char* (*get_chip_name)(struct radeon_winsys *ws);
 665 };
 666
 667 static inline bool radeon_emitted(struct radeon_cmdbuf *cs, unsigned num_dw)
 668 {
 669     return cs && (cs->prev_dw + cs->current.cdw > num_dw);
 670 }
 671
 672 static inline void radeon_emit(struct radeon_cmdbuf *cs, uint32_t value)
 673 {
 674     cs->current.buf[cs->current.cdw++] = value;
 675 }
 676
 677 static inline void radeon_emit_array(struct radeon_cmdbuf *cs,
 678                                      const uint32_t *values, unsigned count)
 679 {
 680     memcpy(cs->current.buf + cs->current.cdw, values, count * 4);
 681     cs->current.cdw += count;
 682 }
 683
 684 enum radeon_heap {
 685     RADEON_HEAP_VRAM_NO_CPU_ACCESS,
 686     RADEON_HEAP_VRAM_READ_ONLY,
 687     RADEON_HEAP_VRAM_READ_ONLY_32BIT,
 688     RADEON_HEAP_VRAM_32BIT,
 689     RADEON_HEAP_VRAM,
 690     RADEON_HEAP_GTT_WC,
 691     RADEON_HEAP_GTT_WC_READ_ONLY,
 692     RADEON_HEAP_GTT_WC_READ_ONLY_32BIT,
 693     RADEON_HEAP_GTT_WC_32BIT,
 694     RADEON_HEAP_GTT,
 695     RADEON_MAX_SLAB_HEAPS,
 696     RADEON_MAX_CACHED_HEAPS = RADEON_MAX_SLAB_HEAPS,
 697 };
 698
 699 static inline enum radeon_bo_domain radeon_domain_from_heap(enum radeon_heap heap)
 700 {
 701     switch (heap) {
 702     case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
 703     case RADEON_HEAP_VRAM_READ_ONLY:
 704     case RADEON_HEAP_VRAM_READ_ONLY_32BIT:
 705     case RADEON_HEAP_VRAM_32BIT:
 706     case RADEON_HEAP_VRAM:
 707         return RADEON_DOMAIN_VRAM;
 708     case RADEON_HEAP_GTT_WC:
 709     case RADEON_HEAP_GTT_WC_READ_ONLY:
 710     case RADEON_HEAP_GTT_WC_READ_ONLY_32BIT:
 711     case RADEON_HEAP_GTT_WC_32BIT:
 712     case RADEON_HEAP_GTT:
 713         return RADEON_DOMAIN_GTT;
 714     default:
 715         assert(0);
 716         return (enum radeon_bo_domain)0;
 717     }
 718 }
 719
 720 static inline unsigned radeon_flags_from_heap(enum radeon_heap heap)
 721 {
 722     unsigned flags = RADEON_FLAG_NO_INTERPROCESS_SHARING |
 723                      (heap != RADEON_HEAP_GTT ? RADEON_FLAG_GTT_WC : 0);
 724
 725     switch (heap) {
 726     case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
 727         return flags |
 728                RADEON_FLAG_NO_CPU_ACCESS;
 729
 730     case RADEON_HEAP_VRAM_READ_ONLY:
 731     case RADEON_HEAP_GTT_WC_READ_ONLY:
 732         return flags |
 733                RADEON_FLAG_READ_ONLY;
 734
 735     case RADEON_HEAP_VRAM_READ_ONLY_32BIT:
 736     case RADEON_HEAP_GTT_WC_READ_ONLY_32BIT:
 737         return flags |
 738                RADEON_FLAG_READ_ONLY |
 739                RADEON_FLAG_32BIT;
 740
 741     case RADEON_HEAP_VRAM_32BIT:
 742     case RADEON_HEAP_GTT_WC_32BIT:
 743         return flags |
 744                RADEON_FLAG_32BIT;
 745
 746     case RADEON_HEAP_VRAM:
 747     case RADEON_HEAP_GTT_WC:
 748     case RADEON_HEAP_GTT:
 749     default:
 750         return flags;
 751     }
 752 }
 753
 754 /* Return the heap index for winsys allocators, or -1 on failure. */
 755 static inline int radeon_get_heap_index(enum radeon_bo_domain domain,
 756                                         enum radeon_bo_flag flags)
 757 {
 758     /* VRAM implies WC (write combining) */
 759     assert(!(domain & RADEON_DOMAIN_VRAM) || flags & RADEON_FLAG_GTT_WC);
 760     /* NO_CPU_ACCESS implies VRAM only. */
 761     assert(!(flags & RADEON_FLAG_NO_CPU_ACCESS) || domain == RADEON_DOMAIN_VRAM);
 762
 763     /* Resources with interprocess sharing don't use any winsys allocators. */
 764     if (!(flags & RADEON_FLAG_NO_INTERPROCESS_SHARING))
 765         return -1;
 766
 767     /* Unsupported flags: NO_SUBALLOC, SPARSE. */
 768     if (flags & ~(RADEON_FLAG_GTT_WC |
 769                   RADEON_FLAG_NO_CPU_ACCESS |
 770                   RADEON_FLAG_NO_INTERPROCESS_SHARING |
 771                   RADEON_FLAG_READ_ONLY |
 772                   RADEON_FLAG_32BIT))
 773         return -1;
 774
 775     switch (domain) {
 776     case RADEON_DOMAIN_VRAM:
 777         switch (flags & (RADEON_FLAG_NO_CPU_ACCESS |
 778                          RADEON_FLAG_READ_ONLY |
 779                          RADEON_FLAG_32BIT)) {
 780         case RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
 781         case RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_READ_ONLY:
 782             assert(!"NO_CPU_ACCESS | READ_ONLY doesn't make sense");
 783             return -1;
 784         case RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_32BIT:
 785             assert(!"NO_CPU_ACCESS with 32BIT is disallowed");
 786             return -1;
 787         case RADEON_FLAG_NO_CPU_ACCESS:
 788             return RADEON_HEAP_VRAM_NO_CPU_ACCESS;
 789         case RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
 790             return RADEON_HEAP_VRAM_READ_ONLY_32BIT;
 791         case RADEON_FLAG_READ_ONLY:
 792             return RADEON_HEAP_VRAM_READ_ONLY;
 793         case RADEON_FLAG_32BIT:
 794             return RADEON_HEAP_VRAM_32BIT;
 795         case 0:
 796             return RADEON_HEAP_VRAM;
 797         }
 798         break;
 799     case RADEON_DOMAIN_GTT:
 800         switch (flags & (RADEON_FLAG_GTT_WC |
 801                          RADEON_FLAG_READ_ONLY |
 802                          RADEON_FLAG_32BIT)) {
 803         case RADEON_FLAG_GTT_WC | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
 804             return RADEON_HEAP_GTT_WC_READ_ONLY_32BIT;
 805         case RADEON_FLAG_GTT_WC | RADEON_FLAG_READ_ONLY:
 806             return RADEON_HEAP_GTT_WC_READ_ONLY;
 807         case RADEON_FLAG_GTT_WC | RADEON_FLAG_32BIT:
 808             return RADEON_HEAP_GTT_WC_32BIT;
 809         case RADEON_FLAG_GTT_WC:
 810             return RADEON_HEAP_GTT_WC;
 811         case RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
 812         case RADEON_FLAG_READ_ONLY:
 813             assert(!"READ_ONLY without WC is disallowed");
 814             return -1;
 815         case RADEON_FLAG_32BIT:
 816             assert(!"32BIT without WC is disallowed");
 817             return -1;
 818         case 0:
 819             return RADEON_HEAP_GTT;
 820         }
 821         break;
 822     default:
 823         break;
 824     }
 825     return -1;
 826 }
 827
 828 #endif