2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 #ifndef RADEON_WINSYS_H
25 #define RADEON_WINSYS_H
27 /* The public winsys interface header for the radeon driver. */
29 /* R300 features in DRM.
33 * - GB_Z_PEQ_CONFIG on rv350->r4xx
34 * - R500 FG_ALPHA_VALUE
37 * - R500 US_FORMAT regs
38 * - R500 ARGB2101010 colorbuffer
43 #include "pipebuffer/pb_buffer.h"
45 #define RADEON_FLUSH_ASYNC (1 << 0)
46 #define RADEON_FLUSH_KEEP_TILING_FLAGS (1 << 1) /* needs DRM 2.12.0 */
47 #define RADEON_FLUSH_COMPUTE (1 << 2)
48 #define RADEON_FLUSH_END_OF_FRAME (1 << 3)
51 enum radeon_bo_layout
{
52 RADEON_LAYOUT_LINEAR
= 0,
54 RADEON_LAYOUT_SQUARETILED
,
59 enum radeon_bo_domain
{ /* bitfield */
60 RADEON_DOMAIN_GTT
= 2,
61 RADEON_DOMAIN_VRAM
= 4,
62 RADEON_DOMAIN_VRAM_GTT
= RADEON_DOMAIN_VRAM
| RADEON_DOMAIN_GTT
65 enum radeon_bo_flag
{ /* bitfield */
66 RADEON_FLAG_GTT_WC
= (1 << 0),
67 RADEON_FLAG_CPU_ACCESS
= (1 << 1),
68 RADEON_FLAG_NO_CPU_ACCESS
= (1 << 2),
71 enum radeon_bo_usage
{ /* bitfield */
72 RADEON_USAGE_READ
= 2,
73 RADEON_USAGE_WRITE
= 4,
74 RADEON_USAGE_READWRITE
= RADEON_USAGE_READ
| RADEON_USAGE_WRITE
79 CHIP_R300
, /* R3xx-based cores. */
87 CHIP_R420
, /* R4xx-based cores. */
96 CHIP_RV515
, /* R5xx-based cores. */
161 enum radeon_value_id
{
162 RADEON_REQUESTED_VRAM_MEMORY
,
163 RADEON_REQUESTED_GTT_MEMORY
,
164 RADEON_BUFFER_WAIT_TIME_NS
,
166 RADEON_NUM_CS_FLUSHES
,
167 RADEON_NUM_BYTES_MOVED
,
170 RADEON_GPU_TEMPERATURE
, /* DRM 2.42.0 */
173 RADEON_GPU_RESET_COUNTER
, /* DRM 2.43.0 */
176 enum radeon_bo_priority
{
178 RADEON_PRIO_SHADER_DATA
, /* shader code, resource descriptors */
179 RADEON_PRIO_SHADER_BUFFER_RO
, /* read-only */
180 RADEON_PRIO_SHADER_TEXTURE_RO
, /* read-only */
181 RADEON_PRIO_SHADER_RESOURCE_RW
, /* buffers, textures, streamout, GS rings, RATs; read/write */
182 RADEON_PRIO_COLOR_BUFFER
,
183 RADEON_PRIO_DEPTH_BUFFER
,
184 RADEON_PRIO_SHADER_TEXTURE_MSAA
,
185 RADEON_PRIO_COLOR_BUFFER_MSAA
,
186 RADEON_PRIO_DEPTH_BUFFER_MSAA
,
187 RADEON_PRIO_COLOR_META
,
188 RADEON_PRIO_DEPTH_META
,
189 RADEON_PRIO_MAX
/* must be <= 15 */
192 struct winsys_handle
;
193 struct radeon_winsys_cs_handle
;
195 struct radeon_winsys_cs
{
196 unsigned cdw
; /* Number of used dwords. */
197 unsigned max_dw
; /* Maximum number of dwords. */
198 uint32_t *buf
; /* The command buffer. */
199 enum ring_type ring_type
;
204 enum radeon_family family
;
205 enum chip_class chip_class
;
209 uint32_t max_compute_units
;
211 uint32_t max_sh_per_se
;
213 uint32_t drm_major
; /* version */
215 uint32_t drm_patchlevel
;
218 uint32_t vce_fw_version
;
221 uint32_t r300_num_gb_pipes
;
222 uint32_t r300_num_z_pipes
;
224 uint32_t r600_num_backends
;
225 uint32_t r600_clock_crystal_freq
;
226 uint32_t r600_tiling_config
;
227 uint32_t r600_num_tile_pipes
;
228 uint32_t r600_max_pipes
;
229 boolean r600_virtual_address
;
230 boolean r600_has_dma
;
232 uint32_t r600_backend_map
;
233 boolean r600_backend_map_valid
;
235 boolean si_tile_mode_array_valid
;
236 uint32_t si_tile_mode_array
[32];
237 uint32_t si_backend_enabled_mask
;
239 boolean cik_macrotile_mode_array_valid
;
240 uint32_t cik_macrotile_mode_array
[16];
243 enum radeon_feature_id
{
244 RADEON_FID_R300_HYPERZ_ACCESS
, /* ZMask + HiZ */
245 RADEON_FID_R300_CMASK_ACCESS
,
248 #define RADEON_SURF_MAX_LEVEL 32
250 #define RADEON_SURF_TYPE_MASK 0xFF
251 #define RADEON_SURF_TYPE_SHIFT 0
252 #define RADEON_SURF_TYPE_1D 0
253 #define RADEON_SURF_TYPE_2D 1
254 #define RADEON_SURF_TYPE_3D 2
255 #define RADEON_SURF_TYPE_CUBEMAP 3
256 #define RADEON_SURF_TYPE_1D_ARRAY 4
257 #define RADEON_SURF_TYPE_2D_ARRAY 5
258 #define RADEON_SURF_MODE_MASK 0xFF
259 #define RADEON_SURF_MODE_SHIFT 8
260 #define RADEON_SURF_MODE_LINEAR 0
261 #define RADEON_SURF_MODE_LINEAR_ALIGNED 1
262 #define RADEON_SURF_MODE_1D 2
263 #define RADEON_SURF_MODE_2D 3
264 #define RADEON_SURF_SCANOUT (1 << 16)
265 #define RADEON_SURF_ZBUFFER (1 << 17)
266 #define RADEON_SURF_SBUFFER (1 << 18)
267 #define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
268 #define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19)
269 #define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20)
270 #define RADEON_SURF_FMASK (1 << 21)
272 #define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
273 #define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
274 #define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
276 struct radeon_surf_level
{
285 uint32_t pitch_bytes
;
290 /* These are inputs to the calculator. */
303 /* These are return values. Some of them can be set by the caller, but
304 * they will be treated as hints (e.g. bankw, bankh) and might be
305 * changed by the calculator.
308 uint64_t bo_alignment
;
309 /* This applies to EG and later. */
314 uint32_t stencil_tile_split
;
315 uint64_t stencil_offset
;
316 struct radeon_surf_level level
[RADEON_SURF_MAX_LEVEL
];
317 struct radeon_surf_level stencil_level
[RADEON_SURF_MAX_LEVEL
];
318 uint32_t tiling_index
[RADEON_SURF_MAX_LEVEL
];
319 uint32_t stencil_tiling_index
[RADEON_SURF_MAX_LEVEL
];
322 struct radeon_winsys
{
324 * The screen object this winsys was created for
326 struct pipe_screen
*screen
;
329 * Decrement the winsys reference count.
331 * \param ws The winsys this function is called for.
332 * \return True if the winsys and screen should be destroyed.
334 bool (*unref
)(struct radeon_winsys
*ws
);
337 * Destroy this winsys.
339 * \param ws The winsys this function is called from.
341 void (*destroy
)(struct radeon_winsys
*ws
);
344 * Query an info structure from winsys.
346 * \param ws The winsys this function is called from.
347 * \param info Return structure
349 void (*query_info
)(struct radeon_winsys
*ws
,
350 struct radeon_info
*info
);
352 /**************************************************************************
353 * Buffer management. Buffer attributes are mostly fixed over its lifetime.
355 * Remember that gallium gets to choose the interface it needs, and the
356 * window systems must then implement that interface (rather than the
357 * other way around...).
358 *************************************************************************/
361 * Create a buffer object.
363 * \param ws The winsys this function is called from.
364 * \param size The size to allocate.
365 * \param alignment An alignment of the buffer in memory.
366 * \param use_reusable_pool Whether the cache buffer manager should be used.
367 * \param domain A bitmask of the RADEON_DOMAIN_* flags.
368 * \return The created buffer object.
370 struct pb_buffer
*(*buffer_create
)(struct radeon_winsys
*ws
,
373 boolean use_reusable_pool
,
374 enum radeon_bo_domain domain
,
375 enum radeon_bo_flag flags
);
377 struct radeon_winsys_cs_handle
*(*buffer_get_cs_handle
)(
378 struct pb_buffer
*buf
);
381 * Map the entire data store of a buffer object into the client's address
384 * \param buf A winsys buffer object to map.
385 * \param cs A command stream to flush if the buffer is referenced by it.
386 * \param usage A bitmask of the PIPE_TRANSFER_* flags.
387 * \return The pointer at the beginning of the buffer.
389 void *(*buffer_map
)(struct radeon_winsys_cs_handle
*buf
,
390 struct radeon_winsys_cs
*cs
,
391 enum pipe_transfer_usage usage
);
394 * Unmap a buffer object from the client's address space.
396 * \param buf A winsys buffer object to unmap.
398 void (*buffer_unmap
)(struct radeon_winsys_cs_handle
*buf
);
401 * Return TRUE if a buffer object is being used by the GPU.
403 * \param buf A winsys buffer object.
404 * \param usage Only check whether the buffer is busy for the given usage.
406 boolean (*buffer_is_busy
)(struct pb_buffer
*buf
,
407 enum radeon_bo_usage usage
);
410 * Wait for a buffer object until it is not used by a GPU. This is
411 * equivalent to a fence placed after the last command using the buffer,
412 * and synchronizing to the fence.
414 * \param buf A winsys buffer object to wait for.
415 * \param usage Only wait until the buffer is idle for the given usage,
416 * but may still be busy for some other usage.
418 void (*buffer_wait
)(struct pb_buffer
*buf
, enum radeon_bo_usage usage
);
421 * Return tiling flags describing a memory layout of a buffer object.
423 * \param buf A winsys buffer object to get the flags from.
424 * \param macrotile A pointer to the return value of the microtile flag.
425 * \param microtile A pointer to the return value of the macrotile flag.
427 * \note microtile and macrotile are not bitmasks!
429 void (*buffer_get_tiling
)(struct pb_buffer
*buf
,
430 enum radeon_bo_layout
*microtile
,
431 enum radeon_bo_layout
*macrotile
,
432 unsigned *bankw
, unsigned *bankh
,
433 unsigned *tile_split
,
434 unsigned *stencil_tile_split
,
439 * Set tiling flags describing a memory layout of a buffer object.
441 * \param buf A winsys buffer object to set the flags for.
442 * \param cs A command stream to flush if the buffer is referenced by it.
443 * \param macrotile A macrotile flag.
444 * \param microtile A microtile flag.
445 * \param stride A stride of the buffer in bytes, for texturing.
447 * \note microtile and macrotile are not bitmasks!
449 void (*buffer_set_tiling
)(struct pb_buffer
*buf
,
450 struct radeon_winsys_cs
*rcs
,
451 enum radeon_bo_layout microtile
,
452 enum radeon_bo_layout macrotile
,
453 unsigned bankw
, unsigned bankh
,
455 unsigned stencil_tile_split
,
461 * Get a winsys buffer from a winsys handle. The internal structure
462 * of the handle is platform-specific and only a winsys should access it.
464 * \param ws The winsys this function is called from.
465 * \param whandle A winsys handle pointer as was received from a state
467 * \param stride The returned buffer stride in bytes.
469 struct pb_buffer
*(*buffer_from_handle
)(struct radeon_winsys
*ws
,
470 struct winsys_handle
*whandle
,
474 * Get a winsys buffer from a user pointer. The resulting buffer can't
475 * be exported. Both pointer and size must be page aligned.
477 * \param ws The winsys this function is called from.
478 * \param pointer User pointer to turn into a buffer object.
479 * \param Size Size in bytes for the new buffer.
481 struct pb_buffer
*(*buffer_from_ptr
)(struct radeon_winsys
*ws
,
482 void *pointer
, unsigned size
);
485 * Get a winsys handle from a winsys buffer. The internal structure
486 * of the handle is platform-specific and only a winsys should access it.
488 * \param buf A winsys buffer object to get the handle from.
489 * \param whandle A winsys handle pointer.
490 * \param stride A stride of the buffer in bytes, for texturing.
491 * \return TRUE on success.
493 boolean (*buffer_get_handle
)(struct pb_buffer
*buf
,
495 struct winsys_handle
*whandle
);
498 * Return the virtual address of a buffer.
500 * \param buf A winsys buffer object
501 * \return virtual address
503 uint64_t (*buffer_get_virtual_address
)(struct radeon_winsys_cs_handle
*buf
);
506 * Query the initial placement of the buffer from the kernel driver.
508 enum radeon_bo_domain (*buffer_get_initial_domain
)(struct radeon_winsys_cs_handle
*buf
);
510 /**************************************************************************
511 * Command submission.
513 * Each pipe context should create its own command stream and submit
514 * commands independently of other contexts.
515 *************************************************************************/
518 * Create a command stream.
520 * \param ws The winsys this function is called from.
521 * \param ring_type The ring type (GFX, DMA, UVD)
522 * \param flush Flush callback function associated with the command stream.
523 * \param user User pointer that will be passed to the flush callback.
524 * \param trace_buf Trace buffer when tracing is enabled
526 struct radeon_winsys_cs
*(*cs_create
)(struct radeon_winsys
*ws
,
527 enum ring_type ring_type
,
528 void (*flush
)(void *ctx
, unsigned flags
,
529 struct pipe_fence_handle
**fence
),
531 struct radeon_winsys_cs_handle
*trace_buf
);
534 * Destroy a command stream.
536 * \param cs A command stream to destroy.
538 void (*cs_destroy
)(struct radeon_winsys_cs
*cs
);
541 * Add a new buffer relocation. Every relocation must first be added
542 * before it can be written.
544 * \param cs A command stream to add buffer for validation against.
545 * \param buf A winsys buffer to validate.
546 * \param usage Whether the buffer is used for read and/or write.
547 * \param domain Bitmask of the RADEON_DOMAIN_* flags.
548 * \param priority A higher number means a greater chance of being
549 * placed in the requested domain. 15 is the maximum.
550 * \return Relocation index.
552 unsigned (*cs_add_reloc
)(struct radeon_winsys_cs
*cs
,
553 struct radeon_winsys_cs_handle
*buf
,
554 enum radeon_bo_usage usage
,
555 enum radeon_bo_domain domain
,
556 enum radeon_bo_priority priority
);
559 * Return the index of an already-added buffer.
561 * \param cs Command stream
563 * \return The buffer index, or -1 if the buffer has not been added.
565 int (*cs_get_reloc
)(struct radeon_winsys_cs
*cs
,
566 struct radeon_winsys_cs_handle
*buf
);
569 * Return TRUE if there is enough memory in VRAM and GTT for the relocs
570 * added so far. If the validation fails, all the relocations which have
571 * been added since the last call of cs_validate will be removed and
572 * the CS will be flushed (provided there are still any relocations).
574 * \param cs A command stream to validate.
576 boolean (*cs_validate
)(struct radeon_winsys_cs
*cs
);
579 * Return TRUE if there is enough memory in VRAM and GTT for the relocs
582 * \param cs A command stream to validate.
583 * \param vram VRAM memory size pending to be use
584 * \param gtt GTT memory size pending to be use
586 boolean (*cs_memory_below_limit
)(struct radeon_winsys_cs
*cs
, uint64_t vram
, uint64_t gtt
);
589 * Flush a command stream.
591 * \param cs A command stream to flush.
592 * \param flags, RADEON_FLUSH_ASYNC or 0.
593 * \param fence Pointer to a fence. If non-NULL, a fence is inserted
594 * after the CS and is returned through this parameter.
595 * \param cs_trace_id A unique identifier of the cs, used for tracing.
597 void (*cs_flush
)(struct radeon_winsys_cs
*cs
,
599 struct pipe_fence_handle
**fence
,
600 uint32_t cs_trace_id
);
603 * Return TRUE if a buffer is referenced by a command stream.
605 * \param cs A command stream.
606 * \param buf A winsys buffer.
608 boolean (*cs_is_buffer_referenced
)(struct radeon_winsys_cs
*cs
,
609 struct radeon_winsys_cs_handle
*buf
,
610 enum radeon_bo_usage usage
);
613 * Request access to a feature for a command stream.
615 * \param cs A command stream.
616 * \param fid Feature ID, one of RADEON_FID_*
617 * \param enable Whether to enable or disable the feature.
619 boolean (*cs_request_feature
)(struct radeon_winsys_cs
*cs
,
620 enum radeon_feature_id fid
,
623 * Make sure all asynchronous flush of the cs have completed
625 * \param cs A command stream.
627 void (*cs_sync_flush
)(struct radeon_winsys_cs
*cs
);
630 * Wait for the fence and return true if the fence has been signalled.
631 * The timeout of 0 will only return the status.
632 * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
635 bool (*fence_wait
)(struct radeon_winsys
*ws
,
636 struct pipe_fence_handle
*fence
,
640 * Reference counting for fences.
642 void (*fence_reference
)(struct pipe_fence_handle
**dst
,
643 struct pipe_fence_handle
*src
);
648 * \param ws The winsys this function is called from.
649 * \param surf Surface structure ptr
651 int (*surface_init
)(struct radeon_winsys
*ws
,
652 struct radeon_surf
*surf
);
655 * Find best values for a surface
657 * \param ws The winsys this function is called from.
658 * \param surf Surface structure ptr
660 int (*surface_best
)(struct radeon_winsys
*ws
,
661 struct radeon_surf
*surf
);
663 uint64_t (*query_value
)(struct radeon_winsys
*ws
,
664 enum radeon_value_id value
);
666 void (*read_registers
)(struct radeon_winsys
*ws
, unsigned reg_offset
,
667 unsigned num_registers
, uint32_t *out
);
671 static inline void radeon_emit(struct radeon_winsys_cs
*cs
, uint32_t value
)
673 cs
->buf
[cs
->cdw
++] = value
;
676 static inline void radeon_emit_array(struct radeon_winsys_cs
*cs
,
677 const uint32_t *values
, unsigned count
)
679 memcpy(cs
->buf
+cs
->cdw
, values
, count
* 4);