2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 #ifndef RADEON_WINSYS_H
25 #define RADEON_WINSYS_H
27 /* The public winsys interface header for the radeon driver. */
29 /* R300 features in DRM.
33 * - GB_Z_PEQ_CONFIG on rv350->r4xx
34 * - R500 FG_ALPHA_VALUE
37 * - R500 US_FORMAT regs
38 * - R500 ARGB2101010 colorbuffer
43 #include "pipebuffer/pb_buffer.h"
45 #define RADEON_FLUSH_ASYNC (1 << 0)
46 #define RADEON_FLUSH_KEEP_TILING_FLAGS (1 << 1) /* needs DRM 2.12.0 */
47 #define RADEON_FLUSH_END_OF_FRAME (1 << 2)
50 enum radeon_bo_layout
{
51 RADEON_LAYOUT_LINEAR
= 0,
53 RADEON_LAYOUT_SQUARETILED
,
58 enum radeon_bo_domain
{ /* bitfield */
59 RADEON_DOMAIN_GTT
= 2,
60 RADEON_DOMAIN_VRAM
= 4,
61 RADEON_DOMAIN_VRAM_GTT
= RADEON_DOMAIN_VRAM
| RADEON_DOMAIN_GTT
64 enum radeon_bo_flag
{ /* bitfield */
65 RADEON_FLAG_GTT_WC
= (1 << 0),
66 RADEON_FLAG_CPU_ACCESS
= (1 << 1),
67 RADEON_FLAG_NO_CPU_ACCESS
= (1 << 2),
70 enum radeon_bo_usage
{ /* bitfield */
71 RADEON_USAGE_READ
= 2,
72 RADEON_USAGE_WRITE
= 4,
73 RADEON_USAGE_READWRITE
= RADEON_USAGE_READ
| RADEON_USAGE_WRITE
78 CHIP_R300
, /* R3xx-based cores. */
86 CHIP_R420
, /* R4xx-based cores. */
95 CHIP_RV515
, /* R5xx-based cores. */
167 enum radeon_value_id
{
168 RADEON_REQUESTED_VRAM_MEMORY
,
169 RADEON_REQUESTED_GTT_MEMORY
,
170 RADEON_BUFFER_WAIT_TIME_NS
,
172 RADEON_NUM_CS_FLUSHES
,
173 RADEON_NUM_BYTES_MOVED
,
176 RADEON_GPU_TEMPERATURE
, /* DRM 2.42.0 */
179 RADEON_GPU_RESET_COUNTER
, /* DRM 2.43.0 */
182 /* Each group of four has the same priority. */
183 enum radeon_bo_priority
{
184 RADEON_PRIO_FENCE
= 0,
186 RADEON_PRIO_SO_FILLED_SIZE
,
189 RADEON_PRIO_IB1
= 4, /* main IB submitted to the kernel */
190 RADEON_PRIO_IB2
, /* IB executed with INDIRECT_BUFFER */
191 RADEON_PRIO_DRAW_INDIRECT
,
192 RADEON_PRIO_INDEX_BUFFER
,
194 RADEON_PRIO_CP_DMA
= 8,
196 RADEON_PRIO_VCE
= 12,
198 RADEON_PRIO_SDMA_BUFFER
,
199 RADEON_PRIO_SDMA_TEXTURE
,
201 RADEON_PRIO_USER_SHADER
= 16,
202 RADEON_PRIO_INTERNAL_SHADER
, /* fetch shader, etc. */
206 RADEON_PRIO_CONST_BUFFER
= 24,
207 RADEON_PRIO_DESCRIPTORS
,
208 RADEON_PRIO_BORDER_COLORS
,
210 RADEON_PRIO_SAMPLER_BUFFER
= 28,
211 RADEON_PRIO_VERTEX_BUFFER
,
213 RADEON_PRIO_SHADER_RW_BUFFER
= 32,
214 RADEON_PRIO_RINGS_STREAMOUT
,
215 RADEON_PRIO_SCRATCH_BUFFER
,
216 RADEON_PRIO_COMPUTE_GLOBAL
,
218 RADEON_PRIO_SAMPLER_TEXTURE
= 36,
219 RADEON_PRIO_SHADER_RW_IMAGE
,
221 RADEON_PRIO_SAMPLER_TEXTURE_MSAA
= 40,
223 RADEON_PRIO_COLOR_BUFFER
= 44,
225 RADEON_PRIO_DEPTH_BUFFER
= 48,
227 RADEON_PRIO_COLOR_BUFFER_MSAA
= 52,
229 RADEON_PRIO_DEPTH_BUFFER_MSAA
= 56,
231 RADEON_PRIO_CMASK
= 60,
234 /* 63 is the maximum value */
237 struct winsys_handle
;
238 struct radeon_winsys_ctx
;
240 struct radeon_winsys_cs
{
241 unsigned cdw
; /* Number of used dwords. */
242 unsigned max_dw
; /* Maximum number of dwords. */
243 uint32_t *buf
; /* The command buffer. */
244 enum ring_type ring_type
;
250 enum radeon_family family
;
251 enum chip_class chip_class
;
254 boolean has_virtual_memory
;
255 bool gfx_ib_pad_with_type2
;
258 uint32_t vce_fw_version
;
259 uint32_t vce_harvest_config
;
260 uint32_t clock_crystal_freq
;
263 uint32_t drm_major
; /* version */
265 uint32_t drm_patchlevel
;
269 uint32_t r600_max_quad_pipes
; /* wave size / 16 */
270 uint32_t max_shader_clock
;
271 uint32_t num_good_compute_units
;
272 uint32_t max_se
; /* shader engines */
273 uint32_t max_sh_per_se
; /* shader arrays per shader engine */
275 /* Render backends (color + depth blocks). */
276 uint32_t r300_num_gb_pipes
;
277 uint32_t r300_num_z_pipes
;
278 uint32_t r600_gb_backend_map
; /* R600 harvest config */
279 boolean r600_gb_backend_map_valid
;
280 uint32_t r600_num_banks
;
281 uint32_t r600_tiling_config
;
282 uint32_t num_render_backends
;
283 uint32_t num_tile_pipes
; /* pipe count from PIPE_CONFIG */
284 uint32_t pipe_interleave_bytes
;
285 uint32_t enabled_rb_mask
; /* GCN harvest config */
288 boolean si_tile_mode_array_valid
;
289 uint32_t si_tile_mode_array
[32];
290 boolean cik_macrotile_mode_array_valid
;
291 uint32_t cik_macrotile_mode_array
[16];
294 enum radeon_feature_id
{
295 RADEON_FID_R300_HYPERZ_ACCESS
, /* ZMask + HiZ */
296 RADEON_FID_R300_CMASK_ACCESS
,
299 #define RADEON_SURF_MAX_LEVEL 32
301 #define RADEON_SURF_TYPE_MASK 0xFF
302 #define RADEON_SURF_TYPE_SHIFT 0
303 #define RADEON_SURF_TYPE_1D 0
304 #define RADEON_SURF_TYPE_2D 1
305 #define RADEON_SURF_TYPE_3D 2
306 #define RADEON_SURF_TYPE_CUBEMAP 3
307 #define RADEON_SURF_TYPE_1D_ARRAY 4
308 #define RADEON_SURF_TYPE_2D_ARRAY 5
309 #define RADEON_SURF_MODE_MASK 0xFF
310 #define RADEON_SURF_MODE_SHIFT 8
311 #define RADEON_SURF_MODE_LINEAR 0
312 #define RADEON_SURF_MODE_LINEAR_ALIGNED 1
313 #define RADEON_SURF_MODE_1D 2
314 #define RADEON_SURF_MODE_2D 3
315 #define RADEON_SURF_SCANOUT (1 << 16)
316 #define RADEON_SURF_ZBUFFER (1 << 17)
317 #define RADEON_SURF_SBUFFER (1 << 18)
318 #define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
319 #define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19)
320 #define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20)
321 #define RADEON_SURF_FMASK (1 << 21)
323 #define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
324 #define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
325 #define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
327 struct radeon_surf_level
{
336 uint32_t pitch_bytes
;
342 /* These are inputs to the calculator. */
355 /* These are return values. Some of them can be set by the caller, but
356 * they will be treated as hints (e.g. bankw, bankh) and might be
357 * changed by the calculator.
360 uint64_t bo_alignment
;
361 /* This applies to EG and later. */
366 uint32_t stencil_tile_split
;
367 uint64_t stencil_offset
;
368 struct radeon_surf_level level
[RADEON_SURF_MAX_LEVEL
];
369 struct radeon_surf_level stencil_level
[RADEON_SURF_MAX_LEVEL
];
370 uint32_t tiling_index
[RADEON_SURF_MAX_LEVEL
];
371 uint32_t stencil_tiling_index
[RADEON_SURF_MAX_LEVEL
];
372 uint32_t pipe_config
;
376 uint64_t dcc_alignment
;
379 struct radeon_bo_list_item
{
380 struct pb_buffer
*buf
;
382 uint64_t priority_usage
; /* mask of (1 << RADEON_PRIO_*) */
385 struct radeon_winsys
{
387 * The screen object this winsys was created for
389 struct pipe_screen
*screen
;
392 * Decrement the winsys reference count.
394 * \param ws The winsys this function is called for.
395 * \return True if the winsys and screen should be destroyed.
397 bool (*unref
)(struct radeon_winsys
*ws
);
400 * Destroy this winsys.
402 * \param ws The winsys this function is called from.
404 void (*destroy
)(struct radeon_winsys
*ws
);
407 * Query an info structure from winsys.
409 * \param ws The winsys this function is called from.
410 * \param info Return structure
412 void (*query_info
)(struct radeon_winsys
*ws
,
413 struct radeon_info
*info
);
415 /**************************************************************************
416 * Buffer management. Buffer attributes are mostly fixed over its lifetime.
418 * Remember that gallium gets to choose the interface it needs, and the
419 * window systems must then implement that interface (rather than the
420 * other way around...).
421 *************************************************************************/
424 * Create a buffer object.
426 * \param ws The winsys this function is called from.
427 * \param size The size to allocate.
428 * \param alignment An alignment of the buffer in memory.
429 * \param use_reusable_pool Whether the cache buffer manager should be used.
430 * \param domain A bitmask of the RADEON_DOMAIN_* flags.
431 * \return The created buffer object.
433 struct pb_buffer
*(*buffer_create
)(struct radeon_winsys
*ws
,
436 boolean use_reusable_pool
,
437 enum radeon_bo_domain domain
,
438 enum radeon_bo_flag flags
);
441 * Map the entire data store of a buffer object into the client's address
444 * \param buf A winsys buffer object to map.
445 * \param cs A command stream to flush if the buffer is referenced by it.
446 * \param usage A bitmask of the PIPE_TRANSFER_* flags.
447 * \return The pointer at the beginning of the buffer.
449 void *(*buffer_map
)(struct pb_buffer
*buf
,
450 struct radeon_winsys_cs
*cs
,
451 enum pipe_transfer_usage usage
);
454 * Unmap a buffer object from the client's address space.
456 * \param buf A winsys buffer object to unmap.
458 void (*buffer_unmap
)(struct pb_buffer
*buf
);
461 * Wait for the buffer and return true if the buffer is not used
464 * The timeout of 0 will only return the status.
465 * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
468 bool (*buffer_wait
)(struct pb_buffer
*buf
, uint64_t timeout
,
469 enum radeon_bo_usage usage
);
472 * Return tiling flags describing a memory layout of a buffer object.
474 * \param buf A winsys buffer object to get the flags from.
475 * \param macrotile A pointer to the return value of the microtile flag.
476 * \param microtile A pointer to the return value of the macrotile flag.
478 * \note microtile and macrotile are not bitmasks!
480 void (*buffer_get_tiling
)(struct pb_buffer
*buf
,
481 enum radeon_bo_layout
*microtile
,
482 enum radeon_bo_layout
*macrotile
,
483 unsigned *bankw
, unsigned *bankh
,
484 unsigned *tile_split
,
485 unsigned *stencil_tile_split
,
490 * Set tiling flags describing a memory layout of a buffer object.
492 * \param buf A winsys buffer object to set the flags for.
493 * \param cs A command stream to flush if the buffer is referenced by it.
494 * \param macrotile A macrotile flag.
495 * \param microtile A microtile flag.
496 * \param stride A stride of the buffer in bytes, for texturing.
498 * \note microtile and macrotile are not bitmasks!
500 void (*buffer_set_tiling
)(struct pb_buffer
*buf
,
501 struct radeon_winsys_cs
*rcs
,
502 enum radeon_bo_layout microtile
,
503 enum radeon_bo_layout macrotile
,
504 unsigned pipe_config
,
505 unsigned bankw
, unsigned bankh
,
507 unsigned stencil_tile_split
,
508 unsigned mtilea
, unsigned num_banks
,
513 * Get a winsys buffer from a winsys handle. The internal structure
514 * of the handle is platform-specific and only a winsys should access it.
516 * \param ws The winsys this function is called from.
517 * \param whandle A winsys handle pointer as was received from a state
519 * \param stride The returned buffer stride in bytes.
521 struct pb_buffer
*(*buffer_from_handle
)(struct radeon_winsys
*ws
,
522 struct winsys_handle
*whandle
,
526 * Get a winsys buffer from a user pointer. The resulting buffer can't
527 * be exported. Both pointer and size must be page aligned.
529 * \param ws The winsys this function is called from.
530 * \param pointer User pointer to turn into a buffer object.
531 * \param Size Size in bytes for the new buffer.
533 struct pb_buffer
*(*buffer_from_ptr
)(struct radeon_winsys
*ws
,
534 void *pointer
, unsigned size
);
537 * Whether the buffer was created from a user pointer.
539 * \param buf A winsys buffer object
540 * \return whether \p buf was created via buffer_from_ptr
542 bool (*buffer_is_user_ptr
)(struct pb_buffer
*buf
);
545 * Get a winsys handle from a winsys buffer. The internal structure
546 * of the handle is platform-specific and only a winsys should access it.
548 * \param buf A winsys buffer object to get the handle from.
549 * \param whandle A winsys handle pointer.
550 * \param stride A stride of the buffer in bytes, for texturing.
551 * \return TRUE on success.
553 boolean (*buffer_get_handle
)(struct pb_buffer
*buf
,
555 struct winsys_handle
*whandle
);
558 * Return the virtual address of a buffer.
560 * \param buf A winsys buffer object
561 * \return virtual address
563 uint64_t (*buffer_get_virtual_address
)(struct pb_buffer
*buf
);
566 * Query the initial placement of the buffer from the kernel driver.
568 enum radeon_bo_domain (*buffer_get_initial_domain
)(struct pb_buffer
*buf
);
570 /**************************************************************************
571 * Command submission.
573 * Each pipe context should create its own command stream and submit
574 * commands independently of other contexts.
575 *************************************************************************/
578 * Create a command submission context.
579 * Various command streams can be submitted to the same context.
581 struct radeon_winsys_ctx
*(*ctx_create
)(struct radeon_winsys
*ws
);
586 void (*ctx_destroy
)(struct radeon_winsys_ctx
*ctx
);
589 * Query a GPU reset status.
591 enum pipe_reset_status (*ctx_query_reset_status
)(struct radeon_winsys_ctx
*ctx
);
594 * Create a command stream.
596 * \param ctx The submission context
597 * \param ring_type The ring type (GFX, DMA, UVD)
598 * \param flush Flush callback function associated with the command stream.
599 * \param user User pointer that will be passed to the flush callback.
600 * \param trace_buf Trace buffer when tracing is enabled
602 struct radeon_winsys_cs
*(*cs_create
)(struct radeon_winsys_ctx
*ctx
,
603 enum ring_type ring_type
,
604 void (*flush
)(void *ctx
, unsigned flags
,
605 struct pipe_fence_handle
**fence
),
607 struct pb_buffer
*trace_buf
);
610 * Destroy a command stream.
612 * \param cs A command stream to destroy.
614 void (*cs_destroy
)(struct radeon_winsys_cs
*cs
);
617 * Add a buffer. Each buffer used by a CS must be added using this function.
619 * \param cs Command stream
621 * \param usage Whether the buffer is used for read and/or write.
622 * \param domain Bitmask of the RADEON_DOMAIN_* flags.
623 * \param priority A higher number means a greater chance of being
624 * placed in the requested domain. 15 is the maximum.
625 * \return Buffer index.
627 unsigned (*cs_add_buffer
)(struct radeon_winsys_cs
*cs
,
628 struct pb_buffer
*buf
,
629 enum radeon_bo_usage usage
,
630 enum radeon_bo_domain domain
,
631 enum radeon_bo_priority priority
);
634 * Return the index of an already-added buffer.
636 * \param cs Command stream
638 * \return The buffer index, or -1 if the buffer has not been added.
640 int (*cs_lookup_buffer
)(struct radeon_winsys_cs
*cs
,
641 struct pb_buffer
*buf
);
644 * Return TRUE if there is enough memory in VRAM and GTT for the buffers
645 * added so far. If the validation fails, all buffers which have
646 * been added since the last call of cs_validate will be removed and
647 * the CS will be flushed (provided there are still any buffers).
649 * \param cs A command stream to validate.
651 boolean (*cs_validate
)(struct radeon_winsys_cs
*cs
);
654 * Return TRUE if there is enough memory in VRAM and GTT for the buffers
657 * \param cs A command stream to validate.
658 * \param vram VRAM memory size pending to be use
659 * \param gtt GTT memory size pending to be use
661 boolean (*cs_memory_below_limit
)(struct radeon_winsys_cs
*cs
, uint64_t vram
, uint64_t gtt
);
664 * Return the buffer list.
666 * \param cs Command stream
667 * \param list Returned buffer list. Set to NULL to query the count only.
668 * \return The buffer count.
670 unsigned (*cs_get_buffer_list
)(struct radeon_winsys_cs
*cs
,
671 struct radeon_bo_list_item
*list
);
674 * Flush a command stream.
676 * \param cs A command stream to flush.
677 * \param flags, RADEON_FLUSH_ASYNC or 0.
678 * \param fence Pointer to a fence. If non-NULL, a fence is inserted
679 * after the CS and is returned through this parameter.
680 * \param cs_trace_id A unique identifier of the cs, used for tracing.
682 void (*cs_flush
)(struct radeon_winsys_cs
*cs
,
684 struct pipe_fence_handle
**fence
,
685 uint32_t cs_trace_id
);
688 * Return TRUE if a buffer is referenced by a command stream.
690 * \param cs A command stream.
691 * \param buf A winsys buffer.
693 boolean (*cs_is_buffer_referenced
)(struct radeon_winsys_cs
*cs
,
694 struct pb_buffer
*buf
,
695 enum radeon_bo_usage usage
);
698 * Request access to a feature for a command stream.
700 * \param cs A command stream.
701 * \param fid Feature ID, one of RADEON_FID_*
702 * \param enable Whether to enable or disable the feature.
704 boolean (*cs_request_feature
)(struct radeon_winsys_cs
*cs
,
705 enum radeon_feature_id fid
,
708 * Make sure all asynchronous flush of the cs have completed
710 * \param cs A command stream.
712 void (*cs_sync_flush
)(struct radeon_winsys_cs
*cs
);
715 * Wait for the fence and return true if the fence has been signalled.
716 * The timeout of 0 will only return the status.
717 * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
720 bool (*fence_wait
)(struct radeon_winsys
*ws
,
721 struct pipe_fence_handle
*fence
,
725 * Reference counting for fences.
727 void (*fence_reference
)(struct pipe_fence_handle
**dst
,
728 struct pipe_fence_handle
*src
);
733 * \param ws The winsys this function is called from.
734 * \param surf Surface structure ptr
736 int (*surface_init
)(struct radeon_winsys
*ws
,
737 struct radeon_surf
*surf
);
740 * Find best values for a surface
742 * \param ws The winsys this function is called from.
743 * \param surf Surface structure ptr
745 int (*surface_best
)(struct radeon_winsys
*ws
,
746 struct radeon_surf
*surf
);
748 uint64_t (*query_value
)(struct radeon_winsys
*ws
,
749 enum radeon_value_id value
);
751 bool (*read_registers
)(struct radeon_winsys
*ws
, unsigned reg_offset
,
752 unsigned num_registers
, uint32_t *out
);
756 static inline void radeon_emit(struct radeon_winsys_cs
*cs
, uint32_t value
)
758 cs
->buf
[cs
->cdw
++] = value
;
761 static inline void radeon_emit_array(struct radeon_winsys_cs
*cs
,
762 const uint32_t *values
, unsigned count
)
764 memcpy(cs
->buf
+cs
->cdw
, values
, count
* 4);