2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 #ifndef RADEON_WINSYS_H
25 #define RADEON_WINSYS_H
27 /* The public winsys interface header for the radeon driver. */
29 /* R300 features in DRM.
33 * - GB_Z_PEQ_CONFIG on rv350->r4xx
34 * - R500 FG_ALPHA_VALUE
37 * - R500 US_FORMAT regs
38 * - R500 ARGB2101010 colorbuffer
43 #include "pipebuffer/pb_buffer.h"
45 #define RADEON_FLUSH_ASYNC (1 << 0)
46 #define RADEON_FLUSH_KEEP_TILING_FLAGS (1 << 1) /* needs DRM 2.12.0 */
47 #define RADEON_FLUSH_END_OF_FRAME (1 << 2)
50 enum radeon_bo_layout
{
51 RADEON_LAYOUT_LINEAR
= 0,
53 RADEON_LAYOUT_SQUARETILED
,
58 enum radeon_bo_domain
{ /* bitfield */
59 RADEON_DOMAIN_GTT
= 2,
60 RADEON_DOMAIN_VRAM
= 4,
61 RADEON_DOMAIN_VRAM_GTT
= RADEON_DOMAIN_VRAM
| RADEON_DOMAIN_GTT
64 enum radeon_bo_flag
{ /* bitfield */
65 RADEON_FLAG_GTT_WC
= (1 << 0),
66 RADEON_FLAG_CPU_ACCESS
= (1 << 1),
67 RADEON_FLAG_NO_CPU_ACCESS
= (1 << 2),
70 enum radeon_bo_usage
{ /* bitfield */
71 RADEON_USAGE_READ
= 2,
72 RADEON_USAGE_WRITE
= 4,
73 RADEON_USAGE_READWRITE
= RADEON_USAGE_READ
| RADEON_USAGE_WRITE
78 CHIP_R300
, /* R3xx-based cores. */
86 CHIP_R420
, /* R4xx-based cores. */
95 CHIP_RV515
, /* R5xx-based cores. */
166 enum radeon_value_id
{
167 RADEON_REQUESTED_VRAM_MEMORY
,
168 RADEON_REQUESTED_GTT_MEMORY
,
169 RADEON_BUFFER_WAIT_TIME_NS
,
171 RADEON_NUM_CS_FLUSHES
,
172 RADEON_NUM_BYTES_MOVED
,
175 RADEON_GPU_TEMPERATURE
, /* DRM 2.42.0 */
178 RADEON_GPU_RESET_COUNTER
, /* DRM 2.43.0 */
181 enum radeon_bo_priority
{
183 RADEON_PRIO_SHADER_DATA
, /* shader code, resource descriptors */
184 RADEON_PRIO_SHADER_BUFFER_RO
, /* read-only */
185 RADEON_PRIO_SHADER_TEXTURE_RO
, /* read-only */
186 RADEON_PRIO_SHADER_RESOURCE_RW
, /* buffers, textures, streamout, GS rings, RATs; read/write */
187 RADEON_PRIO_COLOR_BUFFER
,
188 RADEON_PRIO_DEPTH_BUFFER
,
189 RADEON_PRIO_SHADER_TEXTURE_MSAA
,
190 RADEON_PRIO_COLOR_BUFFER_MSAA
,
191 RADEON_PRIO_DEPTH_BUFFER_MSAA
,
192 RADEON_PRIO_COLOR_META
,
193 RADEON_PRIO_DEPTH_META
,
194 RADEON_PRIO_MAX
/* must be <= 15 */
197 struct winsys_handle
;
198 struct radeon_winsys_cs_handle
;
199 struct radeon_winsys_ctx
;
201 struct radeon_winsys_cs
{
202 unsigned cdw
; /* Number of used dwords. */
203 unsigned max_dw
; /* Maximum number of dwords. */
204 uint32_t *buf
; /* The command buffer. */
205 enum ring_type ring_type
;
210 enum radeon_family family
;
211 enum chip_class chip_class
;
215 uint32_t max_compute_units
;
217 uint32_t max_sh_per_se
;
219 uint32_t drm_major
; /* version */
221 uint32_t drm_patchlevel
;
224 uint32_t vce_fw_version
;
226 bool gfx_ib_pad_with_type2
;
228 uint32_t r300_num_gb_pipes
;
229 uint32_t r300_num_z_pipes
;
231 uint32_t r600_num_backends
;
232 uint32_t r600_clock_crystal_freq
;
233 uint32_t r600_tiling_config
;
234 uint32_t r600_num_tile_pipes
;
235 uint32_t r600_max_pipes
;
236 boolean r600_virtual_address
;
237 boolean r600_has_dma
;
239 uint32_t r600_backend_map
;
240 boolean r600_backend_map_valid
;
242 boolean si_tile_mode_array_valid
;
243 uint32_t si_tile_mode_array
[32];
244 uint32_t si_backend_enabled_mask
;
246 boolean cik_macrotile_mode_array_valid
;
247 uint32_t cik_macrotile_mode_array
[16];
248 uint32_t vce_harvest_config
;
251 enum radeon_feature_id
{
252 RADEON_FID_R300_HYPERZ_ACCESS
, /* ZMask + HiZ */
253 RADEON_FID_R300_CMASK_ACCESS
,
256 #define RADEON_SURF_MAX_LEVEL 32
258 #define RADEON_SURF_TYPE_MASK 0xFF
259 #define RADEON_SURF_TYPE_SHIFT 0
260 #define RADEON_SURF_TYPE_1D 0
261 #define RADEON_SURF_TYPE_2D 1
262 #define RADEON_SURF_TYPE_3D 2
263 #define RADEON_SURF_TYPE_CUBEMAP 3
264 #define RADEON_SURF_TYPE_1D_ARRAY 4
265 #define RADEON_SURF_TYPE_2D_ARRAY 5
266 #define RADEON_SURF_MODE_MASK 0xFF
267 #define RADEON_SURF_MODE_SHIFT 8
268 #define RADEON_SURF_MODE_LINEAR 0
269 #define RADEON_SURF_MODE_LINEAR_ALIGNED 1
270 #define RADEON_SURF_MODE_1D 2
271 #define RADEON_SURF_MODE_2D 3
272 #define RADEON_SURF_SCANOUT (1 << 16)
273 #define RADEON_SURF_ZBUFFER (1 << 17)
274 #define RADEON_SURF_SBUFFER (1 << 18)
275 #define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
276 #define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19)
277 #define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20)
278 #define RADEON_SURF_FMASK (1 << 21)
280 #define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
281 #define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
282 #define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
284 struct radeon_surf_level
{
293 uint32_t pitch_bytes
;
298 /* These are inputs to the calculator. */
311 /* These are return values. Some of them can be set by the caller, but
312 * they will be treated as hints (e.g. bankw, bankh) and might be
313 * changed by the calculator.
316 uint64_t bo_alignment
;
317 /* This applies to EG and later. */
322 uint32_t stencil_tile_split
;
323 uint64_t stencil_offset
;
324 struct radeon_surf_level level
[RADEON_SURF_MAX_LEVEL
];
325 struct radeon_surf_level stencil_level
[RADEON_SURF_MAX_LEVEL
];
326 uint32_t tiling_index
[RADEON_SURF_MAX_LEVEL
];
327 uint32_t stencil_tiling_index
[RADEON_SURF_MAX_LEVEL
];
328 uint32_t pipe_config
;
332 struct radeon_winsys
{
334 * The screen object this winsys was created for
336 struct pipe_screen
*screen
;
339 * Decrement the winsys reference count.
341 * \param ws The winsys this function is called for.
342 * \return True if the winsys and screen should be destroyed.
344 bool (*unref
)(struct radeon_winsys
*ws
);
347 * Destroy this winsys.
349 * \param ws The winsys this function is called from.
351 void (*destroy
)(struct radeon_winsys
*ws
);
354 * Query an info structure from winsys.
356 * \param ws The winsys this function is called from.
357 * \param info Return structure
359 void (*query_info
)(struct radeon_winsys
*ws
,
360 struct radeon_info
*info
);
362 /**************************************************************************
363 * Buffer management. Buffer attributes are mostly fixed over its lifetime.
365 * Remember that gallium gets to choose the interface it needs, and the
366 * window systems must then implement that interface (rather than the
367 * other way around...).
368 *************************************************************************/
371 * Create a buffer object.
373 * \param ws The winsys this function is called from.
374 * \param size The size to allocate.
375 * \param alignment An alignment of the buffer in memory.
376 * \param use_reusable_pool Whether the cache buffer manager should be used.
377 * \param domain A bitmask of the RADEON_DOMAIN_* flags.
378 * \return The created buffer object.
380 struct pb_buffer
*(*buffer_create
)(struct radeon_winsys
*ws
,
383 boolean use_reusable_pool
,
384 enum radeon_bo_domain domain
,
385 enum radeon_bo_flag flags
);
387 struct radeon_winsys_cs_handle
*(*buffer_get_cs_handle
)(
388 struct pb_buffer
*buf
);
391 * Map the entire data store of a buffer object into the client's address
394 * \param buf A winsys buffer object to map.
395 * \param cs A command stream to flush if the buffer is referenced by it.
396 * \param usage A bitmask of the PIPE_TRANSFER_* flags.
397 * \return The pointer at the beginning of the buffer.
399 void *(*buffer_map
)(struct radeon_winsys_cs_handle
*buf
,
400 struct radeon_winsys_cs
*cs
,
401 enum pipe_transfer_usage usage
);
404 * Unmap a buffer object from the client's address space.
406 * \param buf A winsys buffer object to unmap.
408 void (*buffer_unmap
)(struct radeon_winsys_cs_handle
*buf
);
411 * Wait for the buffer and return true if the buffer is not used
414 * The timeout of 0 will only return the status.
415 * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
418 bool (*buffer_wait
)(struct pb_buffer
*buf
, uint64_t timeout
,
419 enum radeon_bo_usage usage
);
422 * Return tiling flags describing a memory layout of a buffer object.
424 * \param buf A winsys buffer object to get the flags from.
425 * \param macrotile A pointer to the return value of the microtile flag.
426 * \param microtile A pointer to the return value of the macrotile flag.
428 * \note microtile and macrotile are not bitmasks!
430 void (*buffer_get_tiling
)(struct pb_buffer
*buf
,
431 enum radeon_bo_layout
*microtile
,
432 enum radeon_bo_layout
*macrotile
,
433 unsigned *bankw
, unsigned *bankh
,
434 unsigned *tile_split
,
435 unsigned *stencil_tile_split
,
440 * Set tiling flags describing a memory layout of a buffer object.
442 * \param buf A winsys buffer object to set the flags for.
443 * \param cs A command stream to flush if the buffer is referenced by it.
444 * \param macrotile A macrotile flag.
445 * \param microtile A microtile flag.
446 * \param stride A stride of the buffer in bytes, for texturing.
448 * \note microtile and macrotile are not bitmasks!
450 void (*buffer_set_tiling
)(struct pb_buffer
*buf
,
451 struct radeon_winsys_cs
*rcs
,
452 enum radeon_bo_layout microtile
,
453 enum radeon_bo_layout macrotile
,
454 unsigned pipe_config
,
455 unsigned bankw
, unsigned bankh
,
457 unsigned stencil_tile_split
,
458 unsigned mtilea
, unsigned num_banks
,
463 * Get a winsys buffer from a winsys handle. The internal structure
464 * of the handle is platform-specific and only a winsys should access it.
466 * \param ws The winsys this function is called from.
467 * \param whandle A winsys handle pointer as was received from a state
469 * \param stride The returned buffer stride in bytes.
471 struct pb_buffer
*(*buffer_from_handle
)(struct radeon_winsys
*ws
,
472 struct winsys_handle
*whandle
,
476 * Get a winsys buffer from a user pointer. The resulting buffer can't
477 * be exported. Both pointer and size must be page aligned.
479 * \param ws The winsys this function is called from.
480 * \param pointer User pointer to turn into a buffer object.
481 * \param Size Size in bytes for the new buffer.
483 struct pb_buffer
*(*buffer_from_ptr
)(struct radeon_winsys
*ws
,
484 void *pointer
, unsigned size
);
487 * Get a winsys handle from a winsys buffer. The internal structure
488 * of the handle is platform-specific and only a winsys should access it.
490 * \param buf A winsys buffer object to get the handle from.
491 * \param whandle A winsys handle pointer.
492 * \param stride A stride of the buffer in bytes, for texturing.
493 * \return TRUE on success.
495 boolean (*buffer_get_handle
)(struct pb_buffer
*buf
,
497 struct winsys_handle
*whandle
);
500 * Return the virtual address of a buffer.
502 * \param buf A winsys buffer object
503 * \return virtual address
505 uint64_t (*buffer_get_virtual_address
)(struct radeon_winsys_cs_handle
*buf
);
508 * Query the initial placement of the buffer from the kernel driver.
510 enum radeon_bo_domain (*buffer_get_initial_domain
)(struct radeon_winsys_cs_handle
*buf
);
512 /**************************************************************************
513 * Command submission.
515 * Each pipe context should create its own command stream and submit
516 * commands independently of other contexts.
517 *************************************************************************/
520 * Create a command submission context.
521 * Various command streams can be submitted to the same context.
523 struct radeon_winsys_ctx
*(*ctx_create
)(struct radeon_winsys
*ws
);
528 void (*ctx_destroy
)(struct radeon_winsys_ctx
*ctx
);
531 * Query a GPU reset status.
533 enum pipe_reset_status (*ctx_query_reset_status
)(struct radeon_winsys_ctx
*ctx
);
536 * Create a command stream.
538 * \param ctx The submission context
539 * \param ring_type The ring type (GFX, DMA, UVD)
540 * \param flush Flush callback function associated with the command stream.
541 * \param user User pointer that will be passed to the flush callback.
542 * \param trace_buf Trace buffer when tracing is enabled
544 struct radeon_winsys_cs
*(*cs_create
)(struct radeon_winsys_ctx
*ctx
,
545 enum ring_type ring_type
,
546 void (*flush
)(void *ctx
, unsigned flags
,
547 struct pipe_fence_handle
**fence
),
549 struct radeon_winsys_cs_handle
*trace_buf
);
552 * Destroy a command stream.
554 * \param cs A command stream to destroy.
556 void (*cs_destroy
)(struct radeon_winsys_cs
*cs
);
559 * Add a new buffer relocation. Every relocation must first be added
560 * before it can be written.
562 * \param cs A command stream to add buffer for validation against.
563 * \param buf A winsys buffer to validate.
564 * \param usage Whether the buffer is used for read and/or write.
565 * \param domain Bitmask of the RADEON_DOMAIN_* flags.
566 * \param priority A higher number means a greater chance of being
567 * placed in the requested domain. 15 is the maximum.
568 * \return Relocation index.
570 unsigned (*cs_add_reloc
)(struct radeon_winsys_cs
*cs
,
571 struct radeon_winsys_cs_handle
*buf
,
572 enum radeon_bo_usage usage
,
573 enum radeon_bo_domain domain
,
574 enum radeon_bo_priority priority
);
577 * Return the index of an already-added buffer.
579 * \param cs Command stream
581 * \return The buffer index, or -1 if the buffer has not been added.
583 int (*cs_get_reloc
)(struct radeon_winsys_cs
*cs
,
584 struct radeon_winsys_cs_handle
*buf
);
587 * Return TRUE if there is enough memory in VRAM and GTT for the relocs
588 * added so far. If the validation fails, all the relocations which have
589 * been added since the last call of cs_validate will be removed and
590 * the CS will be flushed (provided there are still any relocations).
592 * \param cs A command stream to validate.
594 boolean (*cs_validate
)(struct radeon_winsys_cs
*cs
);
597 * Return TRUE if there is enough memory in VRAM and GTT for the relocs
600 * \param cs A command stream to validate.
601 * \param vram VRAM memory size pending to be use
602 * \param gtt GTT memory size pending to be use
604 boolean (*cs_memory_below_limit
)(struct radeon_winsys_cs
*cs
, uint64_t vram
, uint64_t gtt
);
607 * Flush a command stream.
609 * \param cs A command stream to flush.
610 * \param flags, RADEON_FLUSH_ASYNC or 0.
611 * \param fence Pointer to a fence. If non-NULL, a fence is inserted
612 * after the CS and is returned through this parameter.
613 * \param cs_trace_id A unique identifier of the cs, used for tracing.
615 void (*cs_flush
)(struct radeon_winsys_cs
*cs
,
617 struct pipe_fence_handle
**fence
,
618 uint32_t cs_trace_id
);
621 * Return TRUE if a buffer is referenced by a command stream.
623 * \param cs A command stream.
624 * \param buf A winsys buffer.
626 boolean (*cs_is_buffer_referenced
)(struct radeon_winsys_cs
*cs
,
627 struct radeon_winsys_cs_handle
*buf
,
628 enum radeon_bo_usage usage
);
631 * Request access to a feature for a command stream.
633 * \param cs A command stream.
634 * \param fid Feature ID, one of RADEON_FID_*
635 * \param enable Whether to enable or disable the feature.
637 boolean (*cs_request_feature
)(struct radeon_winsys_cs
*cs
,
638 enum radeon_feature_id fid
,
641 * Make sure all asynchronous flush of the cs have completed
643 * \param cs A command stream.
645 void (*cs_sync_flush
)(struct radeon_winsys_cs
*cs
);
648 * Wait for the fence and return true if the fence has been signalled.
649 * The timeout of 0 will only return the status.
650 * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
653 bool (*fence_wait
)(struct radeon_winsys
*ws
,
654 struct pipe_fence_handle
*fence
,
658 * Reference counting for fences.
660 void (*fence_reference
)(struct pipe_fence_handle
**dst
,
661 struct pipe_fence_handle
*src
);
666 * \param ws The winsys this function is called from.
667 * \param surf Surface structure ptr
669 int (*surface_init
)(struct radeon_winsys
*ws
,
670 struct radeon_surf
*surf
);
673 * Find best values for a surface
675 * \param ws The winsys this function is called from.
676 * \param surf Surface structure ptr
678 int (*surface_best
)(struct radeon_winsys
*ws
,
679 struct radeon_surf
*surf
);
681 uint64_t (*query_value
)(struct radeon_winsys
*ws
,
682 enum radeon_value_id value
);
684 bool (*read_registers
)(struct radeon_winsys
*ws
, unsigned reg_offset
,
685 unsigned num_registers
, uint32_t *out
);
689 static inline void radeon_emit(struct radeon_winsys_cs
*cs
, uint32_t value
)
691 cs
->buf
[cs
->cdw
++] = value
;
694 static inline void radeon_emit_array(struct radeon_winsys_cs
*cs
,
695 const uint32_t *values
, unsigned count
)
697 memcpy(cs
->buf
+cs
->cdw
, values
, count
* 4);