src/gallium/drivers/radeon/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #ifndef RADEON_WINSYS_H
  25 #define RADEON_WINSYS_H
  26
  27 /* The public winsys interface header for the radeon driver. */
  28
  29 #include "pipebuffer/pb_buffer.h"
  30
  31 #define RADEON_FLUSH_ASYNC              (1 << 0)
  32 #define RADEON_FLUSH_END_OF_FRAME       (1 << 1)
  33
  34 /* Tiling flags. */
  35 enum radeon_bo_layout {
  36     RADEON_LAYOUT_LINEAR = 0,
  37     RADEON_LAYOUT_TILED,
  38     RADEON_LAYOUT_SQUARETILED,
  39
  40     RADEON_LAYOUT_UNKNOWN
  41 };
  42
  43 enum radeon_bo_domain { /* bitfield */
  44     RADEON_DOMAIN_GTT  = 2,
  45     RADEON_DOMAIN_VRAM = 4,
  46     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  47 };
  48
  49 enum radeon_bo_flag { /* bitfield */
  50     RADEON_FLAG_GTT_WC =        (1 << 0),
  51     RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  52     RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  53 };
  54
  55 enum radeon_bo_usage { /* bitfield */
  56     RADEON_USAGE_READ = 2,
  57     RADEON_USAGE_WRITE = 4,
  58     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
  59 };
  60
  61 enum radeon_family {
  62     CHIP_UNKNOWN = 0,
  63     CHIP_R300, /* R3xx-based cores. */
  64     CHIP_R350,
  65     CHIP_RV350,
  66     CHIP_RV370,
  67     CHIP_RV380,
  68     CHIP_RS400,
  69     CHIP_RC410,
  70     CHIP_RS480,
  71     CHIP_R420,     /* R4xx-based cores. */
  72     CHIP_R423,
  73     CHIP_R430,
  74     CHIP_R480,
  75     CHIP_R481,
  76     CHIP_RV410,
  77     CHIP_RS600,
  78     CHIP_RS690,
  79     CHIP_RS740,
  80     CHIP_RV515,    /* R5xx-based cores. */
  81     CHIP_R520,
  82     CHIP_RV530,
  83     CHIP_R580,
  84     CHIP_RV560,
  85     CHIP_RV570,
  86     CHIP_R600,
  87     CHIP_RV610,
  88     CHIP_RV630,
  89     CHIP_RV670,
  90     CHIP_RV620,
  91     CHIP_RV635,
  92     CHIP_RS780,
  93     CHIP_RS880,
  94     CHIP_RV770,
  95     CHIP_RV730,
  96     CHIP_RV710,
  97     CHIP_RV740,
  98     CHIP_CEDAR,
  99     CHIP_REDWOOD,
 100     CHIP_JUNIPER,
 101     CHIP_CYPRESS,
 102     CHIP_HEMLOCK,
 103     CHIP_PALM,
 104     CHIP_SUMO,
 105     CHIP_SUMO2,
 106     CHIP_BARTS,
 107     CHIP_TURKS,
 108     CHIP_CAICOS,
 109     CHIP_CAYMAN,
 110     CHIP_ARUBA,
 111     CHIP_TAHITI,
 112     CHIP_PITCAIRN,
 113     CHIP_VERDE,
 114     CHIP_OLAND,
 115     CHIP_HAINAN,
 116     CHIP_BONAIRE,
 117     CHIP_KAVERI,
 118     CHIP_KABINI,
 119     CHIP_HAWAII,
 120     CHIP_MULLINS,
 121     CHIP_TONGA,
 122     CHIP_ICELAND,
 123     CHIP_CARRIZO,
 124     CHIP_FIJI,
 125     CHIP_STONEY,
 126     CHIP_POLARIS10,
 127     CHIP_POLARIS11,
 128     CHIP_LAST,
 129 };
 130
 131 enum chip_class {
 132     CLASS_UNKNOWN = 0,
 133     R300,
 134     R400,
 135     R500,
 136     R600,
 137     R700,
 138     EVERGREEN,
 139     CAYMAN,
 140     SI,
 141     CIK,
 142     VI,
 143 };
 144
 145 enum ring_type {
 146     RING_GFX = 0,
 147     RING_COMPUTE,
 148     RING_DMA,
 149     RING_UVD,
 150     RING_VCE,
 151     RING_LAST,
 152 };
 153
 154 enum radeon_value_id {
 155     RADEON_REQUESTED_VRAM_MEMORY,
 156     RADEON_REQUESTED_GTT_MEMORY,
 157     RADEON_BUFFER_WAIT_TIME_NS,
 158     RADEON_TIMESTAMP,
 159     RADEON_NUM_CS_FLUSHES,
 160     RADEON_NUM_BYTES_MOVED,
 161     RADEON_VRAM_USAGE,
 162     RADEON_GTT_USAGE,
 163     RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
 164     RADEON_CURRENT_SCLK,
 165     RADEON_CURRENT_MCLK,
 166     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
 167 };
 168
 169 /* Each group of four has the same priority. */
 170 enum radeon_bo_priority {
 171     RADEON_PRIO_FENCE = 0,
 172     RADEON_PRIO_TRACE,
 173     RADEON_PRIO_SO_FILLED_SIZE,
 174     RADEON_PRIO_QUERY,
 175
 176     RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
 177     RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
 178     RADEON_PRIO_DRAW_INDIRECT,
 179     RADEON_PRIO_INDEX_BUFFER,
 180
 181     RADEON_PRIO_CP_DMA = 8,
 182
 183     RADEON_PRIO_VCE = 12,
 184     RADEON_PRIO_UVD,
 185     RADEON_PRIO_SDMA_BUFFER,
 186     RADEON_PRIO_SDMA_TEXTURE,
 187
 188     RADEON_PRIO_USER_SHADER = 16,
 189     RADEON_PRIO_INTERNAL_SHADER, /* fetch shader, etc. */
 190
 191     /* gap: 20 */
 192
 193     RADEON_PRIO_CONST_BUFFER = 24,
 194     RADEON_PRIO_DESCRIPTORS,
 195     RADEON_PRIO_BORDER_COLORS,
 196
 197     RADEON_PRIO_SAMPLER_BUFFER = 28,
 198     RADEON_PRIO_VERTEX_BUFFER,
 199
 200     RADEON_PRIO_SHADER_RW_BUFFER = 32,
 201     RADEON_PRIO_RINGS_STREAMOUT,
 202     RADEON_PRIO_SCRATCH_BUFFER,
 203     RADEON_PRIO_COMPUTE_GLOBAL,
 204
 205     RADEON_PRIO_SAMPLER_TEXTURE = 36,
 206     RADEON_PRIO_SHADER_RW_IMAGE,
 207
 208     RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 40,
 209
 210     RADEON_PRIO_COLOR_BUFFER = 44,
 211
 212     RADEON_PRIO_DEPTH_BUFFER = 48,
 213
 214     RADEON_PRIO_COLOR_BUFFER_MSAA = 52,
 215
 216     RADEON_PRIO_DEPTH_BUFFER_MSAA = 56,
 217
 218     RADEON_PRIO_CMASK = 60,
 219     RADEON_PRIO_DCC,
 220     RADEON_PRIO_HTILE,
 221     /* 63 is the maximum value */
 222 };
 223
 224 struct winsys_handle;
 225 struct radeon_winsys_ctx;
 226
 227 struct radeon_winsys_cs_chunk {
 228     unsigned cdw;  /* Number of used dwords. */
 229     unsigned max_dw; /* Maximum number of dwords. */
 230     uint32_t *buf; /* The base pointer of the chunk. */
 231 };
 232
 233 struct radeon_winsys_cs {
 234     struct radeon_winsys_cs_chunk current;
 235     struct radeon_winsys_cs_chunk *prev;
 236     unsigned                      num_prev; /* Number of previous chunks. */
 237     unsigned                      max_prev; /* Space in array pointed to by prev. */
 238     unsigned                      prev_dw; /* Total number of dwords in previous chunks. */
 239
 240     /* Memory usage of the buffer list. These are always 0 for CE and preamble
 241      * IBs. */
 242     uint64_t                      used_vram;
 243     uint64_t                      used_gart;
 244 };
 245
 246 struct radeon_info {
 247     /* PCI info: domain:bus:dev:func */
 248     uint32_t                    pci_domain;
 249     uint32_t                    pci_bus;
 250     uint32_t                    pci_dev;
 251     uint32_t                    pci_func;
 252
 253     /* Device info. */
 254     uint32_t                    pci_id;
 255     enum radeon_family          family;
 256     enum chip_class             chip_class;
 257     uint32_t                    gart_page_size;
 258     uint64_t                    gart_size;
 259     uint64_t                    vram_size;
 260     uint64_t                    max_alloc_size;
 261     bool                        has_dedicated_vram;
 262     bool                        has_virtual_memory;
 263     bool                        gfx_ib_pad_with_type2;
 264     bool                        has_sdma;
 265     bool                        has_uvd;
 266     uint32_t                    uvd_fw_version;
 267     uint32_t                    vce_fw_version;
 268     uint32_t                    vce_harvest_config;
 269     uint32_t                    clock_crystal_freq;
 270
 271     /* Kernel info. */
 272     uint32_t                    drm_major; /* version */
 273     uint32_t                    drm_minor;
 274     uint32_t                    drm_patchlevel;
 275     bool                        has_userptr;
 276
 277     /* Shader cores. */
 278     uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
 279     uint32_t                    max_shader_clock;
 280     uint32_t                    num_good_compute_units;
 281     uint32_t                    max_se; /* shader engines */
 282     uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 283
 284     /* Render backends (color + depth blocks). */
 285     uint32_t                    r300_num_gb_pipes;
 286     uint32_t                    r300_num_z_pipes;
 287     uint32_t                    r600_gb_backend_map; /* R600 harvest config */
 288     bool                        r600_gb_backend_map_valid;
 289     uint32_t                    r600_num_banks;
 290     uint32_t                    num_render_backends;
 291     uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
 292     uint32_t                    pipe_interleave_bytes;
 293     uint32_t                    enabled_rb_mask; /* GCN harvest config */
 294
 295     /* Tile modes. */
 296     uint32_t                    si_tile_mode_array[32];
 297     uint32_t                    cik_macrotile_mode_array[16];
 298 };
 299
 300 /* Tiling info for display code, DRI sharing, and other data. */
 301 struct radeon_bo_metadata {
 302     /* Tiling flags describing the texture layout for display code
 303      * and DRI sharing.
 304      */
 305     enum radeon_bo_layout   microtile;
 306     enum radeon_bo_layout   macrotile;
 307     unsigned                pipe_config;
 308     unsigned                bankw;
 309     unsigned                bankh;
 310     unsigned                tile_split;
 311     unsigned                mtilea;
 312     unsigned                num_banks;
 313     unsigned                stride;
 314     bool                    scanout;
 315
 316     /* Additional metadata associated with the buffer, in bytes.
 317      * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 318      * Supported by amdgpu only.
 319      */
 320     uint32_t                size_metadata;
 321     uint32_t                metadata[64];
 322 };
 323
 324 enum radeon_feature_id {
 325     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 326     RADEON_FID_R300_CMASK_ACCESS,
 327 };
 328
 329 #define RADEON_SURF_MAX_LEVEL                   32
 330
 331 #define RADEON_SURF_TYPE_MASK                   0xFF
 332 #define RADEON_SURF_TYPE_SHIFT                  0
 333 #define     RADEON_SURF_TYPE_1D                     0
 334 #define     RADEON_SURF_TYPE_2D                     1
 335 #define     RADEON_SURF_TYPE_3D                     2
 336 #define     RADEON_SURF_TYPE_CUBEMAP                3
 337 #define     RADEON_SURF_TYPE_1D_ARRAY               4
 338 #define     RADEON_SURF_TYPE_2D_ARRAY               5
 339 #define RADEON_SURF_MODE_MASK                   0xFF
 340 #define RADEON_SURF_MODE_SHIFT                  8
 341 #define     RADEON_SURF_MODE_LINEAR_ALIGNED         1
 342 #define     RADEON_SURF_MODE_1D                     2
 343 #define     RADEON_SURF_MODE_2D                     3
 344 #define RADEON_SURF_SCANOUT                     (1 << 16)
 345 #define RADEON_SURF_ZBUFFER                     (1 << 17)
 346 #define RADEON_SURF_SBUFFER                     (1 << 18)
 347 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
 348 #define RADEON_SURF_HAS_SBUFFER_MIPTREE         (1 << 19)
 349 #define RADEON_SURF_HAS_TILE_MODE_INDEX         (1 << 20)
 350 #define RADEON_SURF_FMASK                       (1 << 21)
 351 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
 352
 353 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
 354 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
 355 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
 356
 357 struct radeon_surf_level {
 358     uint64_t                    offset;
 359     uint64_t                    slice_size;
 360     uint32_t                    npix_x;
 361     uint32_t                    npix_y;
 362     uint32_t                    npix_z;
 363     uint32_t                    nblk_x;
 364     uint32_t                    nblk_y;
 365     uint32_t                    nblk_z;
 366     uint32_t                    pitch_bytes;
 367     uint32_t                    mode;
 368     uint64_t                    dcc_offset;
 369     uint64_t                    dcc_fast_clear_size;
 370     bool                        dcc_enabled;
 371 };
 372
 373 struct radeon_surf {
 374     /* These are inputs to the calculator. */
 375     uint32_t                    npix_x;
 376     uint32_t                    npix_y;
 377     uint32_t                    npix_z;
 378     uint32_t                    blk_w;
 379     uint32_t                    blk_h;
 380     uint32_t                    blk_d;
 381     uint32_t                    array_size;
 382     uint32_t                    last_level;
 383     uint32_t                    bpe;
 384     uint32_t                    nsamples;
 385     uint32_t                    flags;
 386
 387     /* These are return values. Some of them can be set by the caller, but
 388      * they will be treated as hints (e.g. bankw, bankh) and might be
 389      * changed by the calculator.
 390      */
 391     uint64_t                    bo_size;
 392     uint64_t                    bo_alignment;
 393     /* This applies to EG and later. */
 394     uint32_t                    bankw;
 395     uint32_t                    bankh;
 396     uint32_t                    mtilea;
 397     uint32_t                    tile_split;
 398     uint32_t                    stencil_tile_split;
 399     struct radeon_surf_level    level[RADEON_SURF_MAX_LEVEL];
 400     struct radeon_surf_level    stencil_level[RADEON_SURF_MAX_LEVEL];
 401     uint32_t                    tiling_index[RADEON_SURF_MAX_LEVEL];
 402     uint32_t                    stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
 403     uint32_t                    pipe_config;
 404     uint32_t                    num_banks;
 405     uint32_t                    macro_tile_index;
 406     uint32_t                    micro_tile_mode; /* displayable, thin, depth, rotated */
 407
 408     /* Whether the depth miptree or stencil miptree as used by the DB are
 409      * adjusted from their TC compatible form to ensure depth/stencil
 410      * compatibility. If either is true, the corresponding plane cannot be
 411      * sampled from.
 412      */
 413     bool                        depth_adjusted;
 414     bool                        stencil_adjusted;
 415
 416     uint64_t                    dcc_size;
 417     uint64_t                    dcc_alignment;
 418 };
 419
 420 struct radeon_bo_list_item {
 421     uint64_t bo_size;
 422     uint64_t vm_address;
 423     uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
 424 };
 425
 426 struct radeon_winsys {
 427     /**
 428      * The screen object this winsys was created for
 429      */
 430     struct pipe_screen *screen;
 431
 432     /**
 433      * Decrement the winsys reference count.
 434      *
 435      * \param ws  The winsys this function is called for.
 436      * \return    True if the winsys and screen should be destroyed.
 437      */
 438     bool (*unref)(struct radeon_winsys *ws);
 439
 440     /**
 441      * Destroy this winsys.
 442      *
 443      * \param ws        The winsys this function is called from.
 444      */
 445     void (*destroy)(struct radeon_winsys *ws);
 446
 447     /**
 448      * Query an info structure from winsys.
 449      *
 450      * \param ws        The winsys this function is called from.
 451      * \param info      Return structure
 452      */
 453     void (*query_info)(struct radeon_winsys *ws,
 454                        struct radeon_info *info);
 455
 456     /**************************************************************************
 457      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 458      *
 459      * Remember that gallium gets to choose the interface it needs, and the
 460      * window systems must then implement that interface (rather than the
 461      * other way around...).
 462      *************************************************************************/
 463
 464     /**
 465      * Create a buffer object.
 466      *
 467      * \param ws        The winsys this function is called from.
 468      * \param size      The size to allocate.
 469      * \param alignment An alignment of the buffer in memory.
 470      * \param use_reusable_pool Whether the cache buffer manager should be used.
 471      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 472      * \return          The created buffer object.
 473      */
 474     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 475                                        uint64_t size,
 476                                        unsigned alignment,
 477                                        enum radeon_bo_domain domain,
 478                                        enum radeon_bo_flag flags);
 479
 480     /**
 481      * Map the entire data store of a buffer object into the client's address
 482      * space.
 483      *
 484      * \param buf       A winsys buffer object to map.
 485      * \param cs        A command stream to flush if the buffer is referenced by it.
 486      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 487      * \return          The pointer at the beginning of the buffer.
 488      */
 489     void *(*buffer_map)(struct pb_buffer *buf,
 490                         struct radeon_winsys_cs *cs,
 491                         enum pipe_transfer_usage usage);
 492
 493     /**
 494      * Unmap a buffer object from the client's address space.
 495      *
 496      * \param buf       A winsys buffer object to unmap.
 497      */
 498     void (*buffer_unmap)(struct pb_buffer *buf);
 499
 500     /**
 501      * Wait for the buffer and return true if the buffer is not used
 502      * by the device.
 503      *
 504      * The timeout of 0 will only return the status.
 505      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
 506      * is idle.
 507      */
 508     bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
 509                         enum radeon_bo_usage usage);
 510
 511     /**
 512      * Return buffer metadata.
 513      * (tiling info for display code, DRI sharing, and other data)
 514      *
 515      * \param buf       A winsys buffer object to get the flags from.
 516      * \param md        Metadata
 517      */
 518     void (*buffer_get_metadata)(struct pb_buffer *buf,
 519                                 struct radeon_bo_metadata *md);
 520
 521     /**
 522      * Set buffer metadata.
 523      * (tiling info for display code, DRI sharing, and other data)
 524      *
 525      * \param buf       A winsys buffer object to set the flags for.
 526      * \param md        Metadata
 527      */
 528     void (*buffer_set_metadata)(struct pb_buffer *buf,
 529                                 struct radeon_bo_metadata *md);
 530
 531     /**
 532      * Get a winsys buffer from a winsys handle. The internal structure
 533      * of the handle is platform-specific and only a winsys should access it.
 534      *
 535      * \param ws        The winsys this function is called from.
 536      * \param whandle   A winsys handle pointer as was received from a state
 537      *                  tracker.
 538      * \param stride    The returned buffer stride in bytes.
 539      */
 540     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 541                                             struct winsys_handle *whandle,
 542                                             unsigned *stride, unsigned *offset);
 543
 544     /**
 545      * Get a winsys buffer from a user pointer. The resulting buffer can't
 546      * be exported. Both pointer and size must be page aligned.
 547      *
 548      * \param ws        The winsys this function is called from.
 549      * \param pointer   User pointer to turn into a buffer object.
 550      * \param Size      Size in bytes for the new buffer.
 551      */
 552     struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
 553                                          void *pointer, uint64_t size);
 554
 555     /**
 556      * Whether the buffer was created from a user pointer.
 557      *
 558      * \param buf       A winsys buffer object
 559      * \return          whether \p buf was created via buffer_from_ptr
 560      */
 561     bool (*buffer_is_user_ptr)(struct pb_buffer *buf);
 562
 563     /**
 564      * Get a winsys handle from a winsys buffer. The internal structure
 565      * of the handle is platform-specific and only a winsys should access it.
 566      *
 567      * \param buf       A winsys buffer object to get the handle from.
 568      * \param whandle   A winsys handle pointer.
 569      * \param stride    A stride of the buffer in bytes, for texturing.
 570      * \return          true on success.
 571      */
 572     bool (*buffer_get_handle)(struct pb_buffer *buf,
 573                               unsigned stride, unsigned offset,
 574                               unsigned slice_size,
 575                               struct winsys_handle *whandle);
 576
 577     /**
 578      * Return the virtual address of a buffer.
 579      *
 580      * \param buf       A winsys buffer object
 581      * \return          virtual address
 582      */
 583     uint64_t (*buffer_get_virtual_address)(struct pb_buffer *buf);
 584
 585     /**
 586      * Query the initial placement of the buffer from the kernel driver.
 587      */
 588     enum radeon_bo_domain (*buffer_get_initial_domain)(struct pb_buffer *buf);
 589
 590     /**************************************************************************
 591      * Command submission.
 592      *
 593      * Each pipe context should create its own command stream and submit
 594      * commands independently of other contexts.
 595      *************************************************************************/
 596
 597     /**
 598      * Create a command submission context.
 599      * Various command streams can be submitted to the same context.
 600      */
 601     struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 602
 603     /**
 604      * Destroy a context.
 605      */
 606     void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 607
 608     /**
 609      * Query a GPU reset status.
 610      */
 611     enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
 612
 613     /**
 614      * Create a command stream.
 615      *
 616      * \param ctx       The submission context
 617      * \param ring_type The ring type (GFX, DMA, UVD)
 618      * \param flush     Flush callback function associated with the command stream.
 619      * \param user      User pointer that will be passed to the flush callback.
 620      */
 621     struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys_ctx *ctx,
 622                                           enum ring_type ring_type,
 623                                           void (*flush)(void *ctx, unsigned flags,
 624                                                         struct pipe_fence_handle **fence),
 625                                           void *flush_ctx);
 626
 627     /**
 628      * Add a constant engine IB to a graphics CS. This makes the graphics CS
 629      * from "cs_create" a group of two IBs that share a buffer list and are
 630      * flushed together.
 631      *
 632      * The returned constant CS is only a stream for writing packets to the new
 633      * IB. Calling other winsys functions with it is not allowed, not even
 634      * "cs_destroy".
 635      *
 636      * In order to add buffers and check memory usage, use the graphics CS.
 637      * In order to flush it, use the graphics CS, which will flush both IBs.
 638      * Destroying the graphics CS will destroy both of them.
 639      *
 640      * \param cs  The graphics CS from "cs_create" that will hold the buffer
 641      *            list and will be used for flushing.
 642      */
 643     struct radeon_winsys_cs *(*cs_add_const_ib)(struct radeon_winsys_cs *cs);
 644
 645      /**
 646      * Add a constant engine preamble IB to a graphics CS. This add an extra IB
 647      * in similar manner to cs_add_const_ib. This should always be called after
 648      * cs_add_const_ib.
 649      *
 650      * The returned IB is a constant engine IB that only gets flushed if the
 651      * context changed.
 652      *
 653      * \param cs  The graphics CS from "cs_create" that will hold the buffer
 654      *            list and will be used for flushing.
 655      */
 656     struct radeon_winsys_cs *(*cs_add_const_preamble_ib)(struct radeon_winsys_cs *cs);
 657     /**
 658      * Destroy a command stream.
 659      *
 660      * \param cs        A command stream to destroy.
 661      */
 662     void (*cs_destroy)(struct radeon_winsys_cs *cs);
 663
 664     /**
 665      * Add a buffer. Each buffer used by a CS must be added using this function.
 666      *
 667      * \param cs      Command stream
 668      * \param buf     Buffer
 669      * \param usage   Whether the buffer is used for read and/or write.
 670      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 671      * \param priority  A higher number means a greater chance of being
 672      *                  placed in the requested domain. 15 is the maximum.
 673      * \return Buffer index.
 674      */
 675     unsigned (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 676                              struct pb_buffer *buf,
 677                              enum radeon_bo_usage usage,
 678                              enum radeon_bo_domain domain,
 679                              enum radeon_bo_priority priority);
 680
 681     /**
 682      * Return the index of an already-added buffer.
 683      *
 684      * \param cs        Command stream
 685      * \param buf       Buffer
 686      * \return          The buffer index, or -1 if the buffer has not been added.
 687      */
 688     int (*cs_lookup_buffer)(struct radeon_winsys_cs *cs,
 689                             struct pb_buffer *buf);
 690
 691     /**
 692      * Return true if there is enough memory in VRAM and GTT for the buffers
 693      * added so far. If the validation fails, all buffers which have
 694      * been added since the last call of cs_validate will be removed and
 695      * the CS will be flushed (provided there are still any buffers).
 696      *
 697      * \param cs        A command stream to validate.
 698      */
 699     bool (*cs_validate)(struct radeon_winsys_cs *cs);
 700
 701     /**
 702      * Check whether the given number of dwords is available in the IB.
 703      * Optionally chain a new chunk of the IB if necessary and supported.
 704      *
 705      * \param cs        A command stream.
 706      * \param dw        Number of CS dwords requested by the caller.
 707      */
 708     bool (*cs_check_space)(struct radeon_winsys_cs *cs, unsigned dw);
 709
 710     /**
 711      * Return true if there is enough memory in VRAM and GTT for the buffers
 712      * added so far.
 713      *
 714      * \param cs        A command stream to validate.
 715      * \param vram      VRAM memory size pending to be use
 716      * \param gtt       GTT memory size pending to be use
 717      */
 718     bool (*cs_memory_below_limit)(struct radeon_winsys_cs *cs,
 719                                   uint64_t vram, uint64_t gtt);
 720
 721     /**
 722      * Return the buffer list.
 723      *
 724      * \param cs    Command stream
 725      * \param list  Returned buffer list. Set to NULL to query the count only.
 726      * \return      The buffer count.
 727      */
 728     unsigned (*cs_get_buffer_list)(struct radeon_winsys_cs *cs,
 729                                    struct radeon_bo_list_item *list);
 730
 731     /**
 732      * Flush a command stream.
 733      *
 734      * \param cs          A command stream to flush.
 735      * \param flags,      RADEON_FLUSH_ASYNC or 0.
 736      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 737      *                    after the CS and is returned through this parameter.
 738      * \return Negative POSIX error code or 0 for success.
 739      *         Asynchronous submissions never return an error.
 740      */
 741     int (*cs_flush)(struct radeon_winsys_cs *cs,
 742                     unsigned flags,
 743                     struct pipe_fence_handle **fence);
 744
 745     /**
 746      * Return true if a buffer is referenced by a command stream.
 747      *
 748      * \param cs        A command stream.
 749      * \param buf       A winsys buffer.
 750      */
 751     bool (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
 752                                     struct pb_buffer *buf,
 753                                     enum radeon_bo_usage usage);
 754
 755     /**
 756      * Request access to a feature for a command stream.
 757      *
 758      * \param cs        A command stream.
 759      * \param fid       Feature ID, one of RADEON_FID_*
 760      * \param enable    Whether to enable or disable the feature.
 761      */
 762     bool (*cs_request_feature)(struct radeon_winsys_cs *cs,
 763                                enum radeon_feature_id fid,
 764                                bool enable);
 765      /**
 766       * Make sure all asynchronous flush of the cs have completed
 767       *
 768       * \param cs        A command stream.
 769       */
 770     void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
 771
 772     /**
 773      * Wait for the fence and return true if the fence has been signalled.
 774      * The timeout of 0 will only return the status.
 775      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 776      * is signalled.
 777      */
 778     bool (*fence_wait)(struct radeon_winsys *ws,
 779                        struct pipe_fence_handle *fence,
 780                        uint64_t timeout);
 781
 782     /**
 783      * Reference counting for fences.
 784      */
 785     void (*fence_reference)(struct pipe_fence_handle **dst,
 786                             struct pipe_fence_handle *src);
 787
 788     /**
 789      * Initialize surface
 790      *
 791      * \param ws        The winsys this function is called from.
 792      * \param surf      Surface structure ptr
 793      */
 794     int (*surface_init)(struct radeon_winsys *ws,
 795                         struct radeon_surf *surf);
 796
 797     /**
 798      * Find best values for a surface
 799      *
 800      * \param ws        The winsys this function is called from.
 801      * \param surf      Surface structure ptr
 802      */
 803     int (*surface_best)(struct radeon_winsys *ws,
 804                         struct radeon_surf *surf);
 805
 806     uint64_t (*query_value)(struct radeon_winsys *ws,
 807                             enum radeon_value_id value);
 808
 809     bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 810                            unsigned num_registers, uint32_t *out);
 811 };
 812
 813 static inline bool radeon_emitted(struct radeon_winsys_cs *cs, unsigned num_dw)
 814 {
 815     return cs && (cs->prev_dw + cs->current.cdw > num_dw);
 816 }
 817
 818 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 819 {
 820     cs->current.buf[cs->current.cdw++] = value;
 821 }
 822
 823 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 824                                      const uint32_t *values, unsigned count)
 825 {
 826     memcpy(cs->current.buf + cs->current.cdw, values, count * 4);
 827     cs->current.cdw += count;
 828 }
 829
 830 #endif