src/gallium/drivers/radeon/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #ifndef RADEON_WINSYS_H
  25 #define RADEON_WINSYS_H
  26
  27 /* The public winsys interface header for the radeon driver. */
  28
  29 #include "pipebuffer/pb_buffer.h"
  30
  31 #include "amd/common/ac_gpu_info.h"
  32 #include "amd/common/ac_surface.h"
  33
  34 #define RADEON_FLUSH_ASYNC              (1 << 0)
  35 #define RADEON_FLUSH_END_OF_FRAME       (1 << 1)
  36
  37 /* Tiling flags. */
  38 enum radeon_bo_layout {
  39     RADEON_LAYOUT_LINEAR = 0,
  40     RADEON_LAYOUT_TILED,
  41     RADEON_LAYOUT_SQUARETILED,
  42
  43     RADEON_LAYOUT_UNKNOWN
  44 };
  45
  46 enum radeon_bo_domain { /* bitfield */
  47     RADEON_DOMAIN_GTT  = 2,
  48     RADEON_DOMAIN_VRAM = 4,
  49     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  50 };
  51
  52 enum radeon_bo_flag { /* bitfield */
  53     RADEON_FLAG_GTT_WC =        (1 << 0),
  54     RADEON_FLAG_NO_CPU_ACCESS = (1 << 1),
  55     RADEON_FLAG_NO_SUBALLOC =   (1 << 2),
  56     RADEON_FLAG_SPARSE =        (1 << 3),
  57 };
  58
  59 enum radeon_bo_usage { /* bitfield */
  60     RADEON_USAGE_READ = 2,
  61     RADEON_USAGE_WRITE = 4,
  62     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE,
  63
  64     /* The winsys ensures that the CS submission will be scheduled after
  65      * previously flushed CSs referencing this BO in a conflicting way.
  66      */
  67     RADEON_USAGE_SYNCHRONIZED = 8
  68 };
  69
  70 #define RADEON_SPARSE_PAGE_SIZE (64 * 1024)
  71
  72 enum ring_type {
  73     RING_GFX = 0,
  74     RING_COMPUTE,
  75     RING_DMA,
  76     RING_UVD,
  77     RING_VCE,
  78     RING_UVD_ENC,
  79     RING_VCN_DEC,
  80     RING_LAST,
  81 };
  82
  83 enum radeon_value_id {
  84     RADEON_REQUESTED_VRAM_MEMORY,
  85     RADEON_REQUESTED_GTT_MEMORY,
  86     RADEON_MAPPED_VRAM,
  87     RADEON_MAPPED_GTT,
  88     RADEON_BUFFER_WAIT_TIME_NS,
  89     RADEON_NUM_MAPPED_BUFFERS,
  90     RADEON_TIMESTAMP,
  91     RADEON_NUM_GFX_IBS,
  92     RADEON_NUM_SDMA_IBS,
  93     RADEON_GFX_BO_LIST_COUNTER, /* number of BOs submitted in gfx IBs */
  94     RADEON_NUM_BYTES_MOVED,
  95     RADEON_NUM_EVICTIONS,
  96     RADEON_NUM_VRAM_CPU_PAGE_FAULTS,
  97     RADEON_VRAM_USAGE,
  98     RADEON_VRAM_VIS_USAGE,
  99     RADEON_GTT_USAGE,
 100     RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
 101     RADEON_CURRENT_SCLK,
 102     RADEON_CURRENT_MCLK,
 103     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
 104     RADEON_CS_THREAD_TIME,
 105 };
 106
 107 /* Each group of four has the same priority. */
 108 enum radeon_bo_priority {
 109     RADEON_PRIO_FENCE = 0,
 110     RADEON_PRIO_TRACE,
 111     RADEON_PRIO_SO_FILLED_SIZE,
 112     RADEON_PRIO_QUERY,
 113
 114     RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
 115     RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
 116     RADEON_PRIO_DRAW_INDIRECT,
 117     RADEON_PRIO_INDEX_BUFFER,
 118
 119     RADEON_PRIO_VCE = 8,
 120     RADEON_PRIO_UVD,
 121     RADEON_PRIO_SDMA_BUFFER,
 122     RADEON_PRIO_SDMA_TEXTURE,
 123
 124     RADEON_PRIO_CP_DMA = 12,
 125
 126     RADEON_PRIO_CONST_BUFFER = 16,
 127     RADEON_PRIO_DESCRIPTORS,
 128     RADEON_PRIO_BORDER_COLORS,
 129
 130     RADEON_PRIO_SAMPLER_BUFFER = 20,
 131     RADEON_PRIO_VERTEX_BUFFER,
 132
 133     RADEON_PRIO_SHADER_RW_BUFFER = 24,
 134     RADEON_PRIO_COMPUTE_GLOBAL,
 135
 136     RADEON_PRIO_SAMPLER_TEXTURE = 28,
 137     RADEON_PRIO_SHADER_RW_IMAGE,
 138
 139     RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 32,
 140
 141     RADEON_PRIO_COLOR_BUFFER = 36,
 142
 143     RADEON_PRIO_DEPTH_BUFFER = 40,
 144
 145     RADEON_PRIO_COLOR_BUFFER_MSAA = 44,
 146
 147     RADEON_PRIO_DEPTH_BUFFER_MSAA = 48,
 148
 149     RADEON_PRIO_CMASK = 52,
 150     RADEON_PRIO_DCC,
 151     RADEON_PRIO_HTILE,
 152     RADEON_PRIO_SHADER_BINARY, /* the hw can't hide instruction cache misses */
 153
 154     RADEON_PRIO_SHADER_RINGS = 56,
 155
 156     RADEON_PRIO_SCRATCH_BUFFER = 60,
 157     /* 63 is the maximum value */
 158 };
 159
 160 struct winsys_handle;
 161 struct radeon_winsys_ctx;
 162
 163 struct radeon_winsys_cs_chunk {
 164     unsigned cdw;  /* Number of used dwords. */
 165     unsigned max_dw; /* Maximum number of dwords. */
 166     uint32_t *buf; /* The base pointer of the chunk. */
 167 };
 168
 169 struct radeon_winsys_cs {
 170     struct radeon_winsys_cs_chunk current;
 171     struct radeon_winsys_cs_chunk *prev;
 172     unsigned                      num_prev; /* Number of previous chunks. */
 173     unsigned                      max_prev; /* Space in array pointed to by prev. */
 174     unsigned                      prev_dw; /* Total number of dwords in previous chunks. */
 175
 176     /* Memory usage of the buffer list. These are always 0 for preamble IBs. */
 177     uint64_t                      used_vram;
 178     uint64_t                      used_gart;
 179 };
 180
 181 /* Tiling info for display code, DRI sharing, and other data. */
 182 struct radeon_bo_metadata {
 183     /* Tiling flags describing the texture layout for display code
 184      * and DRI sharing.
 185      */
 186     union {
 187         struct {
 188             enum radeon_bo_layout   microtile;
 189             enum radeon_bo_layout   macrotile;
 190             unsigned                pipe_config;
 191             unsigned                bankw;
 192             unsigned                bankh;
 193             unsigned                tile_split;
 194             unsigned                mtilea;
 195             unsigned                num_banks;
 196             unsigned                stride;
 197             bool                    scanout;
 198         } legacy;
 199
 200         struct {
 201             /* surface flags */
 202             unsigned swizzle_mode:5;
 203         } gfx9;
 204     } u;
 205
 206     /* Additional metadata associated with the buffer, in bytes.
 207      * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 208      * Supported by amdgpu only.
 209      */
 210     uint32_t                size_metadata;
 211     uint32_t                metadata[64];
 212 };
 213
 214 enum radeon_feature_id {
 215     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 216     RADEON_FID_R300_CMASK_ACCESS,
 217 };
 218
 219 struct radeon_bo_list_item {
 220     uint64_t bo_size;
 221     uint64_t vm_address;
 222     uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
 223 };
 224
 225 struct radeon_winsys {
 226     /**
 227      * The screen object this winsys was created for
 228      */
 229     struct pipe_screen *screen;
 230
 231     /**
 232      * Decrement the winsys reference count.
 233      *
 234      * \param ws  The winsys this function is called for.
 235      * \return    True if the winsys and screen should be destroyed.
 236      */
 237     bool (*unref)(struct radeon_winsys *ws);
 238
 239     /**
 240      * Destroy this winsys.
 241      *
 242      * \param ws        The winsys this function is called from.
 243      */
 244     void (*destroy)(struct radeon_winsys *ws);
 245
 246     /**
 247      * Query an info structure from winsys.
 248      *
 249      * \param ws        The winsys this function is called from.
 250      * \param info      Return structure
 251      */
 252     void (*query_info)(struct radeon_winsys *ws,
 253                        struct radeon_info *info);
 254
 255     /**************************************************************************
 256      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 257      *
 258      * Remember that gallium gets to choose the interface it needs, and the
 259      * window systems must then implement that interface (rather than the
 260      * other way around...).
 261      *************************************************************************/
 262
 263     /**
 264      * Create a buffer object.
 265      *
 266      * \param ws        The winsys this function is called from.
 267      * \param size      The size to allocate.
 268      * \param alignment An alignment of the buffer in memory.
 269      * \param use_reusable_pool Whether the cache buffer manager should be used.
 270      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 271      * \return          The created buffer object.
 272      */
 273     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 274                                        uint64_t size,
 275                                        unsigned alignment,
 276                                        enum radeon_bo_domain domain,
 277                                        enum radeon_bo_flag flags);
 278
 279     /**
 280      * Map the entire data store of a buffer object into the client's address
 281      * space.
 282      *
 283      * \param buf       A winsys buffer object to map.
 284      * \param cs        A command stream to flush if the buffer is referenced by it.
 285      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 286      * \return          The pointer at the beginning of the buffer.
 287      */
 288     void *(*buffer_map)(struct pb_buffer *buf,
 289                         struct radeon_winsys_cs *cs,
 290                         enum pipe_transfer_usage usage);
 291
 292     /**
 293      * Unmap a buffer object from the client's address space.
 294      *
 295      * \param buf       A winsys buffer object to unmap.
 296      */
 297     void (*buffer_unmap)(struct pb_buffer *buf);
 298
 299     /**
 300      * Wait for the buffer and return true if the buffer is not used
 301      * by the device.
 302      *
 303      * The timeout of 0 will only return the status.
 304      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
 305      * is idle.
 306      */
 307     bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
 308                         enum radeon_bo_usage usage);
 309
 310     /**
 311      * Return buffer metadata.
 312      * (tiling info for display code, DRI sharing, and other data)
 313      *
 314      * \param buf       A winsys buffer object to get the flags from.
 315      * \param md        Metadata
 316      */
 317     void (*buffer_get_metadata)(struct pb_buffer *buf,
 318                                 struct radeon_bo_metadata *md);
 319
 320     /**
 321      * Set buffer metadata.
 322      * (tiling info for display code, DRI sharing, and other data)
 323      *
 324      * \param buf       A winsys buffer object to set the flags for.
 325      * \param md        Metadata
 326      */
 327     void (*buffer_set_metadata)(struct pb_buffer *buf,
 328                                 struct radeon_bo_metadata *md);
 329
 330     /**
 331      * Get a winsys buffer from a winsys handle. The internal structure
 332      * of the handle is platform-specific and only a winsys should access it.
 333      *
 334      * \param ws        The winsys this function is called from.
 335      * \param whandle   A winsys handle pointer as was received from a state
 336      *                  tracker.
 337      * \param stride    The returned buffer stride in bytes.
 338      */
 339     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 340                                             struct winsys_handle *whandle,
 341                                             unsigned *stride, unsigned *offset);
 342
 343     /**
 344      * Get a winsys buffer from a user pointer. The resulting buffer can't
 345      * be exported. Both pointer and size must be page aligned.
 346      *
 347      * \param ws        The winsys this function is called from.
 348      * \param pointer   User pointer to turn into a buffer object.
 349      * \param Size      Size in bytes for the new buffer.
 350      */
 351     struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
 352                                          void *pointer, uint64_t size);
 353
 354     /**
 355      * Whether the buffer was created from a user pointer.
 356      *
 357      * \param buf       A winsys buffer object
 358      * \return          whether \p buf was created via buffer_from_ptr
 359      */
 360     bool (*buffer_is_user_ptr)(struct pb_buffer *buf);
 361
 362     /** Whether the buffer was suballocated. */
 363     bool (*buffer_is_suballocated)(struct pb_buffer *buf);
 364
 365     /**
 366      * Get a winsys handle from a winsys buffer. The internal structure
 367      * of the handle is platform-specific and only a winsys should access it.
 368      *
 369      * \param buf       A winsys buffer object to get the handle from.
 370      * \param whandle   A winsys handle pointer.
 371      * \param stride    A stride of the buffer in bytes, for texturing.
 372      * \return          true on success.
 373      */
 374     bool (*buffer_get_handle)(struct pb_buffer *buf,
 375                               unsigned stride, unsigned offset,
 376                               unsigned slice_size,
 377                               struct winsys_handle *whandle);
 378
 379     /**
 380      * Change the commitment of a (64KB-page aligned) region of the given
 381      * sparse buffer.
 382      *
 383      * \warning There is no automatic synchronization with command submission.
 384      *
 385      * \note Only implemented by the amdgpu winsys.
 386      *
 387      * \return false on out of memory or other failure, true on success.
 388      */
 389     bool (*buffer_commit)(struct pb_buffer *buf,
 390                           uint64_t offset, uint64_t size,
 391                           bool commit);
 392
 393     /**
 394      * Return the virtual address of a buffer.
 395      *
 396      * When virtual memory is not in use, this is the offset relative to the
 397      * relocation base (non-zero for sub-allocated buffers).
 398      *
 399      * \param buf       A winsys buffer object
 400      * \return          virtual address
 401      */
 402     uint64_t (*buffer_get_virtual_address)(struct pb_buffer *buf);
 403
 404     /**
 405      * Return the offset of this buffer relative to the relocation base.
 406      * This is only non-zero for sub-allocated buffers.
 407      *
 408      * This is only supported in the radeon winsys, since amdgpu uses virtual
 409      * addresses in submissions even for the video engines.
 410      *
 411      * \param buf      A winsys buffer object
 412      * \return         the offset for relocations
 413      */
 414     unsigned (*buffer_get_reloc_offset)(struct pb_buffer *buf);
 415
 416     /**
 417      * Query the initial placement of the buffer from the kernel driver.
 418      */
 419     enum radeon_bo_domain (*buffer_get_initial_domain)(struct pb_buffer *buf);
 420
 421     /**************************************************************************
 422      * Command submission.
 423      *
 424      * Each pipe context should create its own command stream and submit
 425      * commands independently of other contexts.
 426      *************************************************************************/
 427
 428     /**
 429      * Create a command submission context.
 430      * Various command streams can be submitted to the same context.
 431      */
 432     struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 433
 434     /**
 435      * Destroy a context.
 436      */
 437     void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 438
 439     /**
 440      * Query a GPU reset status.
 441      */
 442     enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
 443
 444     /**
 445      * Create a command stream.
 446      *
 447      * \param ctx       The submission context
 448      * \param ring_type The ring type (GFX, DMA, UVD)
 449      * \param flush     Flush callback function associated with the command stream.
 450      * \param user      User pointer that will be passed to the flush callback.
 451      */
 452     struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys_ctx *ctx,
 453                                           enum ring_type ring_type,
 454                                           void (*flush)(void *ctx, unsigned flags,
 455                                                         struct pipe_fence_handle **fence),
 456                                           void *flush_ctx);
 457
 458     /**
 459      * Destroy a command stream.
 460      *
 461      * \param cs        A command stream to destroy.
 462      */
 463     void (*cs_destroy)(struct radeon_winsys_cs *cs);
 464
 465     /**
 466      * Add a buffer. Each buffer used by a CS must be added using this function.
 467      *
 468      * \param cs      Command stream
 469      * \param buf     Buffer
 470      * \param usage   Whether the buffer is used for read and/or write.
 471      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 472      * \param priority  A higher number means a greater chance of being
 473      *                  placed in the requested domain. 15 is the maximum.
 474      * \return Buffer index.
 475      */
 476     unsigned (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 477                              struct pb_buffer *buf,
 478                              enum radeon_bo_usage usage,
 479                              enum radeon_bo_domain domain,
 480                              enum radeon_bo_priority priority);
 481
 482     /**
 483      * Return the index of an already-added buffer.
 484      *
 485      * Not supported on amdgpu. Drivers with GPUVM should not care about
 486      * buffer indices.
 487      *
 488      * \param cs        Command stream
 489      * \param buf       Buffer
 490      * \return          The buffer index, or -1 if the buffer has not been added.
 491      */
 492     int (*cs_lookup_buffer)(struct radeon_winsys_cs *cs,
 493                             struct pb_buffer *buf);
 494
 495     /**
 496      * Return true if there is enough memory in VRAM and GTT for the buffers
 497      * added so far. If the validation fails, all buffers which have
 498      * been added since the last call of cs_validate will be removed and
 499      * the CS will be flushed (provided there are still any buffers).
 500      *
 501      * \param cs        A command stream to validate.
 502      */
 503     bool (*cs_validate)(struct radeon_winsys_cs *cs);
 504
 505     /**
 506      * Check whether the given number of dwords is available in the IB.
 507      * Optionally chain a new chunk of the IB if necessary and supported.
 508      *
 509      * \param cs        A command stream.
 510      * \param dw        Number of CS dwords requested by the caller.
 511      */
 512     bool (*cs_check_space)(struct radeon_winsys_cs *cs, unsigned dw);
 513
 514     /**
 515      * Return the buffer list.
 516      *
 517      * This is the buffer list as passed to the kernel, i.e. it only contains
 518      * the parent buffers of sub-allocated buffers.
 519      *
 520      * \param cs    Command stream
 521      * \param list  Returned buffer list. Set to NULL to query the count only.
 522      * \return      The buffer count.
 523      */
 524     unsigned (*cs_get_buffer_list)(struct radeon_winsys_cs *cs,
 525                                    struct radeon_bo_list_item *list);
 526
 527     /**
 528      * Flush a command stream.
 529      *
 530      * \param cs          A command stream to flush.
 531      * \param flags,      RADEON_FLUSH_ASYNC or 0.
 532      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 533      *                    after the CS and is returned through this parameter.
 534      * \return Negative POSIX error code or 0 for success.
 535      *         Asynchronous submissions never return an error.
 536      */
 537     int (*cs_flush)(struct radeon_winsys_cs *cs,
 538                     unsigned flags,
 539                     struct pipe_fence_handle **fence);
 540
 541     /**
 542      * Create a fence before the CS is flushed.
 543      * The user must flush manually to complete the initializaton of the fence.
 544      * The fence must not be used before the flush.
 545      */
 546     struct pipe_fence_handle *(*cs_get_next_fence)(struct radeon_winsys_cs *cs);
 547
 548     /**
 549      * Return true if a buffer is referenced by a command stream.
 550      *
 551      * \param cs        A command stream.
 552      * \param buf       A winsys buffer.
 553      */
 554     bool (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
 555                                     struct pb_buffer *buf,
 556                                     enum radeon_bo_usage usage);
 557
 558     /**
 559      * Request access to a feature for a command stream.
 560      *
 561      * \param cs        A command stream.
 562      * \param fid       Feature ID, one of RADEON_FID_*
 563      * \param enable    Whether to enable or disable the feature.
 564      */
 565     bool (*cs_request_feature)(struct radeon_winsys_cs *cs,
 566                                enum radeon_feature_id fid,
 567                                bool enable);
 568      /**
 569       * Make sure all asynchronous flush of the cs have completed
 570       *
 571       * \param cs        A command stream.
 572       */
 573     void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
 574
 575     /**
 576      * Wait for the fence and return true if the fence has been signalled.
 577      * The timeout of 0 will only return the status.
 578      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 579      * is signalled.
 580      */
 581     bool (*fence_wait)(struct radeon_winsys *ws,
 582                        struct pipe_fence_handle *fence,
 583                        uint64_t timeout);
 584
 585     /**
 586      * Reference counting for fences.
 587      */
 588     void (*fence_reference)(struct pipe_fence_handle **dst,
 589                             struct pipe_fence_handle *src);
 590
 591     /**
 592      * Initialize surface
 593      *
 594      * \param ws        The winsys this function is called from.
 595      * \param tex       Input texture description
 596      * \param flags     Bitmask of RADEON_SURF_* flags
 597      * \param bpe       Bytes per pixel, it can be different for Z buffers.
 598      * \param mode      Preferred tile mode. (linear, 1D, or 2D)
 599      * \param surf      Output structure
 600      */
 601     int (*surface_init)(struct radeon_winsys *ws,
 602                         const struct pipe_resource *tex,
 603                         unsigned flags, unsigned bpe,
 604                         enum radeon_surf_mode mode,
 605                         struct radeon_surf *surf);
 606
 607     uint64_t (*query_value)(struct radeon_winsys *ws,
 608                             enum radeon_value_id value);
 609
 610     bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 611                            unsigned num_registers, uint32_t *out);
 612
 613     const char* (*get_chip_name)(struct radeon_winsys *ws);
 614 };
 615
 616 static inline bool radeon_emitted(struct radeon_winsys_cs *cs, unsigned num_dw)
 617 {
 618     return cs && (cs->prev_dw + cs->current.cdw > num_dw);
 619 }
 620
 621 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 622 {
 623     cs->current.buf[cs->current.cdw++] = value;
 624 }
 625
 626 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 627                                      const uint32_t *values, unsigned count)
 628 {
 629     memcpy(cs->current.buf + cs->current.cdw, values, count * 4);
 630     cs->current.cdw += count;
 631 }
 632
 633 enum radeon_heap {
 634     RADEON_HEAP_VRAM_NO_CPU_ACCESS,
 635     RADEON_HEAP_VRAM,
 636     RADEON_HEAP_VRAM_GTT, /* combined heaps */
 637     RADEON_HEAP_GTT_WC,
 638     RADEON_HEAP_GTT,
 639     RADEON_MAX_SLAB_HEAPS,
 640     RADEON_MAX_CACHED_HEAPS = RADEON_MAX_SLAB_HEAPS,
 641 };
 642
 643 static inline enum radeon_bo_domain radeon_domain_from_heap(enum radeon_heap heap)
 644 {
 645     switch (heap) {
 646     case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
 647     case RADEON_HEAP_VRAM:
 648         return RADEON_DOMAIN_VRAM;
 649     case RADEON_HEAP_VRAM_GTT:
 650         return RADEON_DOMAIN_VRAM_GTT;
 651     case RADEON_HEAP_GTT_WC:
 652     case RADEON_HEAP_GTT:
 653         return RADEON_DOMAIN_GTT;
 654     default:
 655         assert(0);
 656         return (enum radeon_bo_domain)0;
 657     }
 658 }
 659
 660 static inline unsigned radeon_flags_from_heap(enum radeon_heap heap)
 661 {
 662     switch (heap) {
 663     case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
 664         return RADEON_FLAG_GTT_WC | RADEON_FLAG_NO_CPU_ACCESS;
 665     case RADEON_HEAP_VRAM:
 666     case RADEON_HEAP_VRAM_GTT:
 667     case RADEON_HEAP_GTT_WC:
 668         return RADEON_FLAG_GTT_WC;
 669     case RADEON_HEAP_GTT:
 670     default:
 671         return 0;
 672     }
 673 }
 674
 675 /* The pb cache bucket is chosen to minimize pb_cache misses.
 676  * It must be between 0 and 3 inclusive.
 677  */
 678 static inline unsigned radeon_get_pb_cache_bucket_index(enum radeon_heap heap)
 679 {
 680     switch (heap) {
 681     case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
 682         return 0;
 683     case RADEON_HEAP_VRAM:
 684     case RADEON_HEAP_VRAM_GTT:
 685         return 1;
 686     case RADEON_HEAP_GTT_WC:
 687         return 2;
 688     case RADEON_HEAP_GTT:
 689     default:
 690         return 3;
 691     }
 692 }
 693
 694 /* Return the heap index for winsys allocators, or -1 on failure. */
 695 static inline int radeon_get_heap_index(enum radeon_bo_domain domain,
 696                                         enum radeon_bo_flag flags)
 697 {
 698     /* VRAM implies WC (write combining) */
 699     assert(!(domain & RADEON_DOMAIN_VRAM) || flags & RADEON_FLAG_GTT_WC);
 700     /* NO_CPU_ACCESS implies VRAM only. */
 701     assert(!(flags & RADEON_FLAG_NO_CPU_ACCESS) || domain == RADEON_DOMAIN_VRAM);
 702
 703     /* Unsupported flags: NO_SUBALLOC, SPARSE. */
 704     if (flags & ~(RADEON_FLAG_GTT_WC | RADEON_FLAG_NO_CPU_ACCESS))
 705         return -1;
 706
 707     switch (domain) {
 708     case RADEON_DOMAIN_VRAM:
 709         if (flags & RADEON_FLAG_NO_CPU_ACCESS)
 710             return RADEON_HEAP_VRAM_NO_CPU_ACCESS;
 711         else
 712             return RADEON_HEAP_VRAM;
 713     case RADEON_DOMAIN_VRAM_GTT:
 714         return RADEON_HEAP_VRAM_GTT;
 715     case RADEON_DOMAIN_GTT:
 716         if (flags & RADEON_FLAG_GTT_WC)
 717             return RADEON_HEAP_GTT_WC;
 718         else
 719             return RADEON_HEAP_GTT;
 720     }
 721     return -1;
 722 }
 723
 724 #endif