src/gallium/drivers/radeon/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #ifndef RADEON_WINSYS_H
  25 #define RADEON_WINSYS_H
  26
  27 /* The public winsys interface header for the radeon driver. */
  28
  29 #include "pipebuffer/pb_buffer.h"
  30
  31 #include "amd/common/amd_family.h"
  32 #include "amd/common/ac_surface.h"
  33
  34 #define RADEON_FLUSH_ASYNC              (1 << 0)
  35 #define RADEON_FLUSH_END_OF_FRAME       (1 << 1)
  36
  37 /* Tiling flags. */
  38 enum radeon_bo_layout {
  39     RADEON_LAYOUT_LINEAR = 0,
  40     RADEON_LAYOUT_TILED,
  41     RADEON_LAYOUT_SQUARETILED,
  42
  43     RADEON_LAYOUT_UNKNOWN
  44 };
  45
  46 enum radeon_bo_domain { /* bitfield */
  47     RADEON_DOMAIN_GTT  = 2,
  48     RADEON_DOMAIN_VRAM = 4,
  49     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  50 };
  51
  52 enum radeon_bo_flag { /* bitfield */
  53     RADEON_FLAG_GTT_WC =        (1 << 0),
  54     RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  55     RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  56     RADEON_FLAG_HANDLE =        (1 << 3), /* the buffer must not be suballocated */
  57     RADEON_FLAG_SPARSE =        (1 << 4),
  58 };
  59
  60 enum radeon_bo_usage { /* bitfield */
  61     RADEON_USAGE_READ = 2,
  62     RADEON_USAGE_WRITE = 4,
  63     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE,
  64
  65     /* The winsys ensures that the CS submission will be scheduled after
  66      * previously flushed CSs referencing this BO in a conflicting way.
  67      */
  68     RADEON_USAGE_SYNCHRONIZED = 8
  69 };
  70
  71 #define RADEON_SPARSE_PAGE_SIZE (64 * 1024)
  72
  73 enum ring_type {
  74     RING_GFX = 0,
  75     RING_COMPUTE,
  76     RING_DMA,
  77     RING_UVD,
  78     RING_VCE,
  79     RING_LAST,
  80 };
  81
  82 enum radeon_value_id {
  83     RADEON_REQUESTED_VRAM_MEMORY,
  84     RADEON_REQUESTED_GTT_MEMORY,
  85     RADEON_MAPPED_VRAM,
  86     RADEON_MAPPED_GTT,
  87     RADEON_BUFFER_WAIT_TIME_NS,
  88     RADEON_NUM_MAPPED_BUFFERS,
  89     RADEON_TIMESTAMP,
  90     RADEON_NUM_GFX_IBS,
  91     RADEON_NUM_SDMA_IBS,
  92     RADEON_NUM_BYTES_MOVED,
  93     RADEON_NUM_EVICTIONS,
  94     RADEON_VRAM_USAGE,
  95     RADEON_VRAM_VIS_USAGE,
  96     RADEON_GTT_USAGE,
  97     RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
  98     RADEON_CURRENT_SCLK,
  99     RADEON_CURRENT_MCLK,
 100     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
 101     RADEON_CS_THREAD_TIME,
 102 };
 103
 104 /* Each group of four has the same priority. */
 105 enum radeon_bo_priority {
 106     RADEON_PRIO_FENCE = 0,
 107     RADEON_PRIO_TRACE,
 108     RADEON_PRIO_SO_FILLED_SIZE,
 109     RADEON_PRIO_QUERY,
 110
 111     RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
 112     RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
 113     RADEON_PRIO_DRAW_INDIRECT,
 114     RADEON_PRIO_INDEX_BUFFER,
 115
 116     RADEON_PRIO_VCE = 8,
 117     RADEON_PRIO_UVD,
 118     RADEON_PRIO_SDMA_BUFFER,
 119     RADEON_PRIO_SDMA_TEXTURE,
 120
 121     RADEON_PRIO_CP_DMA = 12,
 122
 123     RADEON_PRIO_CONST_BUFFER = 16,
 124     RADEON_PRIO_DESCRIPTORS,
 125     RADEON_PRIO_BORDER_COLORS,
 126
 127     RADEON_PRIO_SAMPLER_BUFFER = 20,
 128     RADEON_PRIO_VERTEX_BUFFER,
 129
 130     RADEON_PRIO_SHADER_RW_BUFFER = 24,
 131     RADEON_PRIO_COMPUTE_GLOBAL,
 132
 133     RADEON_PRIO_SAMPLER_TEXTURE = 28,
 134     RADEON_PRIO_SHADER_RW_IMAGE,
 135
 136     RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 32,
 137
 138     RADEON_PRIO_COLOR_BUFFER = 36,
 139
 140     RADEON_PRIO_DEPTH_BUFFER = 40,
 141
 142     RADEON_PRIO_COLOR_BUFFER_MSAA = 44,
 143
 144     RADEON_PRIO_DEPTH_BUFFER_MSAA = 48,
 145
 146     RADEON_PRIO_CMASK = 52,
 147     RADEON_PRIO_DCC,
 148     RADEON_PRIO_HTILE,
 149     RADEON_PRIO_SHADER_BINARY, /* the hw can't hide instruction cache misses */
 150
 151     RADEON_PRIO_SHADER_RINGS = 56,
 152
 153     RADEON_PRIO_SCRATCH_BUFFER = 60,
 154     /* 63 is the maximum value */
 155 };
 156
 157 struct winsys_handle;
 158 struct radeon_winsys_ctx;
 159
 160 struct radeon_winsys_cs_chunk {
 161     unsigned cdw;  /* Number of used dwords. */
 162     unsigned max_dw; /* Maximum number of dwords. */
 163     uint32_t *buf; /* The base pointer of the chunk. */
 164 };
 165
 166 struct radeon_winsys_cs {
 167     struct radeon_winsys_cs_chunk current;
 168     struct radeon_winsys_cs_chunk *prev;
 169     unsigned                      num_prev; /* Number of previous chunks. */
 170     unsigned                      max_prev; /* Space in array pointed to by prev. */
 171     unsigned                      prev_dw; /* Total number of dwords in previous chunks. */
 172
 173     /* Memory usage of the buffer list. These are always 0 for CE and preamble
 174      * IBs. */
 175     uint64_t                      used_vram;
 176     uint64_t                      used_gart;
 177 };
 178
 179 struct radeon_info {
 180     /* PCI info: domain:bus:dev:func */
 181     uint32_t                    pci_domain;
 182     uint32_t                    pci_bus;
 183     uint32_t                    pci_dev;
 184     uint32_t                    pci_func;
 185
 186     /* Device info. */
 187     uint32_t                    pci_id;
 188     enum radeon_family          family;
 189     enum chip_class             chip_class;
 190     uint32_t                    gart_page_size;
 191     uint64_t                    gart_size;
 192     uint64_t                    vram_size;
 193     uint64_t                    vram_vis_size;
 194     uint64_t                    max_alloc_size;
 195     uint32_t                    min_alloc_size;
 196     bool                        has_dedicated_vram;
 197     bool                        has_virtual_memory;
 198     bool                        gfx_ib_pad_with_type2;
 199     bool                        has_sdma;
 200     bool                        has_uvd;
 201     uint32_t                    uvd_fw_version;
 202     uint32_t                    vce_fw_version;
 203     uint32_t                    me_fw_version;
 204     uint32_t                    pfp_fw_version;
 205     uint32_t                    ce_fw_version;
 206     uint32_t                    vce_harvest_config;
 207     uint32_t                    clock_crystal_freq;
 208     uint32_t                    tcc_cache_line_size;
 209
 210     /* Kernel info. */
 211     uint32_t                    drm_major; /* version */
 212     uint32_t                    drm_minor;
 213     uint32_t                    drm_patchlevel;
 214     bool                        has_userptr;
 215
 216     /* Shader cores. */
 217     uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
 218     uint32_t                    max_shader_clock;
 219     uint32_t                    num_good_compute_units;
 220     uint32_t                    max_se; /* shader engines */
 221     uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 222
 223     /* Render backends (color + depth blocks). */
 224     uint32_t                    r300_num_gb_pipes;
 225     uint32_t                    r300_num_z_pipes;
 226     uint32_t                    r600_gb_backend_map; /* R600 harvest config */
 227     bool                        r600_gb_backend_map_valid;
 228     uint32_t                    r600_num_banks;
 229     uint32_t                    num_render_backends;
 230     uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
 231     uint32_t                    pipe_interleave_bytes;
 232     uint32_t                    enabled_rb_mask; /* GCN harvest config */
 233
 234     /* Tile modes. */
 235     uint32_t                    si_tile_mode_array[32];
 236     uint32_t                    cik_macrotile_mode_array[16];
 237 };
 238
 239 /* Tiling info for display code, DRI sharing, and other data. */
 240 struct radeon_bo_metadata {
 241     /* Tiling flags describing the texture layout for display code
 242      * and DRI sharing.
 243      */
 244     union {
 245         struct {
 246             enum radeon_bo_layout   microtile;
 247             enum radeon_bo_layout   macrotile;
 248             unsigned                pipe_config;
 249             unsigned                bankw;
 250             unsigned                bankh;
 251             unsigned                tile_split;
 252             unsigned                mtilea;
 253             unsigned                num_banks;
 254             unsigned                stride;
 255             bool                    scanout;
 256         } legacy;
 257
 258         struct {
 259             /* surface flags */
 260             unsigned swizzle_mode:5;
 261         } gfx9;
 262     } u;
 263
 264     /* Additional metadata associated with the buffer, in bytes.
 265      * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 266      * Supported by amdgpu only.
 267      */
 268     uint32_t                size_metadata;
 269     uint32_t                metadata[64];
 270 };
 271
 272 enum radeon_feature_id {
 273     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 274     RADEON_FID_R300_CMASK_ACCESS,
 275 };
 276
 277 struct radeon_bo_list_item {
 278     uint64_t bo_size;
 279     uint64_t vm_address;
 280     uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
 281 };
 282
 283 struct radeon_winsys {
 284     /**
 285      * The screen object this winsys was created for
 286      */
 287     struct pipe_screen *screen;
 288
 289     /**
 290      * Decrement the winsys reference count.
 291      *
 292      * \param ws  The winsys this function is called for.
 293      * \return    True if the winsys and screen should be destroyed.
 294      */
 295     bool (*unref)(struct radeon_winsys *ws);
 296
 297     /**
 298      * Destroy this winsys.
 299      *
 300      * \param ws        The winsys this function is called from.
 301      */
 302     void (*destroy)(struct radeon_winsys *ws);
 303
 304     /**
 305      * Query an info structure from winsys.
 306      *
 307      * \param ws        The winsys this function is called from.
 308      * \param info      Return structure
 309      */
 310     void (*query_info)(struct radeon_winsys *ws,
 311                        struct radeon_info *info);
 312
 313     /**************************************************************************
 314      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 315      *
 316      * Remember that gallium gets to choose the interface it needs, and the
 317      * window systems must then implement that interface (rather than the
 318      * other way around...).
 319      *************************************************************************/
 320
 321     /**
 322      * Create a buffer object.
 323      *
 324      * \param ws        The winsys this function is called from.
 325      * \param size      The size to allocate.
 326      * \param alignment An alignment of the buffer in memory.
 327      * \param use_reusable_pool Whether the cache buffer manager should be used.
 328      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 329      * \return          The created buffer object.
 330      */
 331     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 332                                        uint64_t size,
 333                                        unsigned alignment,
 334                                        enum radeon_bo_domain domain,
 335                                        enum radeon_bo_flag flags);
 336
 337     /**
 338      * Map the entire data store of a buffer object into the client's address
 339      * space.
 340      *
 341      * \param buf       A winsys buffer object to map.
 342      * \param cs        A command stream to flush if the buffer is referenced by it.
 343      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 344      * \return          The pointer at the beginning of the buffer.
 345      */
 346     void *(*buffer_map)(struct pb_buffer *buf,
 347                         struct radeon_winsys_cs *cs,
 348                         enum pipe_transfer_usage usage);
 349
 350     /**
 351      * Unmap a buffer object from the client's address space.
 352      *
 353      * \param buf       A winsys buffer object to unmap.
 354      */
 355     void (*buffer_unmap)(struct pb_buffer *buf);
 356
 357     /**
 358      * Wait for the buffer and return true if the buffer is not used
 359      * by the device.
 360      *
 361      * The timeout of 0 will only return the status.
 362      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
 363      * is idle.
 364      */
 365     bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
 366                         enum radeon_bo_usage usage);
 367
 368     /**
 369      * Return buffer metadata.
 370      * (tiling info for display code, DRI sharing, and other data)
 371      *
 372      * \param buf       A winsys buffer object to get the flags from.
 373      * \param md        Metadata
 374      */
 375     void (*buffer_get_metadata)(struct pb_buffer *buf,
 376                                 struct radeon_bo_metadata *md);
 377
 378     /**
 379      * Set buffer metadata.
 380      * (tiling info for display code, DRI sharing, and other data)
 381      *
 382      * \param buf       A winsys buffer object to set the flags for.
 383      * \param md        Metadata
 384      */
 385     void (*buffer_set_metadata)(struct pb_buffer *buf,
 386                                 struct radeon_bo_metadata *md);
 387
 388     /**
 389      * Get a winsys buffer from a winsys handle. The internal structure
 390      * of the handle is platform-specific and only a winsys should access it.
 391      *
 392      * \param ws        The winsys this function is called from.
 393      * \param whandle   A winsys handle pointer as was received from a state
 394      *                  tracker.
 395      * \param stride    The returned buffer stride in bytes.
 396      */
 397     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 398                                             struct winsys_handle *whandle,
 399                                             unsigned *stride, unsigned *offset);
 400
 401     /**
 402      * Get a winsys buffer from a user pointer. The resulting buffer can't
 403      * be exported. Both pointer and size must be page aligned.
 404      *
 405      * \param ws        The winsys this function is called from.
 406      * \param pointer   User pointer to turn into a buffer object.
 407      * \param Size      Size in bytes for the new buffer.
 408      */
 409     struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
 410                                          void *pointer, uint64_t size);
 411
 412     /**
 413      * Whether the buffer was created from a user pointer.
 414      *
 415      * \param buf       A winsys buffer object
 416      * \return          whether \p buf was created via buffer_from_ptr
 417      */
 418     bool (*buffer_is_user_ptr)(struct pb_buffer *buf);
 419
 420     /**
 421      * Get a winsys handle from a winsys buffer. The internal structure
 422      * of the handle is platform-specific and only a winsys should access it.
 423      *
 424      * \param buf       A winsys buffer object to get the handle from.
 425      * \param whandle   A winsys handle pointer.
 426      * \param stride    A stride of the buffer in bytes, for texturing.
 427      * \return          true on success.
 428      */
 429     bool (*buffer_get_handle)(struct pb_buffer *buf,
 430                               unsigned stride, unsigned offset,
 431                               unsigned slice_size,
 432                               struct winsys_handle *whandle);
 433
 434     /**
 435      * Change the commitment of a (64KB-page aligned) region of the given
 436      * sparse buffer.
 437      *
 438      * \warning There is no automatic synchronization with command submission.
 439      *
 440      * \note Only implemented by the amdgpu winsys.
 441      *
 442      * \return false on out of memory or other failure, true on success.
 443      */
 444     bool (*buffer_commit)(struct pb_buffer *buf,
 445                           uint64_t offset, uint64_t size,
 446                           bool commit);
 447
 448     /**
 449      * Return the virtual address of a buffer.
 450      *
 451      * When virtual memory is not in use, this is the offset relative to the
 452      * relocation base (non-zero for sub-allocated buffers).
 453      *
 454      * \param buf       A winsys buffer object
 455      * \return          virtual address
 456      */
 457     uint64_t (*buffer_get_virtual_address)(struct pb_buffer *buf);
 458
 459     /**
 460      * Return the offset of this buffer relative to the relocation base.
 461      * This is only non-zero for sub-allocated buffers.
 462      *
 463      * This is only supported in the radeon winsys, since amdgpu uses virtual
 464      * addresses in submissions even for the video engines.
 465      *
 466      * \param buf      A winsys buffer object
 467      * \return         the offset for relocations
 468      */
 469     unsigned (*buffer_get_reloc_offset)(struct pb_buffer *buf);
 470
 471     /**
 472      * Query the initial placement of the buffer from the kernel driver.
 473      */
 474     enum radeon_bo_domain (*buffer_get_initial_domain)(struct pb_buffer *buf);
 475
 476     /**************************************************************************
 477      * Command submission.
 478      *
 479      * Each pipe context should create its own command stream and submit
 480      * commands independently of other contexts.
 481      *************************************************************************/
 482
 483     /**
 484      * Create a command submission context.
 485      * Various command streams can be submitted to the same context.
 486      */
 487     struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 488
 489     /**
 490      * Destroy a context.
 491      */
 492     void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 493
 494     /**
 495      * Query a GPU reset status.
 496      */
 497     enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
 498
 499     /**
 500      * Create a command stream.
 501      *
 502      * \param ctx       The submission context
 503      * \param ring_type The ring type (GFX, DMA, UVD)
 504      * \param flush     Flush callback function associated with the command stream.
 505      * \param user      User pointer that will be passed to the flush callback.
 506      */
 507     struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys_ctx *ctx,
 508                                           enum ring_type ring_type,
 509                                           void (*flush)(void *ctx, unsigned flags,
 510                                                         struct pipe_fence_handle **fence),
 511                                           void *flush_ctx);
 512
 513     /**
 514      * Add a constant engine IB to a graphics CS. This makes the graphics CS
 515      * from "cs_create" a group of two IBs that share a buffer list and are
 516      * flushed together.
 517      *
 518      * The returned constant CS is only a stream for writing packets to the new
 519      * IB. Calling other winsys functions with it is not allowed, not even
 520      * "cs_destroy".
 521      *
 522      * In order to add buffers and check memory usage, use the graphics CS.
 523      * In order to flush it, use the graphics CS, which will flush both IBs.
 524      * Destroying the graphics CS will destroy both of them.
 525      *
 526      * \param cs  The graphics CS from "cs_create" that will hold the buffer
 527      *            list and will be used for flushing.
 528      */
 529     struct radeon_winsys_cs *(*cs_add_const_ib)(struct radeon_winsys_cs *cs);
 530
 531      /**
 532      * Add a constant engine preamble IB to a graphics CS. This add an extra IB
 533      * in similar manner to cs_add_const_ib. This should always be called after
 534      * cs_add_const_ib.
 535      *
 536      * The returned IB is a constant engine IB that only gets flushed if the
 537      * context changed.
 538      *
 539      * \param cs  The graphics CS from "cs_create" that will hold the buffer
 540      *            list and will be used for flushing.
 541      */
 542     struct radeon_winsys_cs *(*cs_add_const_preamble_ib)(struct radeon_winsys_cs *cs);
 543     /**
 544      * Destroy a command stream.
 545      *
 546      * \param cs        A command stream to destroy.
 547      */
 548     void (*cs_destroy)(struct radeon_winsys_cs *cs);
 549
 550     /**
 551      * Add a buffer. Each buffer used by a CS must be added using this function.
 552      *
 553      * \param cs      Command stream
 554      * \param buf     Buffer
 555      * \param usage   Whether the buffer is used for read and/or write.
 556      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 557      * \param priority  A higher number means a greater chance of being
 558      *                  placed in the requested domain. 15 is the maximum.
 559      * \return Buffer index.
 560      */
 561     unsigned (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 562                              struct pb_buffer *buf,
 563                              enum radeon_bo_usage usage,
 564                              enum radeon_bo_domain domain,
 565                              enum radeon_bo_priority priority);
 566
 567     /**
 568      * Return the index of an already-added buffer.
 569      *
 570      * Not supported on amdgpu. Drivers with GPUVM should not care about
 571      * buffer indices.
 572      *
 573      * \param cs        Command stream
 574      * \param buf       Buffer
 575      * \return          The buffer index, or -1 if the buffer has not been added.
 576      */
 577     int (*cs_lookup_buffer)(struct radeon_winsys_cs *cs,
 578                             struct pb_buffer *buf);
 579
 580     /**
 581      * Return true if there is enough memory in VRAM and GTT for the buffers
 582      * added so far. If the validation fails, all buffers which have
 583      * been added since the last call of cs_validate will be removed and
 584      * the CS will be flushed (provided there are still any buffers).
 585      *
 586      * \param cs        A command stream to validate.
 587      */
 588     bool (*cs_validate)(struct radeon_winsys_cs *cs);
 589
 590     /**
 591      * Check whether the given number of dwords is available in the IB.
 592      * Optionally chain a new chunk of the IB if necessary and supported.
 593      *
 594      * \param cs        A command stream.
 595      * \param dw        Number of CS dwords requested by the caller.
 596      */
 597     bool (*cs_check_space)(struct radeon_winsys_cs *cs, unsigned dw);
 598
 599     /**
 600      * Return the buffer list.
 601      *
 602      * This is the buffer list as passed to the kernel, i.e. it only contains
 603      * the parent buffers of sub-allocated buffers.
 604      *
 605      * \param cs    Command stream
 606      * \param list  Returned buffer list. Set to NULL to query the count only.
 607      * \return      The buffer count.
 608      */
 609     unsigned (*cs_get_buffer_list)(struct radeon_winsys_cs *cs,
 610                                    struct radeon_bo_list_item *list);
 611
 612     /**
 613      * Flush a command stream.
 614      *
 615      * \param cs          A command stream to flush.
 616      * \param flags,      RADEON_FLUSH_ASYNC or 0.
 617      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 618      *                    after the CS and is returned through this parameter.
 619      * \return Negative POSIX error code or 0 for success.
 620      *         Asynchronous submissions never return an error.
 621      */
 622     int (*cs_flush)(struct radeon_winsys_cs *cs,
 623                     unsigned flags,
 624                     struct pipe_fence_handle **fence);
 625
 626     /**
 627      * Create a fence before the CS is flushed.
 628      * The user must flush manually to complete the initializaton of the fence.
 629      * The fence must not be used before the flush.
 630      */
 631     struct pipe_fence_handle *(*cs_get_next_fence)(struct radeon_winsys_cs *cs);
 632
 633     /**
 634      * Return true if a buffer is referenced by a command stream.
 635      *
 636      * \param cs        A command stream.
 637      * \param buf       A winsys buffer.
 638      */
 639     bool (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
 640                                     struct pb_buffer *buf,
 641                                     enum radeon_bo_usage usage);
 642
 643     /**
 644      * Request access to a feature for a command stream.
 645      *
 646      * \param cs        A command stream.
 647      * \param fid       Feature ID, one of RADEON_FID_*
 648      * \param enable    Whether to enable or disable the feature.
 649      */
 650     bool (*cs_request_feature)(struct radeon_winsys_cs *cs,
 651                                enum radeon_feature_id fid,
 652                                bool enable);
 653      /**
 654       * Make sure all asynchronous flush of the cs have completed
 655       *
 656       * \param cs        A command stream.
 657       */
 658     void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
 659
 660     /**
 661      * Wait for the fence and return true if the fence has been signalled.
 662      * The timeout of 0 will only return the status.
 663      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 664      * is signalled.
 665      */
 666     bool (*fence_wait)(struct radeon_winsys *ws,
 667                        struct pipe_fence_handle *fence,
 668                        uint64_t timeout);
 669
 670     /**
 671      * Reference counting for fences.
 672      */
 673     void (*fence_reference)(struct pipe_fence_handle **dst,
 674                             struct pipe_fence_handle *src);
 675
 676     /**
 677      * Initialize surface
 678      *
 679      * \param ws        The winsys this function is called from.
 680      * \param tex       Input texture description
 681      * \param flags     Bitmask of RADEON_SURF_* flags
 682      * \param bpe       Bytes per pixel, it can be different for Z buffers.
 683      * \param mode      Preferred tile mode. (linear, 1D, or 2D)
 684      * \param surf      Output structure
 685      */
 686     int (*surface_init)(struct radeon_winsys *ws,
 687                         const struct pipe_resource *tex,
 688                         unsigned flags, unsigned bpe,
 689                         enum radeon_surf_mode mode,
 690                         struct radeon_surf *surf);
 691
 692     uint64_t (*query_value)(struct radeon_winsys *ws,
 693                             enum radeon_value_id value);
 694
 695     bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 696                            unsigned num_registers, uint32_t *out);
 697 };
 698
 699 static inline bool radeon_emitted(struct radeon_winsys_cs *cs, unsigned num_dw)
 700 {
 701     return cs && (cs->prev_dw + cs->current.cdw > num_dw);
 702 }
 703
 704 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 705 {
 706     cs->current.buf[cs->current.cdw++] = value;
 707 }
 708
 709 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 710                                      const uint32_t *values, unsigned count)
 711 {
 712     memcpy(cs->current.buf + cs->current.cdw, values, count * 4);
 713     cs->current.cdw += count;
 714 }
 715
 716 #endif