src/gallium/drivers/radeon/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #ifndef RADEON_WINSYS_H
  25 #define RADEON_WINSYS_H
  26
  27 /* The public winsys interface header for the radeon driver. */
  28
  29 #include "pipebuffer/pb_buffer.h"
  30
  31 #include "amd/common/amd_family.h"
  32
  33 #define RADEON_FLUSH_ASYNC              (1 << 0)
  34 #define RADEON_FLUSH_END_OF_FRAME       (1 << 1)
  35
  36 /* Tiling flags. */
  37 enum radeon_bo_layout {
  38     RADEON_LAYOUT_LINEAR = 0,
  39     RADEON_LAYOUT_TILED,
  40     RADEON_LAYOUT_SQUARETILED,
  41
  42     RADEON_LAYOUT_UNKNOWN
  43 };
  44
  45 enum radeon_bo_domain { /* bitfield */
  46     RADEON_DOMAIN_GTT  = 2,
  47     RADEON_DOMAIN_VRAM = 4,
  48     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  49 };
  50
  51 enum radeon_bo_flag { /* bitfield */
  52     RADEON_FLAG_GTT_WC =        (1 << 0),
  53     RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  54     RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  55 };
  56
  57 enum radeon_bo_usage { /* bitfield */
  58     RADEON_USAGE_READ = 2,
  59     RADEON_USAGE_WRITE = 4,
  60     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
  61 };
  62
  63 enum ring_type {
  64     RING_GFX = 0,
  65     RING_COMPUTE,
  66     RING_DMA,
  67     RING_UVD,
  68     RING_VCE,
  69     RING_LAST,
  70 };
  71
  72 enum radeon_value_id {
  73     RADEON_REQUESTED_VRAM_MEMORY,
  74     RADEON_REQUESTED_GTT_MEMORY,
  75     RADEON_MAPPED_VRAM,
  76     RADEON_MAPPED_GTT,
  77     RADEON_BUFFER_WAIT_TIME_NS,
  78     RADEON_TIMESTAMP,
  79     RADEON_NUM_CS_FLUSHES,
  80     RADEON_NUM_BYTES_MOVED,
  81     RADEON_NUM_EVICTIONS,
  82     RADEON_VRAM_USAGE,
  83     RADEON_GTT_USAGE,
  84     RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
  85     RADEON_CURRENT_SCLK,
  86     RADEON_CURRENT_MCLK,
  87     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
  88 };
  89
  90 /* Each group of four has the same priority. */
  91 enum radeon_bo_priority {
  92     RADEON_PRIO_FENCE = 0,
  93     RADEON_PRIO_TRACE,
  94     RADEON_PRIO_SO_FILLED_SIZE,
  95     RADEON_PRIO_QUERY,
  96
  97     RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
  98     RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
  99     RADEON_PRIO_DRAW_INDIRECT,
 100     RADEON_PRIO_INDEX_BUFFER,
 101
 102     RADEON_PRIO_VCE = 8,
 103     RADEON_PRIO_UVD,
 104     RADEON_PRIO_SDMA_BUFFER,
 105     RADEON_PRIO_SDMA_TEXTURE,
 106
 107     RADEON_PRIO_CP_DMA = 12,
 108
 109     RADEON_PRIO_CONST_BUFFER = 16,
 110     RADEON_PRIO_DESCRIPTORS,
 111     RADEON_PRIO_BORDER_COLORS,
 112
 113     RADEON_PRIO_SAMPLER_BUFFER = 20,
 114     RADEON_PRIO_VERTEX_BUFFER,
 115
 116     RADEON_PRIO_SHADER_RW_BUFFER = 24,
 117     RADEON_PRIO_COMPUTE_GLOBAL,
 118
 119     RADEON_PRIO_SAMPLER_TEXTURE = 28,
 120     RADEON_PRIO_SHADER_RW_IMAGE,
 121
 122     RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 32,
 123
 124     RADEON_PRIO_COLOR_BUFFER = 36,
 125
 126     RADEON_PRIO_DEPTH_BUFFER = 40,
 127
 128     RADEON_PRIO_COLOR_BUFFER_MSAA = 44,
 129
 130     RADEON_PRIO_DEPTH_BUFFER_MSAA = 48,
 131
 132     RADEON_PRIO_CMASK = 52,
 133     RADEON_PRIO_DCC,
 134     RADEON_PRIO_HTILE,
 135     RADEON_PRIO_SHADER_BINARY, /* the hw can't hide instruction cache misses */
 136
 137     RADEON_PRIO_SHADER_RINGS = 56,
 138
 139     RADEON_PRIO_SCRATCH_BUFFER = 60,
 140     /* 63 is the maximum value */
 141 };
 142
 143 struct winsys_handle;
 144 struct radeon_winsys_ctx;
 145
 146 struct radeon_winsys_cs_chunk {
 147     unsigned cdw;  /* Number of used dwords. */
 148     unsigned max_dw; /* Maximum number of dwords. */
 149     uint32_t *buf; /* The base pointer of the chunk. */
 150 };
 151
 152 struct radeon_winsys_cs {
 153     struct radeon_winsys_cs_chunk current;
 154     struct radeon_winsys_cs_chunk *prev;
 155     unsigned                      num_prev; /* Number of previous chunks. */
 156     unsigned                      max_prev; /* Space in array pointed to by prev. */
 157     unsigned                      prev_dw; /* Total number of dwords in previous chunks. */
 158
 159     /* Memory usage of the buffer list. These are always 0 for CE and preamble
 160      * IBs. */
 161     uint64_t                      used_vram;
 162     uint64_t                      used_gart;
 163 };
 164
 165 struct radeon_info {
 166     /* PCI info: domain:bus:dev:func */
 167     uint32_t                    pci_domain;
 168     uint32_t                    pci_bus;
 169     uint32_t                    pci_dev;
 170     uint32_t                    pci_func;
 171
 172     /* Device info. */
 173     uint32_t                    pci_id;
 174     enum radeon_family          family;
 175     enum chip_class             chip_class;
 176     uint32_t                    gart_page_size;
 177     uint64_t                    gart_size;
 178     uint64_t                    vram_size;
 179     uint64_t                    max_alloc_size;
 180     bool                        has_dedicated_vram;
 181     bool                        has_virtual_memory;
 182     bool                        gfx_ib_pad_with_type2;
 183     bool                        has_sdma;
 184     bool                        has_uvd;
 185     uint32_t                    uvd_fw_version;
 186     uint32_t                    vce_fw_version;
 187     uint32_t                    me_fw_version;
 188     uint32_t                    pfp_fw_version;
 189     uint32_t                    ce_fw_version;
 190     uint32_t                    vce_harvest_config;
 191     uint32_t                    clock_crystal_freq;
 192
 193     /* Kernel info. */
 194     uint32_t                    drm_major; /* version */
 195     uint32_t                    drm_minor;
 196     uint32_t                    drm_patchlevel;
 197     bool                        has_userptr;
 198
 199     /* Shader cores. */
 200     uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
 201     uint32_t                    max_shader_clock;
 202     uint32_t                    num_good_compute_units;
 203     uint32_t                    max_se; /* shader engines */
 204     uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 205
 206     /* Render backends (color + depth blocks). */
 207     uint32_t                    r300_num_gb_pipes;
 208     uint32_t                    r300_num_z_pipes;
 209     uint32_t                    r600_gb_backend_map; /* R600 harvest config */
 210     bool                        r600_gb_backend_map_valid;
 211     uint32_t                    r600_num_banks;
 212     uint32_t                    num_render_backends;
 213     uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
 214     uint32_t                    pipe_interleave_bytes;
 215     uint32_t                    enabled_rb_mask; /* GCN harvest config */
 216
 217     /* Tile modes. */
 218     uint32_t                    si_tile_mode_array[32];
 219     uint32_t                    cik_macrotile_mode_array[16];
 220 };
 221
 222 /* Tiling info for display code, DRI sharing, and other data. */
 223 struct radeon_bo_metadata {
 224     /* Tiling flags describing the texture layout for display code
 225      * and DRI sharing.
 226      */
 227     enum radeon_bo_layout   microtile;
 228     enum radeon_bo_layout   macrotile;
 229     unsigned                pipe_config;
 230     unsigned                bankw;
 231     unsigned                bankh;
 232     unsigned                tile_split;
 233     unsigned                mtilea;
 234     unsigned                num_banks;
 235     unsigned                stride;
 236     bool                    scanout;
 237
 238     /* Additional metadata associated with the buffer, in bytes.
 239      * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 240      * Supported by amdgpu only.
 241      */
 242     uint32_t                size_metadata;
 243     uint32_t                metadata[64];
 244 };
 245
 246 enum radeon_feature_id {
 247     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 248     RADEON_FID_R300_CMASK_ACCESS,
 249 };
 250
 251 #define RADEON_SURF_MAX_LEVEL                   32
 252
 253 #define RADEON_SURF_TYPE_MASK                   0xFF
 254 #define RADEON_SURF_TYPE_SHIFT                  0
 255 #define     RADEON_SURF_TYPE_1D                     0
 256 #define     RADEON_SURF_TYPE_2D                     1
 257 #define     RADEON_SURF_TYPE_3D                     2
 258 #define     RADEON_SURF_TYPE_CUBEMAP                3
 259 #define     RADEON_SURF_TYPE_1D_ARRAY               4
 260 #define     RADEON_SURF_TYPE_2D_ARRAY               5
 261 #define RADEON_SURF_MODE_MASK                   0xFF
 262 #define RADEON_SURF_MODE_SHIFT                  8
 263 #define     RADEON_SURF_MODE_LINEAR_ALIGNED         1
 264 #define     RADEON_SURF_MODE_1D                     2
 265 #define     RADEON_SURF_MODE_2D                     3
 266 #define RADEON_SURF_SCANOUT                     (1 << 16)
 267 #define RADEON_SURF_ZBUFFER                     (1 << 17)
 268 #define RADEON_SURF_SBUFFER                     (1 << 18)
 269 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
 270 #define RADEON_SURF_HAS_SBUFFER_MIPTREE         (1 << 19)
 271 #define RADEON_SURF_HAS_TILE_MODE_INDEX         (1 << 20)
 272 #define RADEON_SURF_FMASK                       (1 << 21)
 273 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
 274
 275 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
 276 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
 277 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
 278
 279 struct radeon_surf_level {
 280     uint64_t                    offset;
 281     uint64_t                    slice_size;
 282     uint32_t                    npix_x;
 283     uint32_t                    npix_y;
 284     uint32_t                    npix_z;
 285     uint32_t                    nblk_x;
 286     uint32_t                    nblk_y;
 287     uint32_t                    nblk_z;
 288     uint32_t                    pitch_bytes;
 289     uint32_t                    mode;
 290     uint64_t                    dcc_offset;
 291     uint64_t                    dcc_fast_clear_size;
 292     bool                        dcc_enabled;
 293 };
 294
 295 struct radeon_surf {
 296     /* These are inputs to the calculator. */
 297     uint32_t                    npix_x;
 298     uint32_t                    npix_y;
 299     uint32_t                    npix_z;
 300     uint32_t                    blk_w;
 301     uint32_t                    blk_h;
 302     uint32_t                    blk_d;
 303     uint32_t                    array_size;
 304     uint32_t                    last_level;
 305     uint32_t                    bpe;
 306     uint32_t                    nsamples;
 307     uint32_t                    flags;
 308
 309     /* These are return values. Some of them can be set by the caller, but
 310      * they will be treated as hints (e.g. bankw, bankh) and might be
 311      * changed by the calculator.
 312      */
 313     uint64_t                    bo_size;
 314     uint64_t                    bo_alignment;
 315     /* This applies to EG and later. */
 316     uint32_t                    bankw;
 317     uint32_t                    bankh;
 318     uint32_t                    mtilea;
 319     uint32_t                    tile_split;
 320     uint32_t                    stencil_tile_split;
 321     struct radeon_surf_level    level[RADEON_SURF_MAX_LEVEL];
 322     struct radeon_surf_level    stencil_level[RADEON_SURF_MAX_LEVEL];
 323     uint32_t                    tiling_index[RADEON_SURF_MAX_LEVEL];
 324     uint32_t                    stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
 325     uint32_t                    pipe_config;
 326     uint32_t                    num_banks;
 327     uint32_t                    macro_tile_index;
 328     uint32_t                    micro_tile_mode; /* displayable, thin, depth, rotated */
 329
 330     /* Whether the depth miptree or stencil miptree as used by the DB are
 331      * adjusted from their TC compatible form to ensure depth/stencil
 332      * compatibility. If either is true, the corresponding plane cannot be
 333      * sampled from.
 334      */
 335     bool                        depth_adjusted;
 336     bool                        stencil_adjusted;
 337
 338     uint64_t                    dcc_size;
 339     uint64_t                    dcc_alignment;
 340 };
 341
 342 struct radeon_bo_list_item {
 343     uint64_t bo_size;
 344     uint64_t vm_address;
 345     uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
 346 };
 347
 348 struct radeon_winsys {
 349     /**
 350      * The screen object this winsys was created for
 351      */
 352     struct pipe_screen *screen;
 353
 354     /**
 355      * Decrement the winsys reference count.
 356      *
 357      * \param ws  The winsys this function is called for.
 358      * \return    True if the winsys and screen should be destroyed.
 359      */
 360     bool (*unref)(struct radeon_winsys *ws);
 361
 362     /**
 363      * Destroy this winsys.
 364      *
 365      * \param ws        The winsys this function is called from.
 366      */
 367     void (*destroy)(struct radeon_winsys *ws);
 368
 369     /**
 370      * Query an info structure from winsys.
 371      *
 372      * \param ws        The winsys this function is called from.
 373      * \param info      Return structure
 374      */
 375     void (*query_info)(struct radeon_winsys *ws,
 376                        struct radeon_info *info);
 377
 378     /**************************************************************************
 379      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 380      *
 381      * Remember that gallium gets to choose the interface it needs, and the
 382      * window systems must then implement that interface (rather than the
 383      * other way around...).
 384      *************************************************************************/
 385
 386     /**
 387      * Create a buffer object.
 388      *
 389      * \param ws        The winsys this function is called from.
 390      * \param size      The size to allocate.
 391      * \param alignment An alignment of the buffer in memory.
 392      * \param use_reusable_pool Whether the cache buffer manager should be used.
 393      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 394      * \return          The created buffer object.
 395      */
 396     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 397                                        uint64_t size,
 398                                        unsigned alignment,
 399                                        enum radeon_bo_domain domain,
 400                                        enum radeon_bo_flag flags);
 401
 402     /**
 403      * Map the entire data store of a buffer object into the client's address
 404      * space.
 405      *
 406      * \param buf       A winsys buffer object to map.
 407      * \param cs        A command stream to flush if the buffer is referenced by it.
 408      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 409      * \return          The pointer at the beginning of the buffer.
 410      */
 411     void *(*buffer_map)(struct pb_buffer *buf,
 412                         struct radeon_winsys_cs *cs,
 413                         enum pipe_transfer_usage usage);
 414
 415     /**
 416      * Unmap a buffer object from the client's address space.
 417      *
 418      * \param buf       A winsys buffer object to unmap.
 419      */
 420     void (*buffer_unmap)(struct pb_buffer *buf);
 421
 422     /**
 423      * Wait for the buffer and return true if the buffer is not used
 424      * by the device.
 425      *
 426      * The timeout of 0 will only return the status.
 427      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
 428      * is idle.
 429      */
 430     bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
 431                         enum radeon_bo_usage usage);
 432
 433     /**
 434      * Return buffer metadata.
 435      * (tiling info for display code, DRI sharing, and other data)
 436      *
 437      * \param buf       A winsys buffer object to get the flags from.
 438      * \param md        Metadata
 439      */
 440     void (*buffer_get_metadata)(struct pb_buffer *buf,
 441                                 struct radeon_bo_metadata *md);
 442
 443     /**
 444      * Set buffer metadata.
 445      * (tiling info for display code, DRI sharing, and other data)
 446      *
 447      * \param buf       A winsys buffer object to set the flags for.
 448      * \param md        Metadata
 449      */
 450     void (*buffer_set_metadata)(struct pb_buffer *buf,
 451                                 struct radeon_bo_metadata *md);
 452
 453     /**
 454      * Get a winsys buffer from a winsys handle. The internal structure
 455      * of the handle is platform-specific and only a winsys should access it.
 456      *
 457      * \param ws        The winsys this function is called from.
 458      * \param whandle   A winsys handle pointer as was received from a state
 459      *                  tracker.
 460      * \param stride    The returned buffer stride in bytes.
 461      */
 462     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 463                                             struct winsys_handle *whandle,
 464                                             unsigned *stride, unsigned *offset);
 465
 466     /**
 467      * Get a winsys buffer from a user pointer. The resulting buffer can't
 468      * be exported. Both pointer and size must be page aligned.
 469      *
 470      * \param ws        The winsys this function is called from.
 471      * \param pointer   User pointer to turn into a buffer object.
 472      * \param Size      Size in bytes for the new buffer.
 473      */
 474     struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
 475                                          void *pointer, uint64_t size);
 476
 477     /**
 478      * Whether the buffer was created from a user pointer.
 479      *
 480      * \param buf       A winsys buffer object
 481      * \return          whether \p buf was created via buffer_from_ptr
 482      */
 483     bool (*buffer_is_user_ptr)(struct pb_buffer *buf);
 484
 485     /**
 486      * Get a winsys handle from a winsys buffer. The internal structure
 487      * of the handle is platform-specific and only a winsys should access it.
 488      *
 489      * \param buf       A winsys buffer object to get the handle from.
 490      * \param whandle   A winsys handle pointer.
 491      * \param stride    A stride of the buffer in bytes, for texturing.
 492      * \return          true on success.
 493      */
 494     bool (*buffer_get_handle)(struct pb_buffer *buf,
 495                               unsigned stride, unsigned offset,
 496                               unsigned slice_size,
 497                               struct winsys_handle *whandle);
 498
 499     /**
 500      * Return the virtual address of a buffer.
 501      *
 502      * \param buf       A winsys buffer object
 503      * \return          virtual address
 504      */
 505     uint64_t (*buffer_get_virtual_address)(struct pb_buffer *buf);
 506
 507     /**
 508      * Query the initial placement of the buffer from the kernel driver.
 509      */
 510     enum radeon_bo_domain (*buffer_get_initial_domain)(struct pb_buffer *buf);
 511
 512     /**************************************************************************
 513      * Command submission.
 514      *
 515      * Each pipe context should create its own command stream and submit
 516      * commands independently of other contexts.
 517      *************************************************************************/
 518
 519     /**
 520      * Create a command submission context.
 521      * Various command streams can be submitted to the same context.
 522      */
 523     struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 524
 525     /**
 526      * Destroy a context.
 527      */
 528     void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 529
 530     /**
 531      * Query a GPU reset status.
 532      */
 533     enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
 534
 535     /**
 536      * Create a command stream.
 537      *
 538      * \param ctx       The submission context
 539      * \param ring_type The ring type (GFX, DMA, UVD)
 540      * \param flush     Flush callback function associated with the command stream.
 541      * \param user      User pointer that will be passed to the flush callback.
 542      */
 543     struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys_ctx *ctx,
 544                                           enum ring_type ring_type,
 545                                           void (*flush)(void *ctx, unsigned flags,
 546                                                         struct pipe_fence_handle **fence),
 547                                           void *flush_ctx);
 548
 549     /**
 550      * Add a constant engine IB to a graphics CS. This makes the graphics CS
 551      * from "cs_create" a group of two IBs that share a buffer list and are
 552      * flushed together.
 553      *
 554      * The returned constant CS is only a stream for writing packets to the new
 555      * IB. Calling other winsys functions with it is not allowed, not even
 556      * "cs_destroy".
 557      *
 558      * In order to add buffers and check memory usage, use the graphics CS.
 559      * In order to flush it, use the graphics CS, which will flush both IBs.
 560      * Destroying the graphics CS will destroy both of them.
 561      *
 562      * \param cs  The graphics CS from "cs_create" that will hold the buffer
 563      *            list and will be used for flushing.
 564      */
 565     struct radeon_winsys_cs *(*cs_add_const_ib)(struct radeon_winsys_cs *cs);
 566
 567      /**
 568      * Add a constant engine preamble IB to a graphics CS. This add an extra IB
 569      * in similar manner to cs_add_const_ib. This should always be called after
 570      * cs_add_const_ib.
 571      *
 572      * The returned IB is a constant engine IB that only gets flushed if the
 573      * context changed.
 574      *
 575      * \param cs  The graphics CS from "cs_create" that will hold the buffer
 576      *            list and will be used for flushing.
 577      */
 578     struct radeon_winsys_cs *(*cs_add_const_preamble_ib)(struct radeon_winsys_cs *cs);
 579     /**
 580      * Destroy a command stream.
 581      *
 582      * \param cs        A command stream to destroy.
 583      */
 584     void (*cs_destroy)(struct radeon_winsys_cs *cs);
 585
 586     /**
 587      * Add a buffer. Each buffer used by a CS must be added using this function.
 588      *
 589      * \param cs      Command stream
 590      * \param buf     Buffer
 591      * \param usage   Whether the buffer is used for read and/or write.
 592      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 593      * \param priority  A higher number means a greater chance of being
 594      *                  placed in the requested domain. 15 is the maximum.
 595      * \return Buffer index.
 596      */
 597     unsigned (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 598                              struct pb_buffer *buf,
 599                              enum radeon_bo_usage usage,
 600                              enum radeon_bo_domain domain,
 601                              enum radeon_bo_priority priority);
 602
 603     /**
 604      * Return the index of an already-added buffer.
 605      *
 606      * Not supported on amdgpu. Drivers with GPUVM should not care about
 607      * buffer indices.
 608      *
 609      * \param cs        Command stream
 610      * \param buf       Buffer
 611      * \return          The buffer index, or -1 if the buffer has not been added.
 612      */
 613     int (*cs_lookup_buffer)(struct radeon_winsys_cs *cs,
 614                             struct pb_buffer *buf);
 615
 616     /**
 617      * Return true if there is enough memory in VRAM and GTT for the buffers
 618      * added so far. If the validation fails, all buffers which have
 619      * been added since the last call of cs_validate will be removed and
 620      * the CS will be flushed (provided there are still any buffers).
 621      *
 622      * \param cs        A command stream to validate.
 623      */
 624     bool (*cs_validate)(struct radeon_winsys_cs *cs);
 625
 626     /**
 627      * Check whether the given number of dwords is available in the IB.
 628      * Optionally chain a new chunk of the IB if necessary and supported.
 629      *
 630      * \param cs        A command stream.
 631      * \param dw        Number of CS dwords requested by the caller.
 632      */
 633     bool (*cs_check_space)(struct radeon_winsys_cs *cs, unsigned dw);
 634
 635     /**
 636      * Return the buffer list.
 637      *
 638      * \param cs    Command stream
 639      * \param list  Returned buffer list. Set to NULL to query the count only.
 640      * \return      The buffer count.
 641      */
 642     unsigned (*cs_get_buffer_list)(struct radeon_winsys_cs *cs,
 643                                    struct radeon_bo_list_item *list);
 644
 645     /**
 646      * Flush a command stream.
 647      *
 648      * \param cs          A command stream to flush.
 649      * \param flags,      RADEON_FLUSH_ASYNC or 0.
 650      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 651      *                    after the CS and is returned through this parameter.
 652      * \return Negative POSIX error code or 0 for success.
 653      *         Asynchronous submissions never return an error.
 654      */
 655     int (*cs_flush)(struct radeon_winsys_cs *cs,
 656                     unsigned flags,
 657                     struct pipe_fence_handle **fence);
 658
 659     /**
 660      * Create a fence before the CS is flushed.
 661      * The user must flush manually to complete the initializaton of the fence.
 662      * The fence must not be used before the flush.
 663      */
 664     struct pipe_fence_handle *(*cs_get_next_fence)(struct radeon_winsys_cs *cs);
 665
 666     /**
 667      * Return true if a buffer is referenced by a command stream.
 668      *
 669      * \param cs        A command stream.
 670      * \param buf       A winsys buffer.
 671      */
 672     bool (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
 673                                     struct pb_buffer *buf,
 674                                     enum radeon_bo_usage usage);
 675
 676     /**
 677      * Request access to a feature for a command stream.
 678      *
 679      * \param cs        A command stream.
 680      * \param fid       Feature ID, one of RADEON_FID_*
 681      * \param enable    Whether to enable or disable the feature.
 682      */
 683     bool (*cs_request_feature)(struct radeon_winsys_cs *cs,
 684                                enum radeon_feature_id fid,
 685                                bool enable);
 686      /**
 687       * Make sure all asynchronous flush of the cs have completed
 688       *
 689       * \param cs        A command stream.
 690       */
 691     void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
 692
 693     /**
 694      * Wait for the fence and return true if the fence has been signalled.
 695      * The timeout of 0 will only return the status.
 696      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 697      * is signalled.
 698      */
 699     bool (*fence_wait)(struct radeon_winsys *ws,
 700                        struct pipe_fence_handle *fence,
 701                        uint64_t timeout);
 702
 703     /**
 704      * Reference counting for fences.
 705      */
 706     void (*fence_reference)(struct pipe_fence_handle **dst,
 707                             struct pipe_fence_handle *src);
 708
 709     /**
 710      * Initialize surface
 711      *
 712      * \param ws        The winsys this function is called from.
 713      * \param surf      Surface structure ptr
 714      */
 715     int (*surface_init)(struct radeon_winsys *ws,
 716                         struct radeon_surf *surf);
 717
 718     /**
 719      * Find best values for a surface
 720      *
 721      * \param ws        The winsys this function is called from.
 722      * \param surf      Surface structure ptr
 723      */
 724     int (*surface_best)(struct radeon_winsys *ws,
 725                         struct radeon_surf *surf);
 726
 727     uint64_t (*query_value)(struct radeon_winsys *ws,
 728                             enum radeon_value_id value);
 729
 730     bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 731                            unsigned num_registers, uint32_t *out);
 732 };
 733
 734 static inline bool radeon_emitted(struct radeon_winsys_cs *cs, unsigned num_dw)
 735 {
 736     return cs && (cs->prev_dw + cs->current.cdw > num_dw);
 737 }
 738
 739 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 740 {
 741     cs->current.buf[cs->current.cdw++] = value;
 742 }
 743
 744 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 745                                      const uint32_t *values, unsigned count)
 746 {
 747     memcpy(cs->current.buf + cs->current.cdw, values, count * 4);
 748     cs->current.cdw += count;
 749 }
 750
 751 #endif