2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
4 * Copyright 2018 Advanced Micro Devices, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * on the rights to use, copy, modify, merge, publish, distribute, sub
11 * license, and/or sell copies of the Software, and to permit persons to whom
12 * the Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
26 #ifndef RADEON_WINSYS_H
27 #define RADEON_WINSYS_H
29 /* The public winsys interface header for the radeon driver. */
31 /* Whether the next IB can start immediately and not wait for draws and
32 * dispatches from the current IB to finish. */
33 #define RADEON_FLUSH_START_NEXT_GFX_IB_NOW (1u << 31)
35 #define RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW \
36 (PIPE_FLUSH_ASYNC | RADEON_FLUSH_START_NEXT_GFX_IB_NOW)
38 #include "pipebuffer/pb_buffer.h"
40 #include "amd/common/ac_gpu_info.h"
41 #include "amd/common/ac_surface.h"
44 enum radeon_bo_layout
{
45 RADEON_LAYOUT_LINEAR
= 0,
47 RADEON_LAYOUT_SQUARETILED
,
52 enum radeon_bo_domain
{ /* bitfield */
53 RADEON_DOMAIN_GTT
= 2,
54 RADEON_DOMAIN_VRAM
= 4,
55 RADEON_DOMAIN_VRAM_GTT
= RADEON_DOMAIN_VRAM
| RADEON_DOMAIN_GTT
,
56 RADEON_DOMAIN_GDS
= 8,
57 RADEON_DOMAIN_OA
= 16,
60 enum radeon_bo_flag
{ /* bitfield */
61 RADEON_FLAG_GTT_WC
= (1 << 0),
62 RADEON_FLAG_NO_CPU_ACCESS
= (1 << 1),
63 RADEON_FLAG_NO_SUBALLOC
= (1 << 2),
64 RADEON_FLAG_SPARSE
= (1 << 3),
65 RADEON_FLAG_NO_INTERPROCESS_SHARING
= (1 << 4),
66 RADEON_FLAG_READ_ONLY
= (1 << 5),
67 RADEON_FLAG_32BIT
= (1 << 6),
70 enum radeon_dependency_flag
{
71 /* Add the dependency to the parallel compute IB only. */
72 RADEON_DEPENDENCY_PARALLEL_COMPUTE_ONLY
= 1 << 0,
74 /* Instead of waiting for a job to finish execution, the dependency will
75 * be signaled when the job starts execution.
77 RADEON_DEPENDENCY_START_FENCE
= 1 << 1,
80 enum radeon_bo_usage
{ /* bitfield */
81 RADEON_USAGE_READ
= 2,
82 RADEON_USAGE_WRITE
= 4,
83 RADEON_USAGE_READWRITE
= RADEON_USAGE_READ
| RADEON_USAGE_WRITE
,
85 /* The winsys ensures that the CS submission will be scheduled after
86 * previously flushed CSs referencing this BO in a conflicting way.
88 RADEON_USAGE_SYNCHRONIZED
= 8
91 enum radeon_transfer_flags
{
92 /* Indicates that the caller will unmap the buffer.
94 * Not unmapping buffers is an important performance optimization for
95 * OpenGL (avoids kernel overhead for frequently mapped buffers).
97 RADEON_TRANSFER_TEMPORARY
= (PIPE_TRANSFER_DRV_PRV
<< 0),
100 #define RADEON_SPARSE_PAGE_SIZE (64 * 1024)
115 enum radeon_value_id
{
116 RADEON_REQUESTED_VRAM_MEMORY
,
117 RADEON_REQUESTED_GTT_MEMORY
,
120 RADEON_BUFFER_WAIT_TIME_NS
,
121 RADEON_NUM_MAPPED_BUFFERS
,
125 RADEON_GFX_BO_LIST_COUNTER
, /* number of BOs submitted in gfx IBs */
126 RADEON_GFX_IB_SIZE_COUNTER
,
127 RADEON_NUM_BYTES_MOVED
,
128 RADEON_NUM_EVICTIONS
,
129 RADEON_NUM_VRAM_CPU_PAGE_FAULTS
,
131 RADEON_VRAM_VIS_USAGE
,
133 RADEON_GPU_TEMPERATURE
, /* DRM 2.42.0 */
136 RADEON_GPU_RESET_COUNTER
, /* DRM 2.43.0 */
137 RADEON_CS_THREAD_TIME
,
140 enum radeon_bo_priority
{
141 /* Each group of two has the same priority. */
142 RADEON_PRIO_FENCE
= 0,
145 RADEON_PRIO_SO_FILLED_SIZE
= 2,
148 RADEON_PRIO_IB1
= 4, /* main IB submitted to the kernel */
149 RADEON_PRIO_IB2
, /* IB executed with INDIRECT_BUFFER */
151 RADEON_PRIO_DRAW_INDIRECT
= 6,
152 RADEON_PRIO_INDEX_BUFFER
,
154 RADEON_PRIO_CP_DMA
= 8,
155 RADEON_PRIO_BORDER_COLORS
,
157 RADEON_PRIO_CONST_BUFFER
= 10,
158 RADEON_PRIO_DESCRIPTORS
,
160 RADEON_PRIO_SAMPLER_BUFFER
= 12,
161 RADEON_PRIO_VERTEX_BUFFER
,
163 RADEON_PRIO_SHADER_RW_BUFFER
= 14,
164 RADEON_PRIO_COMPUTE_GLOBAL
,
166 RADEON_PRIO_SAMPLER_TEXTURE
= 16,
167 RADEON_PRIO_SHADER_RW_IMAGE
,
169 RADEON_PRIO_SAMPLER_TEXTURE_MSAA
= 18,
170 RADEON_PRIO_COLOR_BUFFER
,
172 RADEON_PRIO_DEPTH_BUFFER
= 20,
174 RADEON_PRIO_COLOR_BUFFER_MSAA
= 22,
176 RADEON_PRIO_DEPTH_BUFFER_MSAA
= 24,
178 RADEON_PRIO_SEPARATE_META
= 26,
179 RADEON_PRIO_SHADER_BINARY
, /* the hw can't hide instruction cache misses */
181 RADEON_PRIO_SHADER_RINGS
= 28,
183 RADEON_PRIO_SCRATCH_BUFFER
= 30,
184 /* 31 is the maximum value */
187 struct winsys_handle
;
188 struct radeon_winsys_ctx
;
190 struct radeon_cmdbuf_chunk
{
191 unsigned cdw
; /* Number of used dwords. */
192 unsigned max_dw
; /* Maximum number of dwords. */
193 uint32_t *buf
; /* The base pointer of the chunk. */
196 struct radeon_cmdbuf
{
197 struct radeon_cmdbuf_chunk current
;
198 struct radeon_cmdbuf_chunk
*prev
;
199 unsigned num_prev
; /* Number of previous chunks. */
200 unsigned max_prev
; /* Space in array pointed to by prev. */
201 unsigned prev_dw
; /* Total number of dwords in previous chunks. */
203 /* Memory usage of the buffer list. These are always 0 for preamble IBs. */
206 uint64_t gpu_address
;
209 /* Tiling info for display code, DRI sharing, and other data. */
210 struct radeon_bo_metadata
{
211 /* Tiling flags describing the texture layout for display code
216 enum radeon_bo_layout microtile
;
217 enum radeon_bo_layout macrotile
;
218 unsigned pipe_config
;
230 unsigned swizzle_mode
:5;
233 /* [31:8]: max offset = 4GB - 256; 0 = DCC disabled */
234 unsigned dcc_offset_256B
:24;
235 unsigned dcc_pitch_max
:14; /* (mip chain pitch - 1) for DCN */
236 unsigned dcc_independent_64B
:1;
240 /* Additional metadata associated with the buffer, in bytes.
241 * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
242 * Supported by amdgpu only.
244 uint32_t size_metadata
;
245 uint32_t metadata
[64];
248 enum radeon_feature_id
{
249 RADEON_FID_R300_HYPERZ_ACCESS
, /* ZMask + HiZ */
250 RADEON_FID_R300_CMASK_ACCESS
,
253 struct radeon_bo_list_item
{
256 uint32_t priority_usage
; /* mask of (1 << RADEON_PRIO_*) */
259 struct radeon_winsys
{
261 * The screen object this winsys was created for
263 struct pipe_screen
*screen
;
266 * Decrement the winsys reference count.
268 * \param ws The winsys this function is called for.
269 * \return True if the winsys and screen should be destroyed.
271 bool (*unref
)(struct radeon_winsys
*ws
);
274 * Destroy this winsys.
276 * \param ws The winsys this function is called from.
278 void (*destroy
)(struct radeon_winsys
*ws
);
281 * Query an info structure from winsys.
283 * \param ws The winsys this function is called from.
284 * \param info Return structure
286 void (*query_info
)(struct radeon_winsys
*ws
,
287 struct radeon_info
*info
);
290 * A hint for the winsys that it should pin its execution threads to
291 * a group of cores sharing a specific L3 cache if the CPU has multiple
292 * L3 caches. This is needed for good multithreading performance on
295 void (*pin_threads_to_L3_cache
)(struct radeon_winsys
*ws
, unsigned cache
);
297 /**************************************************************************
298 * Buffer management. Buffer attributes are mostly fixed over its lifetime.
300 * Remember that gallium gets to choose the interface it needs, and the
301 * window systems must then implement that interface (rather than the
302 * other way around...).
303 *************************************************************************/
306 * Create a buffer object.
308 * \param ws The winsys this function is called from.
309 * \param size The size to allocate.
310 * \param alignment An alignment of the buffer in memory.
311 * \param use_reusable_pool Whether the cache buffer manager should be used.
312 * \param domain A bitmask of the RADEON_DOMAIN_* flags.
313 * \return The created buffer object.
315 struct pb_buffer
*(*buffer_create
)(struct radeon_winsys
*ws
,
318 enum radeon_bo_domain domain
,
319 enum radeon_bo_flag flags
);
322 * Map the entire data store of a buffer object into the client's address
325 * Callers are expected to unmap buffers again if and only if the
326 * RADEON_TRANSFER_TEMPORARY flag is set in \p usage.
328 * \param buf A winsys buffer object to map.
329 * \param cs A command stream to flush if the buffer is referenced by it.
330 * \param usage A bitmask of the PIPE_TRANSFER_* and RADEON_TRANSFER_* flags.
331 * \return The pointer at the beginning of the buffer.
333 void *(*buffer_map
)(struct pb_buffer
*buf
,
334 struct radeon_cmdbuf
*cs
,
335 enum pipe_transfer_usage usage
);
338 * Unmap a buffer object from the client's address space.
340 * \param buf A winsys buffer object to unmap.
342 void (*buffer_unmap
)(struct pb_buffer
*buf
);
345 * Wait for the buffer and return true if the buffer is not used
348 * The timeout of 0 will only return the status.
349 * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
352 bool (*buffer_wait
)(struct pb_buffer
*buf
, uint64_t timeout
,
353 enum radeon_bo_usage usage
);
356 * Return buffer metadata.
357 * (tiling info for display code, DRI sharing, and other data)
359 * \param buf A winsys buffer object to get the flags from.
362 void (*buffer_get_metadata
)(struct pb_buffer
*buf
,
363 struct radeon_bo_metadata
*md
);
366 * Set buffer metadata.
367 * (tiling info for display code, DRI sharing, and other data)
369 * \param buf A winsys buffer object to set the flags for.
372 void (*buffer_set_metadata
)(struct pb_buffer
*buf
,
373 struct radeon_bo_metadata
*md
);
376 * Get a winsys buffer from a winsys handle. The internal structure
377 * of the handle is platform-specific and only a winsys should access it.
379 * \param ws The winsys this function is called from.
380 * \param whandle A winsys handle pointer as was received from a state
382 * \param stride The returned buffer stride in bytes.
384 struct pb_buffer
*(*buffer_from_handle
)(struct radeon_winsys
*ws
,
385 struct winsys_handle
*whandle
,
386 unsigned vm_alignment
,
387 unsigned *stride
, unsigned *offset
);
390 * Get a winsys buffer from a user pointer. The resulting buffer can't
391 * be exported. Both pointer and size must be page aligned.
393 * \param ws The winsys this function is called from.
394 * \param pointer User pointer to turn into a buffer object.
395 * \param Size Size in bytes for the new buffer.
397 struct pb_buffer
*(*buffer_from_ptr
)(struct radeon_winsys
*ws
,
398 void *pointer
, uint64_t size
);
401 * Whether the buffer was created from a user pointer.
403 * \param buf A winsys buffer object
404 * \return whether \p buf was created via buffer_from_ptr
406 bool (*buffer_is_user_ptr
)(struct pb_buffer
*buf
);
408 /** Whether the buffer was suballocated. */
409 bool (*buffer_is_suballocated
)(struct pb_buffer
*buf
);
412 * Get a winsys handle from a winsys buffer. The internal structure
413 * of the handle is platform-specific and only a winsys should access it.
415 * \param buf A winsys buffer object to get the handle from.
416 * \param whandle A winsys handle pointer.
417 * \param stride A stride of the buffer in bytes, for texturing.
418 * \return true on success.
420 bool (*buffer_get_handle
)(struct pb_buffer
*buf
,
421 unsigned stride
, unsigned offset
,
423 struct winsys_handle
*whandle
);
426 * Change the commitment of a (64KB-page aligned) region of the given
429 * \warning There is no automatic synchronization with command submission.
431 * \note Only implemented by the amdgpu winsys.
433 * \return false on out of memory or other failure, true on success.
435 bool (*buffer_commit
)(struct pb_buffer
*buf
,
436 uint64_t offset
, uint64_t size
,
440 * Return the virtual address of a buffer.
442 * When virtual memory is not in use, this is the offset relative to the
443 * relocation base (non-zero for sub-allocated buffers).
445 * \param buf A winsys buffer object
446 * \return virtual address
448 uint64_t (*buffer_get_virtual_address
)(struct pb_buffer
*buf
);
451 * Return the offset of this buffer relative to the relocation base.
452 * This is only non-zero for sub-allocated buffers.
454 * This is only supported in the radeon winsys, since amdgpu uses virtual
455 * addresses in submissions even for the video engines.
457 * \param buf A winsys buffer object
458 * \return the offset for relocations
460 unsigned (*buffer_get_reloc_offset
)(struct pb_buffer
*buf
);
463 * Query the initial placement of the buffer from the kernel driver.
465 enum radeon_bo_domain (*buffer_get_initial_domain
)(struct pb_buffer
*buf
);
467 /**************************************************************************
468 * Command submission.
470 * Each pipe context should create its own command stream and submit
471 * commands independently of other contexts.
472 *************************************************************************/
475 * Create a command submission context.
476 * Various command streams can be submitted to the same context.
478 struct radeon_winsys_ctx
*(*ctx_create
)(struct radeon_winsys
*ws
);
483 void (*ctx_destroy
)(struct radeon_winsys_ctx
*ctx
);
486 * Query a GPU reset status.
488 enum pipe_reset_status (*ctx_query_reset_status
)(struct radeon_winsys_ctx
*ctx
);
491 * Create a command stream.
493 * \param ctx The submission context
494 * \param ring_type The ring type (GFX, DMA, UVD)
495 * \param flush Flush callback function associated with the command stream.
496 * \param user User pointer that will be passed to the flush callback.
498 struct radeon_cmdbuf
*(*cs_create
)(struct radeon_winsys_ctx
*ctx
,
499 enum ring_type ring_type
,
500 void (*flush
)(void *ctx
, unsigned flags
,
501 struct pipe_fence_handle
**fence
),
503 bool stop_exec_on_failure
);
506 * Add a parallel compute IB to a gfx IB. It will share the buffer list
507 * and fence dependencies with the gfx IB. The gfx flush call will submit
508 * both IBs at the same time.
510 * The compute IB doesn't have an output fence, so the primary IB has
511 * to use a wait packet for synchronization.
513 * The returned IB is only a stream for writing packets to the new
514 * IB. Calling other winsys functions with it is not allowed, not even
515 * "cs_destroy". Use the gfx IB instead.
519 struct radeon_cmdbuf
*(*cs_add_parallel_compute_ib
)(struct radeon_cmdbuf
*cs
,
520 bool uses_gds_ordered_append
);
523 * Destroy a command stream.
525 * \param cs A command stream to destroy.
527 void (*cs_destroy
)(struct radeon_cmdbuf
*cs
);
530 * Add a buffer. Each buffer used by a CS must be added using this function.
532 * \param cs Command stream
534 * \param usage Whether the buffer is used for read and/or write.
535 * \param domain Bitmask of the RADEON_DOMAIN_* flags.
536 * \param priority A higher number means a greater chance of being
537 * placed in the requested domain. 15 is the maximum.
538 * \return Buffer index.
540 unsigned (*cs_add_buffer
)(struct radeon_cmdbuf
*cs
,
541 struct pb_buffer
*buf
,
542 enum radeon_bo_usage usage
,
543 enum radeon_bo_domain domain
,
544 enum radeon_bo_priority priority
);
547 * Return the index of an already-added buffer.
549 * Not supported on amdgpu. Drivers with GPUVM should not care about
552 * \param cs Command stream
554 * \return The buffer index, or -1 if the buffer has not been added.
556 int (*cs_lookup_buffer
)(struct radeon_cmdbuf
*cs
,
557 struct pb_buffer
*buf
);
560 * Return true if there is enough memory in VRAM and GTT for the buffers
561 * added so far. If the validation fails, all buffers which have
562 * been added since the last call of cs_validate will be removed and
563 * the CS will be flushed (provided there are still any buffers).
565 * \param cs A command stream to validate.
567 bool (*cs_validate
)(struct radeon_cmdbuf
*cs
);
570 * Check whether the given number of dwords is available in the IB.
571 * Optionally chain a new chunk of the IB if necessary and supported.
573 * \param cs A command stream.
574 * \param dw Number of CS dwords requested by the caller.
575 * \param force_chaining Chain the IB into a new buffer now to discard
576 * the CP prefetch cache (to emulate PKT3_REWIND)
577 * \return true if there is enough space
579 bool (*cs_check_space
)(struct radeon_cmdbuf
*cs
, unsigned dw
,
580 bool force_chaining
);
583 * Return the buffer list.
585 * This is the buffer list as passed to the kernel, i.e. it only contains
586 * the parent buffers of sub-allocated buffers.
588 * \param cs Command stream
589 * \param list Returned buffer list. Set to NULL to query the count only.
590 * \return The buffer count.
592 unsigned (*cs_get_buffer_list
)(struct radeon_cmdbuf
*cs
,
593 struct radeon_bo_list_item
*list
);
596 * Flush a command stream.
598 * \param cs A command stream to flush.
599 * \param flags, PIPE_FLUSH_* flags.
600 * \param fence Pointer to a fence. If non-NULL, a fence is inserted
601 * after the CS and is returned through this parameter.
602 * \return Negative POSIX error code or 0 for success.
603 * Asynchronous submissions never return an error.
605 int (*cs_flush
)(struct radeon_cmdbuf
*cs
,
607 struct pipe_fence_handle
**fence
);
610 * Create a fence before the CS is flushed.
611 * The user must flush manually to complete the initializaton of the fence.
613 * The fence must not be used for anything except \ref cs_add_fence_dependency
616 struct pipe_fence_handle
*(*cs_get_next_fence
)(struct radeon_cmdbuf
*cs
);
619 * Return true if a buffer is referenced by a command stream.
621 * \param cs A command stream.
622 * \param buf A winsys buffer.
624 bool (*cs_is_buffer_referenced
)(struct radeon_cmdbuf
*cs
,
625 struct pb_buffer
*buf
,
626 enum radeon_bo_usage usage
);
629 * Request access to a feature for a command stream.
631 * \param cs A command stream.
632 * \param fid Feature ID, one of RADEON_FID_*
633 * \param enable Whether to enable or disable the feature.
635 bool (*cs_request_feature
)(struct radeon_cmdbuf
*cs
,
636 enum radeon_feature_id fid
,
639 * Make sure all asynchronous flush of the cs have completed
641 * \param cs A command stream.
643 void (*cs_sync_flush
)(struct radeon_cmdbuf
*cs
);
646 * Add a fence dependency to the CS, so that the CS will wait for
647 * the fence before execution.
649 * \param dependency_flags Bitmask of RADEON_DEPENDENCY_*
651 void (*cs_add_fence_dependency
)(struct radeon_cmdbuf
*cs
,
652 struct pipe_fence_handle
*fence
,
653 unsigned dependency_flags
);
656 * Signal a syncobj when the CS finishes execution.
658 void (*cs_add_syncobj_signal
)(struct radeon_cmdbuf
*cs
,
659 struct pipe_fence_handle
*fence
);
662 * Wait for the fence and return true if the fence has been signalled.
663 * The timeout of 0 will only return the status.
664 * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
667 bool (*fence_wait
)(struct radeon_winsys
*ws
,
668 struct pipe_fence_handle
*fence
,
672 * Reference counting for fences.
674 void (*fence_reference
)(struct pipe_fence_handle
**dst
,
675 struct pipe_fence_handle
*src
);
678 * Create a new fence object corresponding to the given syncobj fd.
680 struct pipe_fence_handle
*(*fence_import_syncobj
)(struct radeon_winsys
*ws
,
684 * Create a new fence object corresponding to the given sync_file.
686 struct pipe_fence_handle
*(*fence_import_sync_file
)(struct radeon_winsys
*ws
,
690 * Return a sync_file FD corresponding to the given fence object.
692 int (*fence_export_sync_file
)(struct radeon_winsys
*ws
,
693 struct pipe_fence_handle
*fence
);
696 * Return a sync file FD that is already signalled.
698 int (*export_signalled_sync_file
)(struct radeon_winsys
*ws
);
703 * \param ws The winsys this function is called from.
704 * \param tex Input texture description
705 * \param flags Bitmask of RADEON_SURF_* flags
706 * \param bpe Bytes per pixel, it can be different for Z buffers.
707 * \param mode Preferred tile mode. (linear, 1D, or 2D)
708 * \param surf Output structure
710 int (*surface_init
)(struct radeon_winsys
*ws
,
711 const struct pipe_resource
*tex
,
712 unsigned flags
, unsigned bpe
,
713 enum radeon_surf_mode mode
,
714 struct radeon_surf
*surf
);
716 uint64_t (*query_value
)(struct radeon_winsys
*ws
,
717 enum radeon_value_id value
);
719 bool (*read_registers
)(struct radeon_winsys
*ws
, unsigned reg_offset
,
720 unsigned num_registers
, uint32_t *out
);
723 static inline bool radeon_emitted(struct radeon_cmdbuf
*cs
, unsigned num_dw
)
725 return cs
&& (cs
->prev_dw
+ cs
->current
.cdw
> num_dw
);
728 static inline void radeon_emit(struct radeon_cmdbuf
*cs
, uint32_t value
)
730 cs
->current
.buf
[cs
->current
.cdw
++] = value
;
733 static inline void radeon_emit_array(struct radeon_cmdbuf
*cs
,
734 const uint32_t *values
, unsigned count
)
736 memcpy(cs
->current
.buf
+ cs
->current
.cdw
, values
, count
* 4);
737 cs
->current
.cdw
+= count
;
741 RADEON_HEAP_VRAM_NO_CPU_ACCESS
,
742 RADEON_HEAP_VRAM_READ_ONLY
,
743 RADEON_HEAP_VRAM_READ_ONLY_32BIT
,
744 RADEON_HEAP_VRAM_32BIT
,
747 RADEON_HEAP_GTT_WC_READ_ONLY
,
748 RADEON_HEAP_GTT_WC_READ_ONLY_32BIT
,
749 RADEON_HEAP_GTT_WC_32BIT
,
751 RADEON_MAX_SLAB_HEAPS
,
752 RADEON_MAX_CACHED_HEAPS
= RADEON_MAX_SLAB_HEAPS
,
755 static inline enum radeon_bo_domain
radeon_domain_from_heap(enum radeon_heap heap
)
758 case RADEON_HEAP_VRAM_NO_CPU_ACCESS
:
759 case RADEON_HEAP_VRAM_READ_ONLY
:
760 case RADEON_HEAP_VRAM_READ_ONLY_32BIT
:
761 case RADEON_HEAP_VRAM_32BIT
:
762 case RADEON_HEAP_VRAM
:
763 return RADEON_DOMAIN_VRAM
;
764 case RADEON_HEAP_GTT_WC
:
765 case RADEON_HEAP_GTT_WC_READ_ONLY
:
766 case RADEON_HEAP_GTT_WC_READ_ONLY_32BIT
:
767 case RADEON_HEAP_GTT_WC_32BIT
:
768 case RADEON_HEAP_GTT
:
769 return RADEON_DOMAIN_GTT
;
772 return (enum radeon_bo_domain
)0;
776 static inline unsigned radeon_flags_from_heap(enum radeon_heap heap
)
778 unsigned flags
= RADEON_FLAG_NO_INTERPROCESS_SHARING
|
779 (heap
!= RADEON_HEAP_GTT
? RADEON_FLAG_GTT_WC
: 0);
782 case RADEON_HEAP_VRAM_NO_CPU_ACCESS
:
784 RADEON_FLAG_NO_CPU_ACCESS
;
786 case RADEON_HEAP_VRAM_READ_ONLY
:
787 case RADEON_HEAP_GTT_WC_READ_ONLY
:
789 RADEON_FLAG_READ_ONLY
;
791 case RADEON_HEAP_VRAM_READ_ONLY_32BIT
:
792 case RADEON_HEAP_GTT_WC_READ_ONLY_32BIT
:
794 RADEON_FLAG_READ_ONLY
|
797 case RADEON_HEAP_VRAM_32BIT
:
798 case RADEON_HEAP_GTT_WC_32BIT
:
802 case RADEON_HEAP_VRAM
:
803 case RADEON_HEAP_GTT_WC
:
804 case RADEON_HEAP_GTT
:
810 /* Return the heap index for winsys allocators, or -1 on failure. */
811 static inline int radeon_get_heap_index(enum radeon_bo_domain domain
,
812 enum radeon_bo_flag flags
)
814 /* VRAM implies WC (write combining) */
815 assert(!(domain
& RADEON_DOMAIN_VRAM
) || flags
& RADEON_FLAG_GTT_WC
);
816 /* NO_CPU_ACCESS implies VRAM only. */
817 assert(!(flags
& RADEON_FLAG_NO_CPU_ACCESS
) || domain
== RADEON_DOMAIN_VRAM
);
819 /* Resources with interprocess sharing don't use any winsys allocators. */
820 if (!(flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
))
823 /* Unsupported flags: NO_SUBALLOC, SPARSE. */
824 if (flags
& ~(RADEON_FLAG_GTT_WC
|
825 RADEON_FLAG_NO_CPU_ACCESS
|
826 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
827 RADEON_FLAG_READ_ONLY
|
832 case RADEON_DOMAIN_VRAM
:
833 switch (flags
& (RADEON_FLAG_NO_CPU_ACCESS
|
834 RADEON_FLAG_READ_ONLY
|
835 RADEON_FLAG_32BIT
)) {
836 case RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_READ_ONLY
| RADEON_FLAG_32BIT
:
837 case RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_READ_ONLY
:
838 assert(!"NO_CPU_ACCESS | READ_ONLY doesn't make sense");
840 case RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_32BIT
:
841 assert(!"NO_CPU_ACCESS with 32BIT is disallowed");
843 case RADEON_FLAG_NO_CPU_ACCESS
:
844 return RADEON_HEAP_VRAM_NO_CPU_ACCESS
;
845 case RADEON_FLAG_READ_ONLY
| RADEON_FLAG_32BIT
:
846 return RADEON_HEAP_VRAM_READ_ONLY_32BIT
;
847 case RADEON_FLAG_READ_ONLY
:
848 return RADEON_HEAP_VRAM_READ_ONLY
;
849 case RADEON_FLAG_32BIT
:
850 return RADEON_HEAP_VRAM_32BIT
;
852 return RADEON_HEAP_VRAM
;
855 case RADEON_DOMAIN_GTT
:
856 switch (flags
& (RADEON_FLAG_GTT_WC
|
857 RADEON_FLAG_READ_ONLY
|
858 RADEON_FLAG_32BIT
)) {
859 case RADEON_FLAG_GTT_WC
| RADEON_FLAG_READ_ONLY
| RADEON_FLAG_32BIT
:
860 return RADEON_HEAP_GTT_WC_READ_ONLY_32BIT
;
861 case RADEON_FLAG_GTT_WC
| RADEON_FLAG_READ_ONLY
:
862 return RADEON_HEAP_GTT_WC_READ_ONLY
;
863 case RADEON_FLAG_GTT_WC
| RADEON_FLAG_32BIT
:
864 return RADEON_HEAP_GTT_WC_32BIT
;
865 case RADEON_FLAG_GTT_WC
:
866 return RADEON_HEAP_GTT_WC
;
867 case RADEON_FLAG_READ_ONLY
| RADEON_FLAG_32BIT
:
868 case RADEON_FLAG_READ_ONLY
:
869 assert(!"READ_ONLY without WC is disallowed");
871 case RADEON_FLAG_32BIT
:
872 assert(!"32BIT without WC is disallowed");
875 return RADEON_HEAP_GTT
;