2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 #ifndef RADEON_WINSYS_H
25 #define RADEON_WINSYS_H
27 /* The public winsys interface header for the radeon driver. */
29 #include "pipebuffer/pb_buffer.h"
31 #include "amd/common/amd_family.h"
33 #define RADEON_FLUSH_ASYNC (1 << 0)
34 #define RADEON_FLUSH_END_OF_FRAME (1 << 1)
37 enum radeon_bo_layout
{
38 RADEON_LAYOUT_LINEAR
= 0,
40 RADEON_LAYOUT_SQUARETILED
,
45 enum radeon_bo_domain
{ /* bitfield */
46 RADEON_DOMAIN_GTT
= 2,
47 RADEON_DOMAIN_VRAM
= 4,
48 RADEON_DOMAIN_VRAM_GTT
= RADEON_DOMAIN_VRAM
| RADEON_DOMAIN_GTT
51 enum radeon_bo_flag
{ /* bitfield */
52 RADEON_FLAG_GTT_WC
= (1 << 0),
53 RADEON_FLAG_CPU_ACCESS
= (1 << 1),
54 RADEON_FLAG_NO_CPU_ACCESS
= (1 << 2),
55 RADEON_FLAG_HANDLE
= (1 << 3), /* the buffer most not be suballocated */
58 enum radeon_bo_usage
{ /* bitfield */
59 RADEON_USAGE_READ
= 2,
60 RADEON_USAGE_WRITE
= 4,
61 RADEON_USAGE_READWRITE
= RADEON_USAGE_READ
| RADEON_USAGE_WRITE
,
63 /* The winsys ensures that the CS submission will be scheduled after
64 * previously flushed CSs referencing this BO in a conflicting way.
66 RADEON_USAGE_SYNCHRONIZED
= 8
78 enum radeon_value_id
{
79 RADEON_REQUESTED_VRAM_MEMORY
,
80 RADEON_REQUESTED_GTT_MEMORY
,
83 RADEON_BUFFER_WAIT_TIME_NS
,
87 RADEON_NUM_BYTES_MOVED
,
91 RADEON_GPU_TEMPERATURE
, /* DRM 2.42.0 */
94 RADEON_GPU_RESET_COUNTER
, /* DRM 2.43.0 */
97 /* Each group of four has the same priority. */
98 enum radeon_bo_priority
{
99 RADEON_PRIO_FENCE
= 0,
101 RADEON_PRIO_SO_FILLED_SIZE
,
104 RADEON_PRIO_IB1
= 4, /* main IB submitted to the kernel */
105 RADEON_PRIO_IB2
, /* IB executed with INDIRECT_BUFFER */
106 RADEON_PRIO_DRAW_INDIRECT
,
107 RADEON_PRIO_INDEX_BUFFER
,
111 RADEON_PRIO_SDMA_BUFFER
,
112 RADEON_PRIO_SDMA_TEXTURE
,
114 RADEON_PRIO_CP_DMA
= 12,
116 RADEON_PRIO_CONST_BUFFER
= 16,
117 RADEON_PRIO_DESCRIPTORS
,
118 RADEON_PRIO_BORDER_COLORS
,
120 RADEON_PRIO_SAMPLER_BUFFER
= 20,
121 RADEON_PRIO_VERTEX_BUFFER
,
123 RADEON_PRIO_SHADER_RW_BUFFER
= 24,
124 RADEON_PRIO_COMPUTE_GLOBAL
,
126 RADEON_PRIO_SAMPLER_TEXTURE
= 28,
127 RADEON_PRIO_SHADER_RW_IMAGE
,
129 RADEON_PRIO_SAMPLER_TEXTURE_MSAA
= 32,
131 RADEON_PRIO_COLOR_BUFFER
= 36,
133 RADEON_PRIO_DEPTH_BUFFER
= 40,
135 RADEON_PRIO_COLOR_BUFFER_MSAA
= 44,
137 RADEON_PRIO_DEPTH_BUFFER_MSAA
= 48,
139 RADEON_PRIO_CMASK
= 52,
142 RADEON_PRIO_SHADER_BINARY
, /* the hw can't hide instruction cache misses */
144 RADEON_PRIO_SHADER_RINGS
= 56,
146 RADEON_PRIO_SCRATCH_BUFFER
= 60,
147 /* 63 is the maximum value */
150 struct winsys_handle
;
151 struct radeon_winsys_ctx
;
153 struct radeon_winsys_cs_chunk
{
154 unsigned cdw
; /* Number of used dwords. */
155 unsigned max_dw
; /* Maximum number of dwords. */
156 uint32_t *buf
; /* The base pointer of the chunk. */
159 struct radeon_winsys_cs
{
160 struct radeon_winsys_cs_chunk current
;
161 struct radeon_winsys_cs_chunk
*prev
;
162 unsigned num_prev
; /* Number of previous chunks. */
163 unsigned max_prev
; /* Space in array pointed to by prev. */
164 unsigned prev_dw
; /* Total number of dwords in previous chunks. */
166 /* Memory usage of the buffer list. These are always 0 for CE and preamble
173 /* PCI info: domain:bus:dev:func */
181 enum radeon_family family
;
182 enum chip_class chip_class
;
183 uint32_t gart_page_size
;
186 uint64_t max_alloc_size
;
187 uint32_t min_alloc_size
;
188 bool has_dedicated_vram
;
189 bool has_virtual_memory
;
190 bool gfx_ib_pad_with_type2
;
193 uint32_t uvd_fw_version
;
194 uint32_t vce_fw_version
;
195 uint32_t me_fw_version
;
196 uint32_t pfp_fw_version
;
197 uint32_t ce_fw_version
;
198 uint32_t vce_harvest_config
;
199 uint32_t clock_crystal_freq
;
202 uint32_t drm_major
; /* version */
204 uint32_t drm_patchlevel
;
208 uint32_t r600_max_quad_pipes
; /* wave size / 16 */
209 uint32_t max_shader_clock
;
210 uint32_t num_good_compute_units
;
211 uint32_t max_se
; /* shader engines */
212 uint32_t max_sh_per_se
; /* shader arrays per shader engine */
214 /* Render backends (color + depth blocks). */
215 uint32_t r300_num_gb_pipes
;
216 uint32_t r300_num_z_pipes
;
217 uint32_t r600_gb_backend_map
; /* R600 harvest config */
218 bool r600_gb_backend_map_valid
;
219 uint32_t r600_num_banks
;
220 uint32_t num_render_backends
;
221 uint32_t num_tile_pipes
; /* pipe count from PIPE_CONFIG */
222 uint32_t pipe_interleave_bytes
;
223 uint32_t enabled_rb_mask
; /* GCN harvest config */
226 uint32_t si_tile_mode_array
[32];
227 uint32_t cik_macrotile_mode_array
[16];
230 /* Tiling info for display code, DRI sharing, and other data. */
231 struct radeon_bo_metadata
{
232 /* Tiling flags describing the texture layout for display code
235 enum radeon_bo_layout microtile
;
236 enum radeon_bo_layout macrotile
;
237 unsigned pipe_config
;
246 /* Additional metadata associated with the buffer, in bytes.
247 * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
248 * Supported by amdgpu only.
250 uint32_t size_metadata
;
251 uint32_t metadata
[64];
254 enum radeon_feature_id
{
255 RADEON_FID_R300_HYPERZ_ACCESS
, /* ZMask + HiZ */
256 RADEON_FID_R300_CMASK_ACCESS
,
259 #define RADEON_SURF_MAX_LEVELS 15
261 enum radeon_surf_mode
{
262 RADEON_SURF_MODE_LINEAR_ALIGNED
= 1,
263 RADEON_SURF_MODE_1D
= 2,
264 RADEON_SURF_MODE_2D
= 3,
267 /* These are defined exactly like GB_TILE_MODEn.MICRO_TILE_MODE_NEW. */
268 enum radeon_micro_mode
{
269 RADEON_MICRO_MODE_DISPLAY
= 0,
270 RADEON_MICRO_MODE_THIN
= 1,
271 RADEON_MICRO_MODE_DEPTH
= 2,
272 RADEON_MICRO_MODE_ROTATED
= 3,
275 /* the first 16 bits are reserved for libdrm_radeon, don't use them */
276 #define RADEON_SURF_SCANOUT (1 << 16)
277 #define RADEON_SURF_ZBUFFER (1 << 17)
278 #define RADEON_SURF_SBUFFER (1 << 18)
279 #define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
280 /* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
281 #define RADEON_SURF_FMASK (1 << 21)
282 #define RADEON_SURF_DISABLE_DCC (1 << 22)
283 #define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23)
284 #define RADEON_SURF_IMPORTED (1 << 24)
285 #define RADEON_SURF_OPTIMIZE_FOR_SPACE (1 << 25)
287 struct radeon_surf_level
{
291 uint64_t dcc_fast_clear_size
;
294 enum radeon_surf_mode mode
;
298 /* Format properties. */
302 /* Number of mipmap levels where DCC is enabled starting from level 0.
303 * Non-zero levels may be disabled due to alignment constraints, but not
306 unsigned num_dcc_levels
:4;
307 unsigned is_linear
:1;
310 /* These are return values. Some of them can be set by the caller, but
311 * they will be treated as hints (e.g. bankw, bankh) and might be
312 * changed by the calculator.
318 uint32_t surf_alignment
;
319 uint32_t dcc_alignment
;
320 uint32_t htile_alignment
;
322 /* This applies to EG and later. */
323 unsigned bankw
:4; /* max 8 */
324 unsigned bankh
:4; /* max 8 */
325 unsigned mtilea
:4; /* max 8 */
326 unsigned tile_split
:13; /* max 4K */
327 unsigned stencil_tile_split
:13; /* max 4K */
328 unsigned pipe_config
:5; /* max 17 */
329 unsigned num_banks
:5; /* max 16 */
330 unsigned macro_tile_index
:4; /* max 15 */
331 unsigned micro_tile_mode
:3; /* displayable, thin, depth, rotated */
333 /* Whether the depth miptree or stencil miptree as used by the DB are
334 * adjusted from their TC compatible form to ensure depth/stencil
335 * compatibility. If either is true, the corresponding plane cannot be
338 unsigned depth_adjusted
:1;
339 unsigned stencil_adjusted
:1;
341 struct radeon_surf_level level
[RADEON_SURF_MAX_LEVELS
];
342 struct radeon_surf_level stencil_level
[RADEON_SURF_MAX_LEVELS
];
343 uint8_t tiling_index
[RADEON_SURF_MAX_LEVELS
];
344 uint8_t stencil_tiling_index
[RADEON_SURF_MAX_LEVELS
];
347 struct radeon_bo_list_item
{
350 uint64_t priority_usage
; /* mask of (1 << RADEON_PRIO_*) */
353 struct radeon_winsys
{
355 * The screen object this winsys was created for
357 struct pipe_screen
*screen
;
360 * Decrement the winsys reference count.
362 * \param ws The winsys this function is called for.
363 * \return True if the winsys and screen should be destroyed.
365 bool (*unref
)(struct radeon_winsys
*ws
);
368 * Destroy this winsys.
370 * \param ws The winsys this function is called from.
372 void (*destroy
)(struct radeon_winsys
*ws
);
375 * Query an info structure from winsys.
377 * \param ws The winsys this function is called from.
378 * \param info Return structure
380 void (*query_info
)(struct radeon_winsys
*ws
,
381 struct radeon_info
*info
);
383 /**************************************************************************
384 * Buffer management. Buffer attributes are mostly fixed over its lifetime.
386 * Remember that gallium gets to choose the interface it needs, and the
387 * window systems must then implement that interface (rather than the
388 * other way around...).
389 *************************************************************************/
392 * Create a buffer object.
394 * \param ws The winsys this function is called from.
395 * \param size The size to allocate.
396 * \param alignment An alignment of the buffer in memory.
397 * \param use_reusable_pool Whether the cache buffer manager should be used.
398 * \param domain A bitmask of the RADEON_DOMAIN_* flags.
399 * \return The created buffer object.
401 struct pb_buffer
*(*buffer_create
)(struct radeon_winsys
*ws
,
404 enum radeon_bo_domain domain
,
405 enum radeon_bo_flag flags
);
408 * Map the entire data store of a buffer object into the client's address
411 * \param buf A winsys buffer object to map.
412 * \param cs A command stream to flush if the buffer is referenced by it.
413 * \param usage A bitmask of the PIPE_TRANSFER_* flags.
414 * \return The pointer at the beginning of the buffer.
416 void *(*buffer_map
)(struct pb_buffer
*buf
,
417 struct radeon_winsys_cs
*cs
,
418 enum pipe_transfer_usage usage
);
421 * Unmap a buffer object from the client's address space.
423 * \param buf A winsys buffer object to unmap.
425 void (*buffer_unmap
)(struct pb_buffer
*buf
);
428 * Wait for the buffer and return true if the buffer is not used
431 * The timeout of 0 will only return the status.
432 * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
435 bool (*buffer_wait
)(struct pb_buffer
*buf
, uint64_t timeout
,
436 enum radeon_bo_usage usage
);
439 * Return buffer metadata.
440 * (tiling info for display code, DRI sharing, and other data)
442 * \param buf A winsys buffer object to get the flags from.
445 void (*buffer_get_metadata
)(struct pb_buffer
*buf
,
446 struct radeon_bo_metadata
*md
);
449 * Set buffer metadata.
450 * (tiling info for display code, DRI sharing, and other data)
452 * \param buf A winsys buffer object to set the flags for.
455 void (*buffer_set_metadata
)(struct pb_buffer
*buf
,
456 struct radeon_bo_metadata
*md
);
459 * Get a winsys buffer from a winsys handle. The internal structure
460 * of the handle is platform-specific and only a winsys should access it.
462 * \param ws The winsys this function is called from.
463 * \param whandle A winsys handle pointer as was received from a state
465 * \param stride The returned buffer stride in bytes.
467 struct pb_buffer
*(*buffer_from_handle
)(struct radeon_winsys
*ws
,
468 struct winsys_handle
*whandle
,
469 unsigned *stride
, unsigned *offset
);
472 * Get a winsys buffer from a user pointer. The resulting buffer can't
473 * be exported. Both pointer and size must be page aligned.
475 * \param ws The winsys this function is called from.
476 * \param pointer User pointer to turn into a buffer object.
477 * \param Size Size in bytes for the new buffer.
479 struct pb_buffer
*(*buffer_from_ptr
)(struct radeon_winsys
*ws
,
480 void *pointer
, uint64_t size
);
483 * Whether the buffer was created from a user pointer.
485 * \param buf A winsys buffer object
486 * \return whether \p buf was created via buffer_from_ptr
488 bool (*buffer_is_user_ptr
)(struct pb_buffer
*buf
);
491 * Get a winsys handle from a winsys buffer. The internal structure
492 * of the handle is platform-specific and only a winsys should access it.
494 * \param buf A winsys buffer object to get the handle from.
495 * \param whandle A winsys handle pointer.
496 * \param stride A stride of the buffer in bytes, for texturing.
497 * \return true on success.
499 bool (*buffer_get_handle
)(struct pb_buffer
*buf
,
500 unsigned stride
, unsigned offset
,
502 struct winsys_handle
*whandle
);
505 * Return the virtual address of a buffer.
507 * When virtual memory is not in use, this is the offset relative to the
508 * relocation base (non-zero for sub-allocated buffers).
510 * \param buf A winsys buffer object
511 * \return virtual address
513 uint64_t (*buffer_get_virtual_address
)(struct pb_buffer
*buf
);
516 * Return the offset of this buffer relative to the relocation base.
517 * This is only non-zero for sub-allocated buffers.
519 * This is only supported in the radeon winsys, since amdgpu uses virtual
520 * addresses in submissions even for the video engines.
522 * \param buf A winsys buffer object
523 * \return the offset for relocations
525 unsigned (*buffer_get_reloc_offset
)(struct pb_buffer
*buf
);
528 * Query the initial placement of the buffer from the kernel driver.
530 enum radeon_bo_domain (*buffer_get_initial_domain
)(struct pb_buffer
*buf
);
532 /**************************************************************************
533 * Command submission.
535 * Each pipe context should create its own command stream and submit
536 * commands independently of other contexts.
537 *************************************************************************/
540 * Create a command submission context.
541 * Various command streams can be submitted to the same context.
543 struct radeon_winsys_ctx
*(*ctx_create
)(struct radeon_winsys
*ws
);
548 void (*ctx_destroy
)(struct radeon_winsys_ctx
*ctx
);
551 * Query a GPU reset status.
553 enum pipe_reset_status (*ctx_query_reset_status
)(struct radeon_winsys_ctx
*ctx
);
556 * Create a command stream.
558 * \param ctx The submission context
559 * \param ring_type The ring type (GFX, DMA, UVD)
560 * \param flush Flush callback function associated with the command stream.
561 * \param user User pointer that will be passed to the flush callback.
563 struct radeon_winsys_cs
*(*cs_create
)(struct radeon_winsys_ctx
*ctx
,
564 enum ring_type ring_type
,
565 void (*flush
)(void *ctx
, unsigned flags
,
566 struct pipe_fence_handle
**fence
),
570 * Add a constant engine IB to a graphics CS. This makes the graphics CS
571 * from "cs_create" a group of two IBs that share a buffer list and are
574 * The returned constant CS is only a stream for writing packets to the new
575 * IB. Calling other winsys functions with it is not allowed, not even
578 * In order to add buffers and check memory usage, use the graphics CS.
579 * In order to flush it, use the graphics CS, which will flush both IBs.
580 * Destroying the graphics CS will destroy both of them.
582 * \param cs The graphics CS from "cs_create" that will hold the buffer
583 * list and will be used for flushing.
585 struct radeon_winsys_cs
*(*cs_add_const_ib
)(struct radeon_winsys_cs
*cs
);
588 * Add a constant engine preamble IB to a graphics CS. This add an extra IB
589 * in similar manner to cs_add_const_ib. This should always be called after
592 * The returned IB is a constant engine IB that only gets flushed if the
595 * \param cs The graphics CS from "cs_create" that will hold the buffer
596 * list and will be used for flushing.
598 struct radeon_winsys_cs
*(*cs_add_const_preamble_ib
)(struct radeon_winsys_cs
*cs
);
600 * Destroy a command stream.
602 * \param cs A command stream to destroy.
604 void (*cs_destroy
)(struct radeon_winsys_cs
*cs
);
607 * Add a buffer. Each buffer used by a CS must be added using this function.
609 * \param cs Command stream
611 * \param usage Whether the buffer is used for read and/or write.
612 * \param domain Bitmask of the RADEON_DOMAIN_* flags.
613 * \param priority A higher number means a greater chance of being
614 * placed in the requested domain. 15 is the maximum.
615 * \return Buffer index.
617 unsigned (*cs_add_buffer
)(struct radeon_winsys_cs
*cs
,
618 struct pb_buffer
*buf
,
619 enum radeon_bo_usage usage
,
620 enum radeon_bo_domain domain
,
621 enum radeon_bo_priority priority
);
624 * Return the index of an already-added buffer.
626 * Not supported on amdgpu. Drivers with GPUVM should not care about
629 * \param cs Command stream
631 * \return The buffer index, or -1 if the buffer has not been added.
633 int (*cs_lookup_buffer
)(struct radeon_winsys_cs
*cs
,
634 struct pb_buffer
*buf
);
637 * Return true if there is enough memory in VRAM and GTT for the buffers
638 * added so far. If the validation fails, all buffers which have
639 * been added since the last call of cs_validate will be removed and
640 * the CS will be flushed (provided there are still any buffers).
642 * \param cs A command stream to validate.
644 bool (*cs_validate
)(struct radeon_winsys_cs
*cs
);
647 * Check whether the given number of dwords is available in the IB.
648 * Optionally chain a new chunk of the IB if necessary and supported.
650 * \param cs A command stream.
651 * \param dw Number of CS dwords requested by the caller.
653 bool (*cs_check_space
)(struct radeon_winsys_cs
*cs
, unsigned dw
);
656 * Return the buffer list.
658 * This is the buffer list as passed to the kernel, i.e. it only contains
659 * the parent buffers of sub-allocated buffers.
661 * \param cs Command stream
662 * \param list Returned buffer list. Set to NULL to query the count only.
663 * \return The buffer count.
665 unsigned (*cs_get_buffer_list
)(struct radeon_winsys_cs
*cs
,
666 struct radeon_bo_list_item
*list
);
669 * Flush a command stream.
671 * \param cs A command stream to flush.
672 * \param flags, RADEON_FLUSH_ASYNC or 0.
673 * \param fence Pointer to a fence. If non-NULL, a fence is inserted
674 * after the CS and is returned through this parameter.
675 * \return Negative POSIX error code or 0 for success.
676 * Asynchronous submissions never return an error.
678 int (*cs_flush
)(struct radeon_winsys_cs
*cs
,
680 struct pipe_fence_handle
**fence
);
683 * Create a fence before the CS is flushed.
684 * The user must flush manually to complete the initializaton of the fence.
685 * The fence must not be used before the flush.
687 struct pipe_fence_handle
*(*cs_get_next_fence
)(struct radeon_winsys_cs
*cs
);
690 * Return true if a buffer is referenced by a command stream.
692 * \param cs A command stream.
693 * \param buf A winsys buffer.
695 bool (*cs_is_buffer_referenced
)(struct radeon_winsys_cs
*cs
,
696 struct pb_buffer
*buf
,
697 enum radeon_bo_usage usage
);
700 * Request access to a feature for a command stream.
702 * \param cs A command stream.
703 * \param fid Feature ID, one of RADEON_FID_*
704 * \param enable Whether to enable or disable the feature.
706 bool (*cs_request_feature
)(struct radeon_winsys_cs
*cs
,
707 enum radeon_feature_id fid
,
710 * Make sure all asynchronous flush of the cs have completed
712 * \param cs A command stream.
714 void (*cs_sync_flush
)(struct radeon_winsys_cs
*cs
);
717 * Wait for the fence and return true if the fence has been signalled.
718 * The timeout of 0 will only return the status.
719 * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
722 bool (*fence_wait
)(struct radeon_winsys
*ws
,
723 struct pipe_fence_handle
*fence
,
727 * Reference counting for fences.
729 void (*fence_reference
)(struct pipe_fence_handle
**dst
,
730 struct pipe_fence_handle
*src
);
735 * \param ws The winsys this function is called from.
736 * \param tex Input texture description
737 * \param flags Bitmask of RADEON_SURF_* flags
738 * \param bpe Bytes per pixel, it can be different for Z buffers.
739 * \param mode Preferred tile mode. (linear, 1D, or 2D)
740 * \param surf Output structure
742 int (*surface_init
)(struct radeon_winsys
*ws
,
743 const struct pipe_resource
*tex
,
744 unsigned flags
, unsigned bpe
,
745 enum radeon_surf_mode mode
,
746 struct radeon_surf
*surf
);
748 uint64_t (*query_value
)(struct radeon_winsys
*ws
,
749 enum radeon_value_id value
);
751 bool (*read_registers
)(struct radeon_winsys
*ws
, unsigned reg_offset
,
752 unsigned num_registers
, uint32_t *out
);
755 static inline bool radeon_emitted(struct radeon_winsys_cs
*cs
, unsigned num_dw
)
757 return cs
&& (cs
->prev_dw
+ cs
->current
.cdw
> num_dw
);
760 static inline void radeon_emit(struct radeon_winsys_cs
*cs
, uint32_t value
)
762 cs
->current
.buf
[cs
->current
.cdw
++] = value
;
765 static inline void radeon_emit_array(struct radeon_winsys_cs
*cs
,
766 const uint32_t *values
, unsigned count
)
768 memcpy(cs
->current
.buf
+ cs
->current
.cdw
, values
, count
* 4);
769 cs
->current
.cdw
+= count
;