src/gallium/drivers/radeon/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #ifndef RADEON_WINSYS_H
  25 #define RADEON_WINSYS_H
  26
  27 /* The public winsys interface header for the radeon driver. */
  28
  29 #include "pipebuffer/pb_buffer.h"
  30
  31 #define RADEON_FLUSH_ASYNC              (1 << 0)
  32 #define RADEON_FLUSH_KEEP_TILING_FLAGS  (1 << 1)
  33 #define RADEON_FLUSH_END_OF_FRAME       (1 << 2)
  34
  35 /* Tiling flags. */
  36 enum radeon_bo_layout {
  37     RADEON_LAYOUT_LINEAR = 0,
  38     RADEON_LAYOUT_TILED,
  39     RADEON_LAYOUT_SQUARETILED,
  40
  41     RADEON_LAYOUT_UNKNOWN
  42 };
  43
  44 enum radeon_bo_domain { /* bitfield */
  45     RADEON_DOMAIN_GTT  = 2,
  46     RADEON_DOMAIN_VRAM = 4,
  47     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  48 };
  49
  50 enum radeon_bo_flag { /* bitfield */
  51     RADEON_FLAG_GTT_WC =        (1 << 0),
  52     RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  53     RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  54 };
  55
  56 enum radeon_bo_usage { /* bitfield */
  57     RADEON_USAGE_READ = 2,
  58     RADEON_USAGE_WRITE = 4,
  59     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
  60 };
  61
  62 enum radeon_family {
  63     CHIP_UNKNOWN = 0,
  64     CHIP_R300, /* R3xx-based cores. */
  65     CHIP_R350,
  66     CHIP_RV350,
  67     CHIP_RV370,
  68     CHIP_RV380,
  69     CHIP_RS400,
  70     CHIP_RC410,
  71     CHIP_RS480,
  72     CHIP_R420,     /* R4xx-based cores. */
  73     CHIP_R423,
  74     CHIP_R430,
  75     CHIP_R480,
  76     CHIP_R481,
  77     CHIP_RV410,
  78     CHIP_RS600,
  79     CHIP_RS690,
  80     CHIP_RS740,
  81     CHIP_RV515,    /* R5xx-based cores. */
  82     CHIP_R520,
  83     CHIP_RV530,
  84     CHIP_R580,
  85     CHIP_RV560,
  86     CHIP_RV570,
  87     CHIP_R600,
  88     CHIP_RV610,
  89     CHIP_RV630,
  90     CHIP_RV670,
  91     CHIP_RV620,
  92     CHIP_RV635,
  93     CHIP_RS780,
  94     CHIP_RS880,
  95     CHIP_RV770,
  96     CHIP_RV730,
  97     CHIP_RV710,
  98     CHIP_RV740,
  99     CHIP_CEDAR,
 100     CHIP_REDWOOD,
 101     CHIP_JUNIPER,
 102     CHIP_CYPRESS,
 103     CHIP_HEMLOCK,
 104     CHIP_PALM,
 105     CHIP_SUMO,
 106     CHIP_SUMO2,
 107     CHIP_BARTS,
 108     CHIP_TURKS,
 109     CHIP_CAICOS,
 110     CHIP_CAYMAN,
 111     CHIP_ARUBA,
 112     CHIP_TAHITI,
 113     CHIP_PITCAIRN,
 114     CHIP_VERDE,
 115     CHIP_OLAND,
 116     CHIP_HAINAN,
 117     CHIP_BONAIRE,
 118     CHIP_KAVERI,
 119     CHIP_KABINI,
 120     CHIP_HAWAII,
 121     CHIP_MULLINS,
 122     CHIP_TONGA,
 123     CHIP_ICELAND,
 124     CHIP_CARRIZO,
 125     CHIP_FIJI,
 126     CHIP_STONEY,
 127     CHIP_LAST,
 128 };
 129
 130 enum chip_class {
 131     CLASS_UNKNOWN = 0,
 132     R300,
 133     R400,
 134     R500,
 135     R600,
 136     R700,
 137     EVERGREEN,
 138     CAYMAN,
 139     SI,
 140     CIK,
 141     VI,
 142 };
 143
 144 enum ring_type {
 145     RING_GFX = 0,
 146     RING_COMPUTE,
 147     RING_DMA,
 148     RING_UVD,
 149     RING_VCE,
 150     RING_LAST,
 151 };
 152
 153 enum radeon_value_id {
 154     RADEON_REQUESTED_VRAM_MEMORY,
 155     RADEON_REQUESTED_GTT_MEMORY,
 156     RADEON_BUFFER_WAIT_TIME_NS,
 157     RADEON_TIMESTAMP,
 158     RADEON_NUM_CS_FLUSHES,
 159     RADEON_NUM_BYTES_MOVED,
 160     RADEON_VRAM_USAGE,
 161     RADEON_GTT_USAGE,
 162     RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
 163     RADEON_CURRENT_SCLK,
 164     RADEON_CURRENT_MCLK,
 165     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
 166 };
 167
 168 /* Each group of four has the same priority. */
 169 enum radeon_bo_priority {
 170     RADEON_PRIO_FENCE = 0,
 171     RADEON_PRIO_TRACE,
 172     RADEON_PRIO_SO_FILLED_SIZE,
 173     RADEON_PRIO_QUERY,
 174
 175     RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
 176     RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
 177     RADEON_PRIO_DRAW_INDIRECT,
 178     RADEON_PRIO_INDEX_BUFFER,
 179
 180     RADEON_PRIO_CP_DMA = 8,
 181
 182     RADEON_PRIO_VCE = 12,
 183     RADEON_PRIO_UVD,
 184     RADEON_PRIO_SDMA_BUFFER,
 185     RADEON_PRIO_SDMA_TEXTURE,
 186
 187     RADEON_PRIO_USER_SHADER = 16,
 188     RADEON_PRIO_INTERNAL_SHADER, /* fetch shader, etc. */
 189
 190     /* gap: 20 */
 191
 192     RADEON_PRIO_CONST_BUFFER = 24,
 193     RADEON_PRIO_DESCRIPTORS,
 194     RADEON_PRIO_BORDER_COLORS,
 195
 196     RADEON_PRIO_SAMPLER_BUFFER = 28,
 197     RADEON_PRIO_VERTEX_BUFFER,
 198
 199     RADEON_PRIO_SHADER_RW_BUFFER = 32,
 200     RADEON_PRIO_RINGS_STREAMOUT,
 201     RADEON_PRIO_SCRATCH_BUFFER,
 202     RADEON_PRIO_COMPUTE_GLOBAL,
 203
 204     RADEON_PRIO_SAMPLER_TEXTURE = 36,
 205     RADEON_PRIO_SHADER_RW_IMAGE,
 206
 207     RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 40,
 208
 209     RADEON_PRIO_COLOR_BUFFER = 44,
 210
 211     RADEON_PRIO_DEPTH_BUFFER = 48,
 212
 213     RADEON_PRIO_COLOR_BUFFER_MSAA = 52,
 214
 215     RADEON_PRIO_DEPTH_BUFFER_MSAA = 56,
 216
 217     RADEON_PRIO_CMASK = 60,
 218     RADEON_PRIO_DCC,
 219     RADEON_PRIO_HTILE,
 220     /* 63 is the maximum value */
 221 };
 222
 223 struct winsys_handle;
 224 struct radeon_winsys_ctx;
 225
 226 struct radeon_winsys_cs {
 227     unsigned                    cdw;  /* Number of used dwords. */
 228     unsigned                    max_dw; /* Maximum number of dwords. */
 229     uint32_t                    *buf; /* The command buffer. */
 230     enum ring_type              ring_type;
 231 };
 232
 233 struct radeon_info {
 234     /* PCI info: domain:bus:dev:func */
 235     uint32_t                    pci_domain;
 236     uint32_t                    pci_bus;
 237     uint32_t                    pci_dev;
 238     uint32_t                    pci_func;
 239
 240     /* Device info. */
 241     uint32_t                    pci_id;
 242     enum radeon_family          family;
 243     enum chip_class             chip_class;
 244     uint64_t                    gart_size;
 245     uint64_t                    vram_size;
 246     boolean                     has_virtual_memory;
 247     bool                        gfx_ib_pad_with_type2;
 248     boolean                     has_sdma;
 249     boolean                     has_uvd;
 250     uint32_t                    vce_fw_version;
 251     uint32_t                    vce_harvest_config;
 252     uint32_t                    clock_crystal_freq;
 253
 254     /* Kernel info. */
 255     uint32_t                    drm_major; /* version */
 256     uint32_t                    drm_minor;
 257     uint32_t                    drm_patchlevel;
 258     boolean                     has_userptr;
 259
 260     /* Shader cores. */
 261     uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
 262     uint32_t                    max_shader_clock;
 263     uint32_t                    num_good_compute_units;
 264     uint32_t                    max_se; /* shader engines */
 265     uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 266
 267     /* Render backends (color + depth blocks). */
 268     uint32_t                    r300_num_gb_pipes;
 269     uint32_t                    r300_num_z_pipes;
 270     uint32_t                    r600_gb_backend_map; /* R600 harvest config */
 271     boolean                     r600_gb_backend_map_valid;
 272     uint32_t                    r600_num_banks;
 273     uint32_t                    num_render_backends;
 274     uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
 275     uint32_t                    pipe_interleave_bytes;
 276     uint32_t                    enabled_rb_mask; /* GCN harvest config */
 277
 278     /* Tile modes. */
 279     boolean                     si_tile_mode_array_valid;
 280     uint32_t                    si_tile_mode_array[32];
 281     boolean                     cik_macrotile_mode_array_valid;
 282     uint32_t                    cik_macrotile_mode_array[16];
 283 };
 284
 285 /* Tiling info for display code, DRI sharing, and other data. */
 286 struct radeon_bo_metadata {
 287     /* Tiling flags describing the texture layout for display code
 288      * and DRI sharing.
 289      */
 290     enum radeon_bo_layout   microtile;
 291     enum radeon_bo_layout   macrotile;
 292     unsigned                pipe_config;
 293     unsigned                bankw;
 294     unsigned                bankh;
 295     unsigned                tile_split;
 296     unsigned                stencil_tile_split;
 297     unsigned                mtilea;
 298     unsigned                num_banks;
 299     unsigned                stride;
 300     bool                    scanout;
 301
 302     /* Additional metadata associated with the buffer, in bytes.
 303      * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 304      * Supported by amdgpu only.
 305      */
 306     uint32_t                size_metadata;
 307     uint32_t                metadata[64];
 308 };
 309
 310 enum radeon_feature_id {
 311     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 312     RADEON_FID_R300_CMASK_ACCESS,
 313 };
 314
 315 #define RADEON_SURF_MAX_LEVEL                   32
 316
 317 #define RADEON_SURF_TYPE_MASK                   0xFF
 318 #define RADEON_SURF_TYPE_SHIFT                  0
 319 #define     RADEON_SURF_TYPE_1D                     0
 320 #define     RADEON_SURF_TYPE_2D                     1
 321 #define     RADEON_SURF_TYPE_3D                     2
 322 #define     RADEON_SURF_TYPE_CUBEMAP                3
 323 #define     RADEON_SURF_TYPE_1D_ARRAY               4
 324 #define     RADEON_SURF_TYPE_2D_ARRAY               5
 325 #define RADEON_SURF_MODE_MASK                   0xFF
 326 #define RADEON_SURF_MODE_SHIFT                  8
 327 #define     RADEON_SURF_MODE_LINEAR                 0
 328 #define     RADEON_SURF_MODE_LINEAR_ALIGNED         1
 329 #define     RADEON_SURF_MODE_1D                     2
 330 #define     RADEON_SURF_MODE_2D                     3
 331 #define RADEON_SURF_SCANOUT                     (1 << 16)
 332 #define RADEON_SURF_ZBUFFER                     (1 << 17)
 333 #define RADEON_SURF_SBUFFER                     (1 << 18)
 334 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
 335 #define RADEON_SURF_HAS_SBUFFER_MIPTREE         (1 << 19)
 336 #define RADEON_SURF_HAS_TILE_MODE_INDEX         (1 << 20)
 337 #define RADEON_SURF_FMASK                       (1 << 21)
 338
 339 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
 340 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
 341 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
 342
 343 struct radeon_surf_level {
 344     uint64_t                    offset;
 345     uint64_t                    slice_size;
 346     uint32_t                    npix_x;
 347     uint32_t                    npix_y;
 348     uint32_t                    npix_z;
 349     uint32_t                    nblk_x;
 350     uint32_t                    nblk_y;
 351     uint32_t                    nblk_z;
 352     uint32_t                    pitch_bytes;
 353     uint32_t                    mode;
 354     uint64_t                    dcc_offset;
 355 };
 356
 357 struct radeon_surf {
 358     /* These are inputs to the calculator. */
 359     uint32_t                    npix_x;
 360     uint32_t                    npix_y;
 361     uint32_t                    npix_z;
 362     uint32_t                    blk_w;
 363     uint32_t                    blk_h;
 364     uint32_t                    blk_d;
 365     uint32_t                    array_size;
 366     uint32_t                    last_level;
 367     uint32_t                    bpe;
 368     uint32_t                    nsamples;
 369     uint32_t                    flags;
 370
 371     /* These are return values. Some of them can be set by the caller, but
 372      * they will be treated as hints (e.g. bankw, bankh) and might be
 373      * changed by the calculator.
 374      */
 375     uint64_t                    bo_size;
 376     uint64_t                    bo_alignment;
 377     /* This applies to EG and later. */
 378     uint32_t                    bankw;
 379     uint32_t                    bankh;
 380     uint32_t                    mtilea;
 381     uint32_t                    tile_split;
 382     uint32_t                    stencil_tile_split;
 383     uint64_t                    stencil_offset;
 384     struct radeon_surf_level    level[RADEON_SURF_MAX_LEVEL];
 385     struct radeon_surf_level    stencil_level[RADEON_SURF_MAX_LEVEL];
 386     uint32_t                    tiling_index[RADEON_SURF_MAX_LEVEL];
 387     uint32_t                    stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
 388     uint32_t                    pipe_config;
 389     uint32_t                    num_banks;
 390
 391     uint64_t                    dcc_size;
 392     uint64_t                    dcc_alignment;
 393 };
 394
 395 struct radeon_bo_list_item {
 396     struct pb_buffer *buf;
 397     uint64_t vm_address;
 398     uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
 399 };
 400
 401 struct radeon_winsys {
 402     /**
 403      * The screen object this winsys was created for
 404      */
 405     struct pipe_screen *screen;
 406
 407     /**
 408      * Decrement the winsys reference count.
 409      *
 410      * \param ws  The winsys this function is called for.
 411      * \return    True if the winsys and screen should be destroyed.
 412      */
 413     bool (*unref)(struct radeon_winsys *ws);
 414
 415     /**
 416      * Destroy this winsys.
 417      *
 418      * \param ws        The winsys this function is called from.
 419      */
 420     void (*destroy)(struct radeon_winsys *ws);
 421
 422     /**
 423      * Query an info structure from winsys.
 424      *
 425      * \param ws        The winsys this function is called from.
 426      * \param info      Return structure
 427      */
 428     void (*query_info)(struct radeon_winsys *ws,
 429                        struct radeon_info *info);
 430
 431     /**************************************************************************
 432      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 433      *
 434      * Remember that gallium gets to choose the interface it needs, and the
 435      * window systems must then implement that interface (rather than the
 436      * other way around...).
 437      *************************************************************************/
 438
 439     /**
 440      * Create a buffer object.
 441      *
 442      * \param ws        The winsys this function is called from.
 443      * \param size      The size to allocate.
 444      * \param alignment An alignment of the buffer in memory.
 445      * \param use_reusable_pool Whether the cache buffer manager should be used.
 446      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 447      * \return          The created buffer object.
 448      */
 449     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 450                                        unsigned size,
 451                                        unsigned alignment,
 452                                        boolean use_reusable_pool,
 453                                        enum radeon_bo_domain domain,
 454                                        enum radeon_bo_flag flags);
 455
 456     /**
 457      * Map the entire data store of a buffer object into the client's address
 458      * space.
 459      *
 460      * \param buf       A winsys buffer object to map.
 461      * \param cs        A command stream to flush if the buffer is referenced by it.
 462      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 463      * \return          The pointer at the beginning of the buffer.
 464      */
 465     void *(*buffer_map)(struct pb_buffer *buf,
 466                         struct radeon_winsys_cs *cs,
 467                         enum pipe_transfer_usage usage);
 468
 469     /**
 470      * Unmap a buffer object from the client's address space.
 471      *
 472      * \param buf       A winsys buffer object to unmap.
 473      */
 474     void (*buffer_unmap)(struct pb_buffer *buf);
 475
 476     /**
 477      * Wait for the buffer and return true if the buffer is not used
 478      * by the device.
 479      *
 480      * The timeout of 0 will only return the status.
 481      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
 482      * is idle.
 483      */
 484     bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
 485                         enum radeon_bo_usage usage);
 486
 487     /**
 488      * Return buffer metadata.
 489      * (tiling info for display code, DRI sharing, and other data)
 490      *
 491      * \param buf       A winsys buffer object to get the flags from.
 492      * \param md        Metadata
 493      */
 494     void (*buffer_get_metadata)(struct pb_buffer *buf,
 495                                 struct radeon_bo_metadata *md);
 496
 497     /**
 498      * Set buffer metadata.
 499      * (tiling info for display code, DRI sharing, and other data)
 500      *
 501      * \param buf       A winsys buffer object to set the flags for.
 502      * \param md        Metadata
 503      */
 504     void (*buffer_set_metadata)(struct pb_buffer *buf,
 505                                 struct radeon_bo_metadata *md);
 506
 507     /**
 508      * Get a winsys buffer from a winsys handle. The internal structure
 509      * of the handle is platform-specific and only a winsys should access it.
 510      *
 511      * \param ws        The winsys this function is called from.
 512      * \param whandle   A winsys handle pointer as was received from a state
 513      *                  tracker.
 514      * \param stride    The returned buffer stride in bytes.
 515      */
 516     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 517                                             struct winsys_handle *whandle,
 518                                             unsigned *stride, unsigned *offset);
 519
 520     /**
 521      * Get a winsys buffer from a user pointer. The resulting buffer can't
 522      * be exported. Both pointer and size must be page aligned.
 523      *
 524      * \param ws        The winsys this function is called from.
 525      * \param pointer   User pointer to turn into a buffer object.
 526      * \param Size      Size in bytes for the new buffer.
 527      */
 528     struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
 529                                          void *pointer, unsigned size);
 530
 531     /**
 532      * Whether the buffer was created from a user pointer.
 533      *
 534      * \param buf       A winsys buffer object
 535      * \return          whether \p buf was created via buffer_from_ptr
 536      */
 537     bool (*buffer_is_user_ptr)(struct pb_buffer *buf);
 538
 539     /**
 540      * Get a winsys handle from a winsys buffer. The internal structure
 541      * of the handle is platform-specific and only a winsys should access it.
 542      *
 543      * \param buf       A winsys buffer object to get the handle from.
 544      * \param whandle   A winsys handle pointer.
 545      * \param stride    A stride of the buffer in bytes, for texturing.
 546      * \return          TRUE on success.
 547      */
 548     boolean (*buffer_get_handle)(struct pb_buffer *buf,
 549                                  unsigned stride, unsigned offset,
 550                                  unsigned slice_size,
 551                                  struct winsys_handle *whandle);
 552
 553     /**
 554      * Return the virtual address of a buffer.
 555      *
 556      * \param buf       A winsys buffer object
 557      * \return          virtual address
 558      */
 559     uint64_t (*buffer_get_virtual_address)(struct pb_buffer *buf);
 560
 561     /**
 562      * Query the initial placement of the buffer from the kernel driver.
 563      */
 564     enum radeon_bo_domain (*buffer_get_initial_domain)(struct pb_buffer *buf);
 565
 566     /**************************************************************************
 567      * Command submission.
 568      *
 569      * Each pipe context should create its own command stream and submit
 570      * commands independently of other contexts.
 571      *************************************************************************/
 572
 573     /**
 574      * Create a command submission context.
 575      * Various command streams can be submitted to the same context.
 576      */
 577     struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 578
 579     /**
 580      * Destroy a context.
 581      */
 582     void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 583
 584     /**
 585      * Query a GPU reset status.
 586      */
 587     enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
 588
 589     /**
 590      * Create a command stream.
 591      *
 592      * \param ctx       The submission context
 593      * \param ring_type The ring type (GFX, DMA, UVD)
 594      * \param flush     Flush callback function associated with the command stream.
 595      * \param user      User pointer that will be passed to the flush callback.
 596      */
 597     struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys_ctx *ctx,
 598                                           enum ring_type ring_type,
 599                                           void (*flush)(void *ctx, unsigned flags,
 600                                                         struct pipe_fence_handle **fence),
 601                                           void *flush_ctx);
 602
 603     /**
 604      * Destroy a command stream.
 605      *
 606      * \param cs        A command stream to destroy.
 607      */
 608     void (*cs_destroy)(struct radeon_winsys_cs *cs);
 609
 610     /**
 611      * Add a buffer. Each buffer used by a CS must be added using this function.
 612      *
 613      * \param cs      Command stream
 614      * \param buf     Buffer
 615      * \param usage   Whether the buffer is used for read and/or write.
 616      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 617      * \param priority  A higher number means a greater chance of being
 618      *                  placed in the requested domain. 15 is the maximum.
 619      * \return Buffer index.
 620      */
 621     unsigned (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 622                              struct pb_buffer *buf,
 623                              enum radeon_bo_usage usage,
 624                              enum radeon_bo_domain domain,
 625                              enum radeon_bo_priority priority);
 626
 627     /**
 628      * Return the index of an already-added buffer.
 629      *
 630      * \param cs        Command stream
 631      * \param buf       Buffer
 632      * \return          The buffer index, or -1 if the buffer has not been added.
 633      */
 634     int (*cs_lookup_buffer)(struct radeon_winsys_cs *cs,
 635                             struct pb_buffer *buf);
 636
 637     /**
 638      * Return TRUE if there is enough memory in VRAM and GTT for the buffers
 639      * added so far. If the validation fails, all buffers which have
 640      * been added since the last call of cs_validate will be removed and
 641      * the CS will be flushed (provided there are still any buffers).
 642      *
 643      * \param cs        A command stream to validate.
 644      */
 645     boolean (*cs_validate)(struct radeon_winsys_cs *cs);
 646
 647     /**
 648      * Return TRUE if there is enough memory in VRAM and GTT for the buffers
 649      * added so far.
 650      *
 651      * \param cs        A command stream to validate.
 652      * \param vram      VRAM memory size pending to be use
 653      * \param gtt       GTT memory size pending to be use
 654      */
 655     boolean (*cs_memory_below_limit)(struct radeon_winsys_cs *cs, uint64_t vram, uint64_t gtt);
 656
 657     /**
 658      * Return the buffer list.
 659      *
 660      * \param cs    Command stream
 661      * \param list  Returned buffer list. Set to NULL to query the count only.
 662      * \return      The buffer count.
 663      */
 664     unsigned (*cs_get_buffer_list)(struct radeon_winsys_cs *cs,
 665                                    struct radeon_bo_list_item *list);
 666
 667     /**
 668      * Flush a command stream.
 669      *
 670      * \param cs          A command stream to flush.
 671      * \param flags,      RADEON_FLUSH_ASYNC or 0.
 672      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 673      *                    after the CS and is returned through this parameter.
 674      */
 675     void (*cs_flush)(struct radeon_winsys_cs *cs,
 676                      unsigned flags,
 677                      struct pipe_fence_handle **fence);
 678
 679     /**
 680      * Return TRUE if a buffer is referenced by a command stream.
 681      *
 682      * \param cs        A command stream.
 683      * \param buf       A winsys buffer.
 684      */
 685     boolean (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
 686                                        struct pb_buffer *buf,
 687                                        enum radeon_bo_usage usage);
 688
 689     /**
 690      * Request access to a feature for a command stream.
 691      *
 692      * \param cs        A command stream.
 693      * \param fid       Feature ID, one of RADEON_FID_*
 694      * \param enable    Whether to enable or disable the feature.
 695      */
 696     boolean (*cs_request_feature)(struct radeon_winsys_cs *cs,
 697                                   enum radeon_feature_id fid,
 698                                   boolean enable);
 699      /**
 700       * Make sure all asynchronous flush of the cs have completed
 701       *
 702       * \param cs        A command stream.
 703       */
 704     void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
 705
 706     /**
 707      * Wait for the fence and return true if the fence has been signalled.
 708      * The timeout of 0 will only return the status.
 709      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 710      * is signalled.
 711      */
 712     bool (*fence_wait)(struct radeon_winsys *ws,
 713                        struct pipe_fence_handle *fence,
 714                        uint64_t timeout);
 715
 716     /**
 717      * Reference counting for fences.
 718      */
 719     void (*fence_reference)(struct pipe_fence_handle **dst,
 720                             struct pipe_fence_handle *src);
 721
 722     /**
 723      * Initialize surface
 724      *
 725      * \param ws        The winsys this function is called from.
 726      * \param surf      Surface structure ptr
 727      */
 728     int (*surface_init)(struct radeon_winsys *ws,
 729                         struct radeon_surf *surf);
 730
 731     /**
 732      * Find best values for a surface
 733      *
 734      * \param ws        The winsys this function is called from.
 735      * \param surf      Surface structure ptr
 736      */
 737     int (*surface_best)(struct radeon_winsys *ws,
 738                         struct radeon_surf *surf);
 739
 740     uint64_t (*query_value)(struct radeon_winsys *ws,
 741                             enum radeon_value_id value);
 742
 743     bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 744                            unsigned num_registers, uint32_t *out);
 745 };
 746
 747
 748 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 749 {
 750     cs->buf[cs->cdw++] = value;
 751 }
 752
 753 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 754                                      const uint32_t *values, unsigned count)
 755 {
 756     memcpy(cs->buf+cs->cdw, values, count * 4);
 757     cs->cdw += count;
 758 }
 759
 760 #endif