src/gallium/drivers/radeon/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  * Copyright 2018 Advanced Micro Devices, Inc.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * on the rights to use, copy, modify, merge, publish, distribute, sub
  11  * license, and/or sell copies of the Software, and to permit persons to whom
  12  * the Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  25
  26 #ifndef RADEON_WINSYS_H
  27 #define RADEON_WINSYS_H
  28
  29 /* The public winsys interface header for the radeon driver. */
  30
  31 /* Whether the next IB can start immediately and not wait for draws and
  32  * dispatches from the current IB to finish. */
  33 #define RADEON_FLUSH_START_NEXT_GFX_IB_NOW      (1u << 31)
  34
  35 #define RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW \
  36         (PIPE_FLUSH_ASYNC | RADEON_FLUSH_START_NEXT_GFX_IB_NOW)
  37
  38 #include "pipebuffer/pb_buffer.h"
  39
  40 #include "amd/common/ac_gpu_info.h"
  41 #include "amd/common/ac_surface.h"
  42
  43 /* Tiling flags. */
  44 enum radeon_bo_layout {
  45     RADEON_LAYOUT_LINEAR = 0,
  46     RADEON_LAYOUT_TILED,
  47     RADEON_LAYOUT_SQUARETILED,
  48
  49     RADEON_LAYOUT_UNKNOWN
  50 };
  51
  52 enum radeon_bo_domain { /* bitfield */
  53     RADEON_DOMAIN_GTT  = 2,
  54     RADEON_DOMAIN_VRAM = 4,
  55     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  56 };
  57
  58 enum radeon_bo_flag { /* bitfield */
  59     RADEON_FLAG_GTT_WC =        (1 << 0),
  60     RADEON_FLAG_NO_CPU_ACCESS = (1 << 1),
  61     RADEON_FLAG_NO_SUBALLOC =   (1 << 2),
  62     RADEON_FLAG_SPARSE =        (1 << 3),
  63     RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 4),
  64     RADEON_FLAG_READ_ONLY =     (1 << 5),
  65     RADEON_FLAG_32BIT =    (1 << 6),
  66 };
  67
  68 enum radeon_bo_usage { /* bitfield */
  69     RADEON_USAGE_READ = 2,
  70     RADEON_USAGE_WRITE = 4,
  71     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE,
  72
  73     /* The winsys ensures that the CS submission will be scheduled after
  74      * previously flushed CSs referencing this BO in a conflicting way.
  75      */
  76     RADEON_USAGE_SYNCHRONIZED = 8
  77 };
  78
  79 #define RADEON_SPARSE_PAGE_SIZE (64 * 1024)
  80
  81 enum ring_type {
  82     RING_GFX = 0,
  83     RING_COMPUTE,
  84     RING_DMA,
  85     RING_UVD,
  86     RING_VCE,
  87     RING_UVD_ENC,
  88     RING_VCN_DEC,
  89     RING_VCN_ENC,
  90     RING_LAST,
  91 };
  92
  93 enum radeon_value_id {
  94     RADEON_REQUESTED_VRAM_MEMORY,
  95     RADEON_REQUESTED_GTT_MEMORY,
  96     RADEON_MAPPED_VRAM,
  97     RADEON_MAPPED_GTT,
  98     RADEON_BUFFER_WAIT_TIME_NS,
  99     RADEON_NUM_MAPPED_BUFFERS,
 100     RADEON_TIMESTAMP,
 101     RADEON_NUM_GFX_IBS,
 102     RADEON_NUM_SDMA_IBS,
 103     RADEON_GFX_BO_LIST_COUNTER, /* number of BOs submitted in gfx IBs */
 104     RADEON_GFX_IB_SIZE_COUNTER,
 105     RADEON_NUM_BYTES_MOVED,
 106     RADEON_NUM_EVICTIONS,
 107     RADEON_NUM_VRAM_CPU_PAGE_FAULTS,
 108     RADEON_VRAM_USAGE,
 109     RADEON_VRAM_VIS_USAGE,
 110     RADEON_GTT_USAGE,
 111     RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
 112     RADEON_CURRENT_SCLK,
 113     RADEON_CURRENT_MCLK,
 114     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
 115     RADEON_CS_THREAD_TIME,
 116 };
 117
 118 /* Each group of four has the same priority. */
 119 enum radeon_bo_priority {
 120     RADEON_PRIO_FENCE = 0,
 121     RADEON_PRIO_TRACE,
 122     RADEON_PRIO_SO_FILLED_SIZE,
 123     RADEON_PRIO_QUERY,
 124
 125     RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
 126     RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
 127     RADEON_PRIO_DRAW_INDIRECT,
 128     RADEON_PRIO_INDEX_BUFFER,
 129
 130     RADEON_PRIO_CP_DMA = 12,
 131
 132     RADEON_PRIO_CONST_BUFFER = 16,
 133     RADEON_PRIO_DESCRIPTORS,
 134     RADEON_PRIO_BORDER_COLORS,
 135
 136     RADEON_PRIO_SAMPLER_BUFFER = 20,
 137     RADEON_PRIO_VERTEX_BUFFER,
 138
 139     RADEON_PRIO_SHADER_RW_BUFFER = 24,
 140     RADEON_PRIO_COMPUTE_GLOBAL,
 141
 142     RADEON_PRIO_SAMPLER_TEXTURE = 28,
 143     RADEON_PRIO_SHADER_RW_IMAGE,
 144
 145     RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 32,
 146
 147     RADEON_PRIO_COLOR_BUFFER = 36,
 148
 149     RADEON_PRIO_DEPTH_BUFFER = 40,
 150
 151     RADEON_PRIO_COLOR_BUFFER_MSAA = 44,
 152
 153     RADEON_PRIO_DEPTH_BUFFER_MSAA = 48,
 154
 155     RADEON_PRIO_CMASK = 52,
 156     RADEON_PRIO_DCC,
 157     RADEON_PRIO_HTILE,
 158     RADEON_PRIO_SHADER_BINARY, /* the hw can't hide instruction cache misses */
 159
 160     RADEON_PRIO_SHADER_RINGS = 56,
 161
 162     RADEON_PRIO_SCRATCH_BUFFER = 60,
 163     /* 63 is the maximum value */
 164 };
 165
 166 struct winsys_handle;
 167 struct radeon_winsys_ctx;
 168
 169 struct radeon_cmdbuf_chunk {
 170     unsigned cdw;  /* Number of used dwords. */
 171     unsigned max_dw; /* Maximum number of dwords. */
 172     uint32_t *buf; /* The base pointer of the chunk. */
 173 };
 174
 175 struct radeon_cmdbuf {
 176     struct radeon_cmdbuf_chunk current;
 177     struct radeon_cmdbuf_chunk *prev;
 178     unsigned                      num_prev; /* Number of previous chunks. */
 179     unsigned                      max_prev; /* Space in array pointed to by prev. */
 180     unsigned                      prev_dw; /* Total number of dwords in previous chunks. */
 181
 182     /* Memory usage of the buffer list. These are always 0 for preamble IBs. */
 183     uint64_t                      used_vram;
 184     uint64_t                      used_gart;
 185 };
 186
 187 /* Tiling info for display code, DRI sharing, and other data. */
 188 struct radeon_bo_metadata {
 189     /* Tiling flags describing the texture layout for display code
 190      * and DRI sharing.
 191      */
 192     union {
 193         struct {
 194             enum radeon_bo_layout   microtile;
 195             enum radeon_bo_layout   macrotile;
 196             unsigned                pipe_config;
 197             unsigned                bankw;
 198             unsigned                bankh;
 199             unsigned                tile_split;
 200             unsigned                mtilea;
 201             unsigned                num_banks;
 202             unsigned                stride;
 203             bool                    scanout;
 204         } legacy;
 205
 206         struct {
 207             /* surface flags */
 208             unsigned swizzle_mode:5;
 209         } gfx9;
 210     } u;
 211
 212     /* Additional metadata associated with the buffer, in bytes.
 213      * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 214      * Supported by amdgpu only.
 215      */
 216     uint32_t                size_metadata;
 217     uint32_t                metadata[64];
 218 };
 219
 220 enum radeon_feature_id {
 221     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 222     RADEON_FID_R300_CMASK_ACCESS,
 223 };
 224
 225 struct radeon_bo_list_item {
 226     uint64_t bo_size;
 227     uint64_t vm_address;
 228     uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
 229 };
 230
 231 struct radeon_winsys {
 232     /**
 233      * The screen object this winsys was created for
 234      */
 235     struct pipe_screen *screen;
 236
 237     /**
 238      * Decrement the winsys reference count.
 239      *
 240      * \param ws  The winsys this function is called for.
 241      * \return    True if the winsys and screen should be destroyed.
 242      */
 243     bool (*unref)(struct radeon_winsys *ws);
 244
 245     /**
 246      * Destroy this winsys.
 247      *
 248      * \param ws        The winsys this function is called from.
 249      */
 250     void (*destroy)(struct radeon_winsys *ws);
 251
 252     /**
 253      * Query an info structure from winsys.
 254      *
 255      * \param ws        The winsys this function is called from.
 256      * \param info      Return structure
 257      */
 258     void (*query_info)(struct radeon_winsys *ws,
 259                        struct radeon_info *info);
 260
 261     /**************************************************************************
 262      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 263      *
 264      * Remember that gallium gets to choose the interface it needs, and the
 265      * window systems must then implement that interface (rather than the
 266      * other way around...).
 267      *************************************************************************/
 268
 269     /**
 270      * Create a buffer object.
 271      *
 272      * \param ws        The winsys this function is called from.
 273      * \param size      The size to allocate.
 274      * \param alignment An alignment of the buffer in memory.
 275      * \param use_reusable_pool Whether the cache buffer manager should be used.
 276      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 277      * \return          The created buffer object.
 278      */
 279     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 280                                        uint64_t size,
 281                                        unsigned alignment,
 282                                        enum radeon_bo_domain domain,
 283                                        enum radeon_bo_flag flags);
 284
 285     /**
 286      * Map the entire data store of a buffer object into the client's address
 287      * space.
 288      *
 289      * \param buf       A winsys buffer object to map.
 290      * \param cs        A command stream to flush if the buffer is referenced by it.
 291      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 292      * \return          The pointer at the beginning of the buffer.
 293      */
 294     void *(*buffer_map)(struct pb_buffer *buf,
 295                         struct radeon_cmdbuf *cs,
 296                         enum pipe_transfer_usage usage);
 297
 298     /**
 299      * Unmap a buffer object from the client's address space.
 300      *
 301      * \param buf       A winsys buffer object to unmap.
 302      */
 303     void (*buffer_unmap)(struct pb_buffer *buf);
 304
 305     /**
 306      * Wait for the buffer and return true if the buffer is not used
 307      * by the device.
 308      *
 309      * The timeout of 0 will only return the status.
 310      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
 311      * is idle.
 312      */
 313     bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
 314                         enum radeon_bo_usage usage);
 315
 316     /**
 317      * Return buffer metadata.
 318      * (tiling info for display code, DRI sharing, and other data)
 319      *
 320      * \param buf       A winsys buffer object to get the flags from.
 321      * \param md        Metadata
 322      */
 323     void (*buffer_get_metadata)(struct pb_buffer *buf,
 324                                 struct radeon_bo_metadata *md);
 325
 326     /**
 327      * Set buffer metadata.
 328      * (tiling info for display code, DRI sharing, and other data)
 329      *
 330      * \param buf       A winsys buffer object to set the flags for.
 331      * \param md        Metadata
 332      */
 333     void (*buffer_set_metadata)(struct pb_buffer *buf,
 334                                 struct radeon_bo_metadata *md);
 335
 336     /**
 337      * Get a winsys buffer from a winsys handle. The internal structure
 338      * of the handle is platform-specific and only a winsys should access it.
 339      *
 340      * \param ws        The winsys this function is called from.
 341      * \param whandle   A winsys handle pointer as was received from a state
 342      *                  tracker.
 343      * \param stride    The returned buffer stride in bytes.
 344      */
 345     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 346                                             struct winsys_handle *whandle,
 347                                             unsigned *stride, unsigned *offset);
 348
 349     /**
 350      * Get a winsys buffer from a user pointer. The resulting buffer can't
 351      * be exported. Both pointer and size must be page aligned.
 352      *
 353      * \param ws        The winsys this function is called from.
 354      * \param pointer   User pointer to turn into a buffer object.
 355      * \param Size      Size in bytes for the new buffer.
 356      */
 357     struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
 358                                          void *pointer, uint64_t size);
 359
 360     /**
 361      * Whether the buffer was created from a user pointer.
 362      *
 363      * \param buf       A winsys buffer object
 364      * \return          whether \p buf was created via buffer_from_ptr
 365      */
 366     bool (*buffer_is_user_ptr)(struct pb_buffer *buf);
 367
 368     /** Whether the buffer was suballocated. */
 369     bool (*buffer_is_suballocated)(struct pb_buffer *buf);
 370
 371     /**
 372      * Get a winsys handle from a winsys buffer. The internal structure
 373      * of the handle is platform-specific and only a winsys should access it.
 374      *
 375      * \param buf       A winsys buffer object to get the handle from.
 376      * \param whandle   A winsys handle pointer.
 377      * \param stride    A stride of the buffer in bytes, for texturing.
 378      * \return          true on success.
 379      */
 380     bool (*buffer_get_handle)(struct pb_buffer *buf,
 381                               unsigned stride, unsigned offset,
 382                               unsigned slice_size,
 383                               struct winsys_handle *whandle);
 384
 385     /**
 386      * Change the commitment of a (64KB-page aligned) region of the given
 387      * sparse buffer.
 388      *
 389      * \warning There is no automatic synchronization with command submission.
 390      *
 391      * \note Only implemented by the amdgpu winsys.
 392      *
 393      * \return false on out of memory or other failure, true on success.
 394      */
 395     bool (*buffer_commit)(struct pb_buffer *buf,
 396                           uint64_t offset, uint64_t size,
 397                           bool commit);
 398
 399     /**
 400      * Return the virtual address of a buffer.
 401      *
 402      * When virtual memory is not in use, this is the offset relative to the
 403      * relocation base (non-zero for sub-allocated buffers).
 404      *
 405      * \param buf       A winsys buffer object
 406      * \return          virtual address
 407      */
 408     uint64_t (*buffer_get_virtual_address)(struct pb_buffer *buf);
 409
 410     /**
 411      * Return the offset of this buffer relative to the relocation base.
 412      * This is only non-zero for sub-allocated buffers.
 413      *
 414      * This is only supported in the radeon winsys, since amdgpu uses virtual
 415      * addresses in submissions even for the video engines.
 416      *
 417      * \param buf      A winsys buffer object
 418      * \return         the offset for relocations
 419      */
 420     unsigned (*buffer_get_reloc_offset)(struct pb_buffer *buf);
 421
 422     /**
 423      * Query the initial placement of the buffer from the kernel driver.
 424      */
 425     enum radeon_bo_domain (*buffer_get_initial_domain)(struct pb_buffer *buf);
 426
 427     /**************************************************************************
 428      * Command submission.
 429      *
 430      * Each pipe context should create its own command stream and submit
 431      * commands independently of other contexts.
 432      *************************************************************************/
 433
 434     /**
 435      * Create a command submission context.
 436      * Various command streams can be submitted to the same context.
 437      */
 438     struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 439
 440     /**
 441      * Destroy a context.
 442      */
 443     void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 444
 445     /**
 446      * Query a GPU reset status.
 447      */
 448     enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
 449
 450     /**
 451      * Create a command stream.
 452      *
 453      * \param ctx       The submission context
 454      * \param ring_type The ring type (GFX, DMA, UVD)
 455      * \param flush     Flush callback function associated with the command stream.
 456      * \param user      User pointer that will be passed to the flush callback.
 457      */
 458     struct radeon_cmdbuf *(*cs_create)(struct radeon_winsys_ctx *ctx,
 459                                           enum ring_type ring_type,
 460                                           void (*flush)(void *ctx, unsigned flags,
 461                                                         struct pipe_fence_handle **fence),
 462                                           void *flush_ctx);
 463
 464     /**
 465      * Destroy a command stream.
 466      *
 467      * \param cs        A command stream to destroy.
 468      */
 469     void (*cs_destroy)(struct radeon_cmdbuf *cs);
 470
 471     /**
 472      * Add a buffer. Each buffer used by a CS must be added using this function.
 473      *
 474      * \param cs      Command stream
 475      * \param buf     Buffer
 476      * \param usage   Whether the buffer is used for read and/or write.
 477      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 478      * \param priority  A higher number means a greater chance of being
 479      *                  placed in the requested domain. 15 is the maximum.
 480      * \return Buffer index.
 481      */
 482     unsigned (*cs_add_buffer)(struct radeon_cmdbuf *cs,
 483                              struct pb_buffer *buf,
 484                              enum radeon_bo_usage usage,
 485                              enum radeon_bo_domain domain,
 486                              enum radeon_bo_priority priority);
 487
 488     /**
 489      * Return the index of an already-added buffer.
 490      *
 491      * Not supported on amdgpu. Drivers with GPUVM should not care about
 492      * buffer indices.
 493      *
 494      * \param cs        Command stream
 495      * \param buf       Buffer
 496      * \return          The buffer index, or -1 if the buffer has not been added.
 497      */
 498     int (*cs_lookup_buffer)(struct radeon_cmdbuf *cs,
 499                             struct pb_buffer *buf);
 500
 501     /**
 502      * Return true if there is enough memory in VRAM and GTT for the buffers
 503      * added so far. If the validation fails, all buffers which have
 504      * been added since the last call of cs_validate will be removed and
 505      * the CS will be flushed (provided there are still any buffers).
 506      *
 507      * \param cs        A command stream to validate.
 508      */
 509     bool (*cs_validate)(struct radeon_cmdbuf *cs);
 510
 511     /**
 512      * Check whether the given number of dwords is available in the IB.
 513      * Optionally chain a new chunk of the IB if necessary and supported.
 514      *
 515      * \param cs        A command stream.
 516      * \param dw        Number of CS dwords requested by the caller.
 517      */
 518     bool (*cs_check_space)(struct radeon_cmdbuf *cs, unsigned dw);
 519
 520     /**
 521      * Return the buffer list.
 522      *
 523      * This is the buffer list as passed to the kernel, i.e. it only contains
 524      * the parent buffers of sub-allocated buffers.
 525      *
 526      * \param cs    Command stream
 527      * \param list  Returned buffer list. Set to NULL to query the count only.
 528      * \return      The buffer count.
 529      */
 530     unsigned (*cs_get_buffer_list)(struct radeon_cmdbuf *cs,
 531                                    struct radeon_bo_list_item *list);
 532
 533     /**
 534      * Flush a command stream.
 535      *
 536      * \param cs          A command stream to flush.
 537      * \param flags,      PIPE_FLUSH_* flags.
 538      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 539      *                    after the CS and is returned through this parameter.
 540      * \return Negative POSIX error code or 0 for success.
 541      *         Asynchronous submissions never return an error.
 542      */
 543     int (*cs_flush)(struct radeon_cmdbuf *cs,
 544                     unsigned flags,
 545                     struct pipe_fence_handle **fence);
 546
 547     /**
 548      * Create a fence before the CS is flushed.
 549      * The user must flush manually to complete the initializaton of the fence.
 550      *
 551      * The fence must not be used for anything except \ref cs_add_fence_dependency
 552      * before the flush.
 553      */
 554     struct pipe_fence_handle *(*cs_get_next_fence)(struct radeon_cmdbuf *cs);
 555
 556     /**
 557      * Return true if a buffer is referenced by a command stream.
 558      *
 559      * \param cs        A command stream.
 560      * \param buf       A winsys buffer.
 561      */
 562     bool (*cs_is_buffer_referenced)(struct radeon_cmdbuf *cs,
 563                                     struct pb_buffer *buf,
 564                                     enum radeon_bo_usage usage);
 565
 566     /**
 567      * Request access to a feature for a command stream.
 568      *
 569      * \param cs        A command stream.
 570      * \param fid       Feature ID, one of RADEON_FID_*
 571      * \param enable    Whether to enable or disable the feature.
 572      */
 573     bool (*cs_request_feature)(struct radeon_cmdbuf *cs,
 574                                enum radeon_feature_id fid,
 575                                bool enable);
 576      /**
 577       * Make sure all asynchronous flush of the cs have completed
 578       *
 579       * \param cs        A command stream.
 580       */
 581     void (*cs_sync_flush)(struct radeon_cmdbuf *cs);
 582
 583     /**
 584      * Add a fence dependency to the CS, so that the CS will wait for
 585      * the fence before execution.
 586      */
 587     void (*cs_add_fence_dependency)(struct radeon_cmdbuf *cs,
 588                                     struct pipe_fence_handle *fence);
 589
 590     /**
 591      * Signal a syncobj when the CS finishes execution.
 592      */
 593     void (*cs_add_syncobj_signal)(struct radeon_cmdbuf *cs,
 594                                   struct pipe_fence_handle *fence);
 595
 596     /**
 597      * Wait for the fence and return true if the fence has been signalled.
 598      * The timeout of 0 will only return the status.
 599      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 600      * is signalled.
 601      */
 602     bool (*fence_wait)(struct radeon_winsys *ws,
 603                        struct pipe_fence_handle *fence,
 604                        uint64_t timeout);
 605
 606     /**
 607      * Reference counting for fences.
 608      */
 609     void (*fence_reference)(struct pipe_fence_handle **dst,
 610                             struct pipe_fence_handle *src);
 611
 612     /**
 613      * Create a new fence object corresponding to the given syncobj fd.
 614      */
 615     struct pipe_fence_handle *(*fence_import_syncobj)(struct radeon_winsys *ws,
 616                                                       int fd);
 617
 618     /**
 619      * Create a new fence object corresponding to the given sync_file.
 620      */
 621     struct pipe_fence_handle *(*fence_import_sync_file)(struct radeon_winsys *ws,
 622                                                         int fd);
 623
 624     /**
 625      * Return a sync_file FD corresponding to the given fence object.
 626      */
 627     int (*fence_export_sync_file)(struct radeon_winsys *ws,
 628                                   struct pipe_fence_handle *fence);
 629
 630     /**
 631      * Return a sync file FD that is already signalled.
 632      */
 633     int (*export_signalled_sync_file)(struct radeon_winsys *ws);
 634
 635     /**
 636      * Initialize surface
 637      *
 638      * \param ws        The winsys this function is called from.
 639      * \param tex       Input texture description
 640      * \param flags     Bitmask of RADEON_SURF_* flags
 641      * \param bpe       Bytes per pixel, it can be different for Z buffers.
 642      * \param mode      Preferred tile mode. (linear, 1D, or 2D)
 643      * \param surf      Output structure
 644      */
 645     int (*surface_init)(struct radeon_winsys *ws,
 646                         const struct pipe_resource *tex,
 647                         unsigned num_color_samples,
 648                         unsigned flags, unsigned bpe,
 649                         enum radeon_surf_mode mode,
 650                         struct radeon_surf *surf);
 651
 652     uint64_t (*query_value)(struct radeon_winsys *ws,
 653                             enum radeon_value_id value);
 654
 655     bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 656                            unsigned num_registers, uint32_t *out);
 657
 658     const char* (*get_chip_name)(struct radeon_winsys *ws);
 659 };
 660
 661 static inline bool radeon_emitted(struct radeon_cmdbuf *cs, unsigned num_dw)
 662 {
 663     return cs && (cs->prev_dw + cs->current.cdw > num_dw);
 664 }
 665
 666 static inline void radeon_emit(struct radeon_cmdbuf *cs, uint32_t value)
 667 {
 668     cs->current.buf[cs->current.cdw++] = value;
 669 }
 670
 671 static inline void radeon_emit_array(struct radeon_cmdbuf *cs,
 672                                      const uint32_t *values, unsigned count)
 673 {
 674     memcpy(cs->current.buf + cs->current.cdw, values, count * 4);
 675     cs->current.cdw += count;
 676 }
 677
 678 enum radeon_heap {
 679     RADEON_HEAP_VRAM_NO_CPU_ACCESS,
 680     RADEON_HEAP_VRAM_READ_ONLY,
 681     RADEON_HEAP_VRAM_READ_ONLY_32BIT,
 682     RADEON_HEAP_VRAM_32BIT,
 683     RADEON_HEAP_VRAM,
 684     RADEON_HEAP_GTT_WC,
 685     RADEON_HEAP_GTT_WC_READ_ONLY,
 686     RADEON_HEAP_GTT_WC_READ_ONLY_32BIT,
 687     RADEON_HEAP_GTT_WC_32BIT,
 688     RADEON_HEAP_GTT,
 689     RADEON_MAX_SLAB_HEAPS,
 690     RADEON_MAX_CACHED_HEAPS = RADEON_MAX_SLAB_HEAPS,
 691 };
 692
 693 static inline enum radeon_bo_domain radeon_domain_from_heap(enum radeon_heap heap)
 694 {
 695     switch (heap) {
 696     case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
 697     case RADEON_HEAP_VRAM_READ_ONLY:
 698     case RADEON_HEAP_VRAM_READ_ONLY_32BIT:
 699     case RADEON_HEAP_VRAM_32BIT:
 700     case RADEON_HEAP_VRAM:
 701         return RADEON_DOMAIN_VRAM;
 702     case RADEON_HEAP_GTT_WC:
 703     case RADEON_HEAP_GTT_WC_READ_ONLY:
 704     case RADEON_HEAP_GTT_WC_READ_ONLY_32BIT:
 705     case RADEON_HEAP_GTT_WC_32BIT:
 706     case RADEON_HEAP_GTT:
 707         return RADEON_DOMAIN_GTT;
 708     default:
 709         assert(0);
 710         return (enum radeon_bo_domain)0;
 711     }
 712 }
 713
 714 static inline unsigned radeon_flags_from_heap(enum radeon_heap heap)
 715 {
 716     unsigned flags = RADEON_FLAG_NO_INTERPROCESS_SHARING |
 717                      (heap != RADEON_HEAP_GTT ? RADEON_FLAG_GTT_WC : 0);
 718
 719     switch (heap) {
 720     case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
 721         return flags |
 722                RADEON_FLAG_NO_CPU_ACCESS;
 723
 724     case RADEON_HEAP_VRAM_READ_ONLY:
 725     case RADEON_HEAP_GTT_WC_READ_ONLY:
 726         return flags |
 727                RADEON_FLAG_READ_ONLY;
 728
 729     case RADEON_HEAP_VRAM_READ_ONLY_32BIT:
 730     case RADEON_HEAP_GTT_WC_READ_ONLY_32BIT:
 731         return flags |
 732                RADEON_FLAG_READ_ONLY |
 733                RADEON_FLAG_32BIT;
 734
 735     case RADEON_HEAP_VRAM_32BIT:
 736     case RADEON_HEAP_GTT_WC_32BIT:
 737         return flags |
 738                RADEON_FLAG_32BIT;
 739
 740     case RADEON_HEAP_VRAM:
 741     case RADEON_HEAP_GTT_WC:
 742     case RADEON_HEAP_GTT:
 743     default:
 744         return flags;
 745     }
 746 }
 747
 748 /* Return the heap index for winsys allocators, or -1 on failure. */
 749 static inline int radeon_get_heap_index(enum radeon_bo_domain domain,
 750                                         enum radeon_bo_flag flags)
 751 {
 752     /* VRAM implies WC (write combining) */
 753     assert(!(domain & RADEON_DOMAIN_VRAM) || flags & RADEON_FLAG_GTT_WC);
 754     /* NO_CPU_ACCESS implies VRAM only. */
 755     assert(!(flags & RADEON_FLAG_NO_CPU_ACCESS) || domain == RADEON_DOMAIN_VRAM);
 756
 757     /* Resources with interprocess sharing don't use any winsys allocators. */
 758     if (!(flags & RADEON_FLAG_NO_INTERPROCESS_SHARING))
 759         return -1;
 760
 761     /* Unsupported flags: NO_SUBALLOC, SPARSE. */
 762     if (flags & ~(RADEON_FLAG_GTT_WC |
 763                   RADEON_FLAG_NO_CPU_ACCESS |
 764                   RADEON_FLAG_NO_INTERPROCESS_SHARING |
 765                   RADEON_FLAG_READ_ONLY |
 766                   RADEON_FLAG_32BIT))
 767         return -1;
 768
 769     switch (domain) {
 770     case RADEON_DOMAIN_VRAM:
 771         switch (flags & (RADEON_FLAG_NO_CPU_ACCESS |
 772                          RADEON_FLAG_READ_ONLY |
 773                          RADEON_FLAG_32BIT)) {
 774         case RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
 775         case RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_READ_ONLY:
 776             assert(!"NO_CPU_ACCESS | READ_ONLY doesn't make sense");
 777             return -1;
 778         case RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_32BIT:
 779             assert(!"NO_CPU_ACCESS with 32BIT is disallowed");
 780             return -1;
 781         case RADEON_FLAG_NO_CPU_ACCESS:
 782             return RADEON_HEAP_VRAM_NO_CPU_ACCESS;
 783         case RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
 784             return RADEON_HEAP_VRAM_READ_ONLY_32BIT;
 785         case RADEON_FLAG_READ_ONLY:
 786             return RADEON_HEAP_VRAM_READ_ONLY;
 787         case RADEON_FLAG_32BIT:
 788             return RADEON_HEAP_VRAM_32BIT;
 789         case 0:
 790             return RADEON_HEAP_VRAM;
 791         }
 792         break;
 793     case RADEON_DOMAIN_GTT:
 794         switch (flags & (RADEON_FLAG_GTT_WC |
 795                          RADEON_FLAG_READ_ONLY |
 796                          RADEON_FLAG_32BIT)) {
 797         case RADEON_FLAG_GTT_WC | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
 798             return RADEON_HEAP_GTT_WC_READ_ONLY_32BIT;
 799         case RADEON_FLAG_GTT_WC | RADEON_FLAG_READ_ONLY:
 800             return RADEON_HEAP_GTT_WC_READ_ONLY;
 801         case RADEON_FLAG_GTT_WC | RADEON_FLAG_32BIT:
 802             return RADEON_HEAP_GTT_WC_32BIT;
 803         case RADEON_FLAG_GTT_WC:
 804             return RADEON_HEAP_GTT_WC;
 805         case RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
 806         case RADEON_FLAG_READ_ONLY:
 807             assert(!"READ_ONLY without WC is disallowed");
 808             return -1;
 809         case RADEON_FLAG_32BIT:
 810             assert(!"32BIT without WC is disallowed");
 811             return -1;
 812         case 0:
 813             return RADEON_HEAP_GTT;
 814         }
 815         break;
 816     default:
 817         break;
 818     }
 819     return -1;
 820 }
 821
 822 #endif