src/gallium/drivers/radeon/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #ifndef RADEON_WINSYS_H
  25 #define RADEON_WINSYS_H
  26
  27 /* The public winsys interface header for the radeon driver. */
  28
  29 #include "pipebuffer/pb_buffer.h"
  30
  31 #define RADEON_FLUSH_ASYNC              (1 << 0)
  32 #define RADEON_FLUSH_KEEP_TILING_FLAGS  (1 << 1)
  33 #define RADEON_FLUSH_END_OF_FRAME       (1 << 2)
  34
  35 /* Tiling flags. */
  36 enum radeon_bo_layout {
  37     RADEON_LAYOUT_LINEAR = 0,
  38     RADEON_LAYOUT_TILED,
  39     RADEON_LAYOUT_SQUARETILED,
  40
  41     RADEON_LAYOUT_UNKNOWN
  42 };
  43
  44 enum radeon_bo_domain { /* bitfield */
  45     RADEON_DOMAIN_GTT  = 2,
  46     RADEON_DOMAIN_VRAM = 4,
  47     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  48 };
  49
  50 enum radeon_bo_flag { /* bitfield */
  51     RADEON_FLAG_GTT_WC =        (1 << 0),
  52     RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  53     RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  54 };
  55
  56 enum radeon_bo_usage { /* bitfield */
  57     RADEON_USAGE_READ = 2,
  58     RADEON_USAGE_WRITE = 4,
  59     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
  60 };
  61
  62 enum radeon_family {
  63     CHIP_UNKNOWN = 0,
  64     CHIP_R300, /* R3xx-based cores. */
  65     CHIP_R350,
  66     CHIP_RV350,
  67     CHIP_RV370,
  68     CHIP_RV380,
  69     CHIP_RS400,
  70     CHIP_RC410,
  71     CHIP_RS480,
  72     CHIP_R420,     /* R4xx-based cores. */
  73     CHIP_R423,
  74     CHIP_R430,
  75     CHIP_R480,
  76     CHIP_R481,
  77     CHIP_RV410,
  78     CHIP_RS600,
  79     CHIP_RS690,
  80     CHIP_RS740,
  81     CHIP_RV515,    /* R5xx-based cores. */
  82     CHIP_R520,
  83     CHIP_RV530,
  84     CHIP_R580,
  85     CHIP_RV560,
  86     CHIP_RV570,
  87     CHIP_R600,
  88     CHIP_RV610,
  89     CHIP_RV630,
  90     CHIP_RV670,
  91     CHIP_RV620,
  92     CHIP_RV635,
  93     CHIP_RS780,
  94     CHIP_RS880,
  95     CHIP_RV770,
  96     CHIP_RV730,
  97     CHIP_RV710,
  98     CHIP_RV740,
  99     CHIP_CEDAR,
 100     CHIP_REDWOOD,
 101     CHIP_JUNIPER,
 102     CHIP_CYPRESS,
 103     CHIP_HEMLOCK,
 104     CHIP_PALM,
 105     CHIP_SUMO,
 106     CHIP_SUMO2,
 107     CHIP_BARTS,
 108     CHIP_TURKS,
 109     CHIP_CAICOS,
 110     CHIP_CAYMAN,
 111     CHIP_ARUBA,
 112     CHIP_TAHITI,
 113     CHIP_PITCAIRN,
 114     CHIP_VERDE,
 115     CHIP_OLAND,
 116     CHIP_HAINAN,
 117     CHIP_BONAIRE,
 118     CHIP_KAVERI,
 119     CHIP_KABINI,
 120     CHIP_HAWAII,
 121     CHIP_MULLINS,
 122     CHIP_TONGA,
 123     CHIP_ICELAND,
 124     CHIP_CARRIZO,
 125     CHIP_FIJI,
 126     CHIP_STONEY,
 127     CHIP_POLARIS10,
 128     CHIP_POLARIS11,
 129     CHIP_LAST,
 130 };
 131
 132 enum chip_class {
 133     CLASS_UNKNOWN = 0,
 134     R300,
 135     R400,
 136     R500,
 137     R600,
 138     R700,
 139     EVERGREEN,
 140     CAYMAN,
 141     SI,
 142     CIK,
 143     VI,
 144 };
 145
 146 enum ring_type {
 147     RING_GFX = 0,
 148     RING_COMPUTE,
 149     RING_DMA,
 150     RING_UVD,
 151     RING_VCE,
 152     RING_LAST,
 153 };
 154
 155 enum radeon_value_id {
 156     RADEON_REQUESTED_VRAM_MEMORY,
 157     RADEON_REQUESTED_GTT_MEMORY,
 158     RADEON_BUFFER_WAIT_TIME_NS,
 159     RADEON_TIMESTAMP,
 160     RADEON_NUM_CS_FLUSHES,
 161     RADEON_NUM_BYTES_MOVED,
 162     RADEON_VRAM_USAGE,
 163     RADEON_GTT_USAGE,
 164     RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
 165     RADEON_CURRENT_SCLK,
 166     RADEON_CURRENT_MCLK,
 167     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
 168 };
 169
 170 /* Each group of four has the same priority. */
 171 enum radeon_bo_priority {
 172     RADEON_PRIO_FENCE = 0,
 173     RADEON_PRIO_TRACE,
 174     RADEON_PRIO_SO_FILLED_SIZE,
 175     RADEON_PRIO_QUERY,
 176
 177     RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
 178     RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
 179     RADEON_PRIO_DRAW_INDIRECT,
 180     RADEON_PRIO_INDEX_BUFFER,
 181
 182     RADEON_PRIO_CP_DMA = 8,
 183
 184     RADEON_PRIO_VCE = 12,
 185     RADEON_PRIO_UVD,
 186     RADEON_PRIO_SDMA_BUFFER,
 187     RADEON_PRIO_SDMA_TEXTURE,
 188
 189     RADEON_PRIO_USER_SHADER = 16,
 190     RADEON_PRIO_INTERNAL_SHADER, /* fetch shader, etc. */
 191
 192     /* gap: 20 */
 193
 194     RADEON_PRIO_CONST_BUFFER = 24,
 195     RADEON_PRIO_DESCRIPTORS,
 196     RADEON_PRIO_BORDER_COLORS,
 197
 198     RADEON_PRIO_SAMPLER_BUFFER = 28,
 199     RADEON_PRIO_VERTEX_BUFFER,
 200
 201     RADEON_PRIO_SHADER_RW_BUFFER = 32,
 202     RADEON_PRIO_RINGS_STREAMOUT,
 203     RADEON_PRIO_SCRATCH_BUFFER,
 204     RADEON_PRIO_COMPUTE_GLOBAL,
 205
 206     RADEON_PRIO_SAMPLER_TEXTURE = 36,
 207     RADEON_PRIO_SHADER_RW_IMAGE,
 208
 209     RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 40,
 210
 211     RADEON_PRIO_COLOR_BUFFER = 44,
 212
 213     RADEON_PRIO_DEPTH_BUFFER = 48,
 214
 215     RADEON_PRIO_COLOR_BUFFER_MSAA = 52,
 216
 217     RADEON_PRIO_DEPTH_BUFFER_MSAA = 56,
 218
 219     RADEON_PRIO_CMASK = 60,
 220     RADEON_PRIO_DCC,
 221     RADEON_PRIO_HTILE,
 222     /* 63 is the maximum value */
 223 };
 224
 225 struct winsys_handle;
 226 struct radeon_winsys_ctx;
 227
 228 struct radeon_winsys_cs {
 229     unsigned                    cdw;  /* Number of used dwords. */
 230     unsigned                    max_dw; /* Maximum number of dwords. */
 231     uint32_t                    *buf; /* The command buffer. */
 232     enum ring_type              ring_type;
 233 };
 234
 235 struct radeon_info {
 236     /* PCI info: domain:bus:dev:func */
 237     uint32_t                    pci_domain;
 238     uint32_t                    pci_bus;
 239     uint32_t                    pci_dev;
 240     uint32_t                    pci_func;
 241
 242     /* Device info. */
 243     uint32_t                    pci_id;
 244     enum radeon_family          family;
 245     enum chip_class             chip_class;
 246     uint64_t                    gart_size;
 247     uint64_t                    vram_size;
 248     bool                        has_dedicated_vram;
 249     boolean                     has_virtual_memory;
 250     bool                        gfx_ib_pad_with_type2;
 251     boolean                     has_sdma;
 252     boolean                     has_uvd;
 253     uint32_t                    vce_fw_version;
 254     uint32_t                    vce_harvest_config;
 255     uint32_t                    clock_crystal_freq;
 256
 257     /* Kernel info. */
 258     uint32_t                    drm_major; /* version */
 259     uint32_t                    drm_minor;
 260     uint32_t                    drm_patchlevel;
 261     boolean                     has_userptr;
 262
 263     /* Shader cores. */
 264     uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
 265     uint32_t                    max_shader_clock;
 266     uint32_t                    num_good_compute_units;
 267     uint32_t                    max_se; /* shader engines */
 268     uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 269
 270     /* Render backends (color + depth blocks). */
 271     uint32_t                    r300_num_gb_pipes;
 272     uint32_t                    r300_num_z_pipes;
 273     uint32_t                    r600_gb_backend_map; /* R600 harvest config */
 274     boolean                     r600_gb_backend_map_valid;
 275     uint32_t                    r600_num_banks;
 276     uint32_t                    num_render_backends;
 277     uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
 278     uint32_t                    pipe_interleave_bytes;
 279     uint32_t                    enabled_rb_mask; /* GCN harvest config */
 280
 281     /* Tile modes. */
 282     boolean                     si_tile_mode_array_valid;
 283     uint32_t                    si_tile_mode_array[32];
 284     boolean                     cik_macrotile_mode_array_valid;
 285     uint32_t                    cik_macrotile_mode_array[16];
 286 };
 287
 288 /* Tiling info for display code, DRI sharing, and other data. */
 289 struct radeon_bo_metadata {
 290     /* Tiling flags describing the texture layout for display code
 291      * and DRI sharing.
 292      */
 293     enum radeon_bo_layout   microtile;
 294     enum radeon_bo_layout   macrotile;
 295     unsigned                pipe_config;
 296     unsigned                bankw;
 297     unsigned                bankh;
 298     unsigned                tile_split;
 299     unsigned                stencil_tile_split;
 300     unsigned                mtilea;
 301     unsigned                num_banks;
 302     unsigned                stride;
 303     bool                    scanout;
 304
 305     /* Additional metadata associated with the buffer, in bytes.
 306      * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 307      * Supported by amdgpu only.
 308      */
 309     uint32_t                size_metadata;
 310     uint32_t                metadata[64];
 311 };
 312
 313 enum radeon_feature_id {
 314     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 315     RADEON_FID_R300_CMASK_ACCESS,
 316 };
 317
 318 #define RADEON_SURF_MAX_LEVEL                   32
 319
 320 #define RADEON_SURF_TYPE_MASK                   0xFF
 321 #define RADEON_SURF_TYPE_SHIFT                  0
 322 #define     RADEON_SURF_TYPE_1D                     0
 323 #define     RADEON_SURF_TYPE_2D                     1
 324 #define     RADEON_SURF_TYPE_3D                     2
 325 #define     RADEON_SURF_TYPE_CUBEMAP                3
 326 #define     RADEON_SURF_TYPE_1D_ARRAY               4
 327 #define     RADEON_SURF_TYPE_2D_ARRAY               5
 328 #define RADEON_SURF_MODE_MASK                   0xFF
 329 #define RADEON_SURF_MODE_SHIFT                  8
 330 #define     RADEON_SURF_MODE_LINEAR                 0
 331 #define     RADEON_SURF_MODE_LINEAR_ALIGNED         1
 332 #define     RADEON_SURF_MODE_1D                     2
 333 #define     RADEON_SURF_MODE_2D                     3
 334 #define RADEON_SURF_SCANOUT                     (1 << 16)
 335 #define RADEON_SURF_ZBUFFER                     (1 << 17)
 336 #define RADEON_SURF_SBUFFER                     (1 << 18)
 337 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
 338 #define RADEON_SURF_HAS_SBUFFER_MIPTREE         (1 << 19)
 339 #define RADEON_SURF_HAS_TILE_MODE_INDEX         (1 << 20)
 340 #define RADEON_SURF_FMASK                       (1 << 21)
 341
 342 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
 343 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
 344 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
 345
 346 struct radeon_surf_level {
 347     uint64_t                    offset;
 348     uint64_t                    slice_size;
 349     uint32_t                    npix_x;
 350     uint32_t                    npix_y;
 351     uint32_t                    npix_z;
 352     uint32_t                    nblk_x;
 353     uint32_t                    nblk_y;
 354     uint32_t                    nblk_z;
 355     uint32_t                    pitch_bytes;
 356     uint32_t                    mode;
 357     uint64_t                    dcc_offset;
 358 };
 359
 360 struct radeon_surf {
 361     /* These are inputs to the calculator. */
 362     uint32_t                    npix_x;
 363     uint32_t                    npix_y;
 364     uint32_t                    npix_z;
 365     uint32_t                    blk_w;
 366     uint32_t                    blk_h;
 367     uint32_t                    blk_d;
 368     uint32_t                    array_size;
 369     uint32_t                    last_level;
 370     uint32_t                    bpe;
 371     uint32_t                    nsamples;
 372     uint32_t                    flags;
 373
 374     /* These are return values. Some of them can be set by the caller, but
 375      * they will be treated as hints (e.g. bankw, bankh) and might be
 376      * changed by the calculator.
 377      */
 378     uint64_t                    bo_size;
 379     uint64_t                    bo_alignment;
 380     /* This applies to EG and later. */
 381     uint32_t                    bankw;
 382     uint32_t                    bankh;
 383     uint32_t                    mtilea;
 384     uint32_t                    tile_split;
 385     uint32_t                    stencil_tile_split;
 386     uint64_t                    stencil_offset;
 387     struct radeon_surf_level    level[RADEON_SURF_MAX_LEVEL];
 388     struct radeon_surf_level    stencil_level[RADEON_SURF_MAX_LEVEL];
 389     uint32_t                    tiling_index[RADEON_SURF_MAX_LEVEL];
 390     uint32_t                    stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
 391     uint32_t                    pipe_config;
 392     uint32_t                    num_banks;
 393
 394     uint64_t                    dcc_size;
 395     uint64_t                    dcc_alignment;
 396 };
 397
 398 struct radeon_bo_list_item {
 399     struct pb_buffer *buf;
 400     uint64_t vm_address;
 401     uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
 402 };
 403
 404 struct radeon_winsys {
 405     /**
 406      * The screen object this winsys was created for
 407      */
 408     struct pipe_screen *screen;
 409
 410     /**
 411      * Decrement the winsys reference count.
 412      *
 413      * \param ws  The winsys this function is called for.
 414      * \return    True if the winsys and screen should be destroyed.
 415      */
 416     bool (*unref)(struct radeon_winsys *ws);
 417
 418     /**
 419      * Destroy this winsys.
 420      *
 421      * \param ws        The winsys this function is called from.
 422      */
 423     void (*destroy)(struct radeon_winsys *ws);
 424
 425     /**
 426      * Query an info structure from winsys.
 427      *
 428      * \param ws        The winsys this function is called from.
 429      * \param info      Return structure
 430      */
 431     void (*query_info)(struct radeon_winsys *ws,
 432                        struct radeon_info *info);
 433
 434     /**************************************************************************
 435      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 436      *
 437      * Remember that gallium gets to choose the interface it needs, and the
 438      * window systems must then implement that interface (rather than the
 439      * other way around...).
 440      *************************************************************************/
 441
 442     /**
 443      * Create a buffer object.
 444      *
 445      * \param ws        The winsys this function is called from.
 446      * \param size      The size to allocate.
 447      * \param alignment An alignment of the buffer in memory.
 448      * \param use_reusable_pool Whether the cache buffer manager should be used.
 449      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 450      * \return          The created buffer object.
 451      */
 452     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 453                                        uint64_t size,
 454                                        unsigned alignment,
 455                                        boolean use_reusable_pool,
 456                                        enum radeon_bo_domain domain,
 457                                        enum radeon_bo_flag flags);
 458
 459     /**
 460      * Map the entire data store of a buffer object into the client's address
 461      * space.
 462      *
 463      * \param buf       A winsys buffer object to map.
 464      * \param cs        A command stream to flush if the buffer is referenced by it.
 465      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 466      * \return          The pointer at the beginning of the buffer.
 467      */
 468     void *(*buffer_map)(struct pb_buffer *buf,
 469                         struct radeon_winsys_cs *cs,
 470                         enum pipe_transfer_usage usage);
 471
 472     /**
 473      * Unmap a buffer object from the client's address space.
 474      *
 475      * \param buf       A winsys buffer object to unmap.
 476      */
 477     void (*buffer_unmap)(struct pb_buffer *buf);
 478
 479     /**
 480      * Wait for the buffer and return true if the buffer is not used
 481      * by the device.
 482      *
 483      * The timeout of 0 will only return the status.
 484      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
 485      * is idle.
 486      */
 487     bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
 488                         enum radeon_bo_usage usage);
 489
 490     /**
 491      * Return buffer metadata.
 492      * (tiling info for display code, DRI sharing, and other data)
 493      *
 494      * \param buf       A winsys buffer object to get the flags from.
 495      * \param md        Metadata
 496      */
 497     void (*buffer_get_metadata)(struct pb_buffer *buf,
 498                                 struct radeon_bo_metadata *md);
 499
 500     /**
 501      * Set buffer metadata.
 502      * (tiling info for display code, DRI sharing, and other data)
 503      *
 504      * \param buf       A winsys buffer object to set the flags for.
 505      * \param md        Metadata
 506      */
 507     void (*buffer_set_metadata)(struct pb_buffer *buf,
 508                                 struct radeon_bo_metadata *md);
 509
 510     /**
 511      * Get a winsys buffer from a winsys handle. The internal structure
 512      * of the handle is platform-specific and only a winsys should access it.
 513      *
 514      * \param ws        The winsys this function is called from.
 515      * \param whandle   A winsys handle pointer as was received from a state
 516      *                  tracker.
 517      * \param stride    The returned buffer stride in bytes.
 518      */
 519     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 520                                             struct winsys_handle *whandle,
 521                                             unsigned *stride, unsigned *offset);
 522
 523     /**
 524      * Get a winsys buffer from a user pointer. The resulting buffer can't
 525      * be exported. Both pointer and size must be page aligned.
 526      *
 527      * \param ws        The winsys this function is called from.
 528      * \param pointer   User pointer to turn into a buffer object.
 529      * \param Size      Size in bytes for the new buffer.
 530      */
 531     struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
 532                                          void *pointer, uint64_t size);
 533
 534     /**
 535      * Whether the buffer was created from a user pointer.
 536      *
 537      * \param buf       A winsys buffer object
 538      * \return          whether \p buf was created via buffer_from_ptr
 539      */
 540     bool (*buffer_is_user_ptr)(struct pb_buffer *buf);
 541
 542     /**
 543      * Get a winsys handle from a winsys buffer. The internal structure
 544      * of the handle is platform-specific and only a winsys should access it.
 545      *
 546      * \param buf       A winsys buffer object to get the handle from.
 547      * \param whandle   A winsys handle pointer.
 548      * \param stride    A stride of the buffer in bytes, for texturing.
 549      * \return          TRUE on success.
 550      */
 551     boolean (*buffer_get_handle)(struct pb_buffer *buf,
 552                                  unsigned stride, unsigned offset,
 553                                  unsigned slice_size,
 554                                  struct winsys_handle *whandle);
 555
 556     /**
 557      * Return the virtual address of a buffer.
 558      *
 559      * \param buf       A winsys buffer object
 560      * \return          virtual address
 561      */
 562     uint64_t (*buffer_get_virtual_address)(struct pb_buffer *buf);
 563
 564     /**
 565      * Query the initial placement of the buffer from the kernel driver.
 566      */
 567     enum radeon_bo_domain (*buffer_get_initial_domain)(struct pb_buffer *buf);
 568
 569     /**************************************************************************
 570      * Command submission.
 571      *
 572      * Each pipe context should create its own command stream and submit
 573      * commands independently of other contexts.
 574      *************************************************************************/
 575
 576     /**
 577      * Create a command submission context.
 578      * Various command streams can be submitted to the same context.
 579      */
 580     struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 581
 582     /**
 583      * Destroy a context.
 584      */
 585     void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 586
 587     /**
 588      * Query a GPU reset status.
 589      */
 590     enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
 591
 592     /**
 593      * Create a command stream.
 594      *
 595      * \param ctx       The submission context
 596      * \param ring_type The ring type (GFX, DMA, UVD)
 597      * \param flush     Flush callback function associated with the command stream.
 598      * \param user      User pointer that will be passed to the flush callback.
 599      */
 600     struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys_ctx *ctx,
 601                                           enum ring_type ring_type,
 602                                           void (*flush)(void *ctx, unsigned flags,
 603                                                         struct pipe_fence_handle **fence),
 604                                           void *flush_ctx);
 605
 606     /**
 607      * Destroy a command stream.
 608      *
 609      * \param cs        A command stream to destroy.
 610      */
 611     void (*cs_destroy)(struct radeon_winsys_cs *cs);
 612
 613     /**
 614      * Add a buffer. Each buffer used by a CS must be added using this function.
 615      *
 616      * \param cs      Command stream
 617      * \param buf     Buffer
 618      * \param usage   Whether the buffer is used for read and/or write.
 619      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 620      * \param priority  A higher number means a greater chance of being
 621      *                  placed in the requested domain. 15 is the maximum.
 622      * \return Buffer index.
 623      */
 624     unsigned (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 625                              struct pb_buffer *buf,
 626                              enum radeon_bo_usage usage,
 627                              enum radeon_bo_domain domain,
 628                              enum radeon_bo_priority priority);
 629
 630     /**
 631      * Return the index of an already-added buffer.
 632      *
 633      * \param cs        Command stream
 634      * \param buf       Buffer
 635      * \return          The buffer index, or -1 if the buffer has not been added.
 636      */
 637     int (*cs_lookup_buffer)(struct radeon_winsys_cs *cs,
 638                             struct pb_buffer *buf);
 639
 640     /**
 641      * Return TRUE if there is enough memory in VRAM and GTT for the buffers
 642      * added so far. If the validation fails, all buffers which have
 643      * been added since the last call of cs_validate will be removed and
 644      * the CS will be flushed (provided there are still any buffers).
 645      *
 646      * \param cs        A command stream to validate.
 647      */
 648     boolean (*cs_validate)(struct radeon_winsys_cs *cs);
 649
 650     /**
 651      * Return TRUE if there is enough memory in VRAM and GTT for the buffers
 652      * added so far.
 653      *
 654      * \param cs        A command stream to validate.
 655      * \param vram      VRAM memory size pending to be use
 656      * \param gtt       GTT memory size pending to be use
 657      */
 658     boolean (*cs_memory_below_limit)(struct radeon_winsys_cs *cs, uint64_t vram, uint64_t gtt);
 659
 660     /**
 661      * Return the buffer list.
 662      *
 663      * \param cs    Command stream
 664      * \param list  Returned buffer list. Set to NULL to query the count only.
 665      * \return      The buffer count.
 666      */
 667     unsigned (*cs_get_buffer_list)(struct radeon_winsys_cs *cs,
 668                                    struct radeon_bo_list_item *list);
 669
 670     /**
 671      * Flush a command stream.
 672      *
 673      * \param cs          A command stream to flush.
 674      * \param flags,      RADEON_FLUSH_ASYNC or 0.
 675      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 676      *                    after the CS and is returned through this parameter.
 677      */
 678     void (*cs_flush)(struct radeon_winsys_cs *cs,
 679                      unsigned flags,
 680                      struct pipe_fence_handle **fence);
 681
 682     /**
 683      * Return TRUE if a buffer is referenced by a command stream.
 684      *
 685      * \param cs        A command stream.
 686      * \param buf       A winsys buffer.
 687      */
 688     boolean (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
 689                                        struct pb_buffer *buf,
 690                                        enum radeon_bo_usage usage);
 691
 692     /**
 693      * Request access to a feature for a command stream.
 694      *
 695      * \param cs        A command stream.
 696      * \param fid       Feature ID, one of RADEON_FID_*
 697      * \param enable    Whether to enable or disable the feature.
 698      */
 699     boolean (*cs_request_feature)(struct radeon_winsys_cs *cs,
 700                                   enum radeon_feature_id fid,
 701                                   boolean enable);
 702      /**
 703       * Make sure all asynchronous flush of the cs have completed
 704       *
 705       * \param cs        A command stream.
 706       */
 707     void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
 708
 709     /**
 710      * Wait for the fence and return true if the fence has been signalled.
 711      * The timeout of 0 will only return the status.
 712      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 713      * is signalled.
 714      */
 715     bool (*fence_wait)(struct radeon_winsys *ws,
 716                        struct pipe_fence_handle *fence,
 717                        uint64_t timeout);
 718
 719     /**
 720      * Reference counting for fences.
 721      */
 722     void (*fence_reference)(struct pipe_fence_handle **dst,
 723                             struct pipe_fence_handle *src);
 724
 725     /**
 726      * Initialize surface
 727      *
 728      * \param ws        The winsys this function is called from.
 729      * \param surf      Surface structure ptr
 730      */
 731     int (*surface_init)(struct radeon_winsys *ws,
 732                         struct radeon_surf *surf);
 733
 734     /**
 735      * Find best values for a surface
 736      *
 737      * \param ws        The winsys this function is called from.
 738      * \param surf      Surface structure ptr
 739      */
 740     int (*surface_best)(struct radeon_winsys *ws,
 741                         struct radeon_surf *surf);
 742
 743     uint64_t (*query_value)(struct radeon_winsys *ws,
 744                             enum radeon_value_id value);
 745
 746     bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 747                            unsigned num_registers, uint32_t *out);
 748 };
 749
 750
 751 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 752 {
 753     cs->buf[cs->cdw++] = value;
 754 }
 755
 756 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 757                                      const uint32_t *values, unsigned count)
 758 {
 759     memcpy(cs->buf+cs->cdw, values, count * 4);
 760     cs->cdw += count;
 761 }
 762
 763 #endif