src/gallium/drivers/radeon/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #ifndef RADEON_WINSYS_H
  25 #define RADEON_WINSYS_H
  26
  27 /* The public winsys interface header for the radeon driver. */
  28
  29 #include "pipebuffer/pb_buffer.h"
  30
  31 #include "amd/common/amd_family.h"
  32
  33 #define RADEON_FLUSH_ASYNC              (1 << 0)
  34 #define RADEON_FLUSH_END_OF_FRAME       (1 << 1)
  35
  36 /* Tiling flags. */
  37 enum radeon_bo_layout {
  38     RADEON_LAYOUT_LINEAR = 0,
  39     RADEON_LAYOUT_TILED,
  40     RADEON_LAYOUT_SQUARETILED,
  41
  42     RADEON_LAYOUT_UNKNOWN
  43 };
  44
  45 enum radeon_bo_domain { /* bitfield */
  46     RADEON_DOMAIN_GTT  = 2,
  47     RADEON_DOMAIN_VRAM = 4,
  48     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  49 };
  50
  51 enum radeon_bo_flag { /* bitfield */
  52     RADEON_FLAG_GTT_WC =        (1 << 0),
  53     RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  54     RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  55     RADEON_FLAG_HANDLE =        (1 << 3), /* the buffer most not be suballocated */
  56 };
  57
  58 enum radeon_bo_usage { /* bitfield */
  59     RADEON_USAGE_READ = 2,
  60     RADEON_USAGE_WRITE = 4,
  61     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE,
  62
  63     /* The winsys ensures that the CS submission will be scheduled after
  64      * previously flushed CSs referencing this BO in a conflicting way.
  65      */
  66     RADEON_USAGE_SYNCHRONIZED = 8
  67 };
  68
  69 enum ring_type {
  70     RING_GFX = 0,
  71     RING_COMPUTE,
  72     RING_DMA,
  73     RING_UVD,
  74     RING_VCE,
  75     RING_LAST,
  76 };
  77
  78 enum radeon_value_id {
  79     RADEON_REQUESTED_VRAM_MEMORY,
  80     RADEON_REQUESTED_GTT_MEMORY,
  81     RADEON_MAPPED_VRAM,
  82     RADEON_MAPPED_GTT,
  83     RADEON_BUFFER_WAIT_TIME_NS,
  84     RADEON_TIMESTAMP,
  85     RADEON_NUM_CS_FLUSHES,
  86     RADEON_NUM_BYTES_MOVED,
  87     RADEON_NUM_EVICTIONS,
  88     RADEON_VRAM_USAGE,
  89     RADEON_GTT_USAGE,
  90     RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
  91     RADEON_CURRENT_SCLK,
  92     RADEON_CURRENT_MCLK,
  93     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
  94 };
  95
  96 /* Each group of four has the same priority. */
  97 enum radeon_bo_priority {
  98     RADEON_PRIO_FENCE = 0,
  99     RADEON_PRIO_TRACE,
 100     RADEON_PRIO_SO_FILLED_SIZE,
 101     RADEON_PRIO_QUERY,
 102
 103     RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
 104     RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
 105     RADEON_PRIO_DRAW_INDIRECT,
 106     RADEON_PRIO_INDEX_BUFFER,
 107
 108     RADEON_PRIO_VCE = 8,
 109     RADEON_PRIO_UVD,
 110     RADEON_PRIO_SDMA_BUFFER,
 111     RADEON_PRIO_SDMA_TEXTURE,
 112
 113     RADEON_PRIO_CP_DMA = 12,
 114
 115     RADEON_PRIO_CONST_BUFFER = 16,
 116     RADEON_PRIO_DESCRIPTORS,
 117     RADEON_PRIO_BORDER_COLORS,
 118
 119     RADEON_PRIO_SAMPLER_BUFFER = 20,
 120     RADEON_PRIO_VERTEX_BUFFER,
 121
 122     RADEON_PRIO_SHADER_RW_BUFFER = 24,
 123     RADEON_PRIO_COMPUTE_GLOBAL,
 124
 125     RADEON_PRIO_SAMPLER_TEXTURE = 28,
 126     RADEON_PRIO_SHADER_RW_IMAGE,
 127
 128     RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 32,
 129
 130     RADEON_PRIO_COLOR_BUFFER = 36,
 131
 132     RADEON_PRIO_DEPTH_BUFFER = 40,
 133
 134     RADEON_PRIO_COLOR_BUFFER_MSAA = 44,
 135
 136     RADEON_PRIO_DEPTH_BUFFER_MSAA = 48,
 137
 138     RADEON_PRIO_CMASK = 52,
 139     RADEON_PRIO_DCC,
 140     RADEON_PRIO_HTILE,
 141     RADEON_PRIO_SHADER_BINARY, /* the hw can't hide instruction cache misses */
 142
 143     RADEON_PRIO_SHADER_RINGS = 56,
 144
 145     RADEON_PRIO_SCRATCH_BUFFER = 60,
 146     /* 63 is the maximum value */
 147 };
 148
 149 struct winsys_handle;
 150 struct radeon_winsys_ctx;
 151
 152 struct radeon_winsys_cs_chunk {
 153     unsigned cdw;  /* Number of used dwords. */
 154     unsigned max_dw; /* Maximum number of dwords. */
 155     uint32_t *buf; /* The base pointer of the chunk. */
 156 };
 157
 158 struct radeon_winsys_cs {
 159     struct radeon_winsys_cs_chunk current;
 160     struct radeon_winsys_cs_chunk *prev;
 161     unsigned                      num_prev; /* Number of previous chunks. */
 162     unsigned                      max_prev; /* Space in array pointed to by prev. */
 163     unsigned                      prev_dw; /* Total number of dwords in previous chunks. */
 164
 165     /* Memory usage of the buffer list. These are always 0 for CE and preamble
 166      * IBs. */
 167     uint64_t                      used_vram;
 168     uint64_t                      used_gart;
 169 };
 170
 171 struct radeon_info {
 172     /* PCI info: domain:bus:dev:func */
 173     uint32_t                    pci_domain;
 174     uint32_t                    pci_bus;
 175     uint32_t                    pci_dev;
 176     uint32_t                    pci_func;
 177
 178     /* Device info. */
 179     uint32_t                    pci_id;
 180     enum radeon_family          family;
 181     enum chip_class             chip_class;
 182     uint32_t                    gart_page_size;
 183     uint64_t                    gart_size;
 184     uint64_t                    vram_size;
 185     uint64_t                    max_alloc_size;
 186     bool                        has_dedicated_vram;
 187     bool                        has_virtual_memory;
 188     bool                        gfx_ib_pad_with_type2;
 189     bool                        has_sdma;
 190     bool                        has_uvd;
 191     uint32_t                    uvd_fw_version;
 192     uint32_t                    vce_fw_version;
 193     uint32_t                    me_fw_version;
 194     uint32_t                    pfp_fw_version;
 195     uint32_t                    ce_fw_version;
 196     uint32_t                    vce_harvest_config;
 197     uint32_t                    clock_crystal_freq;
 198
 199     /* Kernel info. */
 200     uint32_t                    drm_major; /* version */
 201     uint32_t                    drm_minor;
 202     uint32_t                    drm_patchlevel;
 203     bool                        has_userptr;
 204
 205     /* Shader cores. */
 206     uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
 207     uint32_t                    max_shader_clock;
 208     uint32_t                    num_good_compute_units;
 209     uint32_t                    max_se; /* shader engines */
 210     uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 211
 212     /* Render backends (color + depth blocks). */
 213     uint32_t                    r300_num_gb_pipes;
 214     uint32_t                    r300_num_z_pipes;
 215     uint32_t                    r600_gb_backend_map; /* R600 harvest config */
 216     bool                        r600_gb_backend_map_valid;
 217     uint32_t                    r600_num_banks;
 218     uint32_t                    num_render_backends;
 219     uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
 220     uint32_t                    pipe_interleave_bytes;
 221     uint32_t                    enabled_rb_mask; /* GCN harvest config */
 222
 223     /* Tile modes. */
 224     uint32_t                    si_tile_mode_array[32];
 225     uint32_t                    cik_macrotile_mode_array[16];
 226 };
 227
 228 /* Tiling info for display code, DRI sharing, and other data. */
 229 struct radeon_bo_metadata {
 230     /* Tiling flags describing the texture layout for display code
 231      * and DRI sharing.
 232      */
 233     enum radeon_bo_layout   microtile;
 234     enum radeon_bo_layout   macrotile;
 235     unsigned                pipe_config;
 236     unsigned                bankw;
 237     unsigned                bankh;
 238     unsigned                tile_split;
 239     unsigned                mtilea;
 240     unsigned                num_banks;
 241     unsigned                stride;
 242     bool                    scanout;
 243
 244     /* Additional metadata associated with the buffer, in bytes.
 245      * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 246      * Supported by amdgpu only.
 247      */
 248     uint32_t                size_metadata;
 249     uint32_t                metadata[64];
 250 };
 251
 252 enum radeon_feature_id {
 253     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 254     RADEON_FID_R300_CMASK_ACCESS,
 255 };
 256
 257 #define RADEON_SURF_MAX_LEVEL                   32
 258
 259 #define RADEON_SURF_TYPE_MASK                   0xFF
 260 #define RADEON_SURF_TYPE_SHIFT                  0
 261 #define     RADEON_SURF_TYPE_1D                     0
 262 #define     RADEON_SURF_TYPE_2D                     1
 263 #define     RADEON_SURF_TYPE_3D                     2
 264 #define     RADEON_SURF_TYPE_CUBEMAP                3
 265 #define     RADEON_SURF_TYPE_1D_ARRAY               4
 266 #define     RADEON_SURF_TYPE_2D_ARRAY               5
 267 #define RADEON_SURF_MODE_MASK                   0xFF
 268 #define RADEON_SURF_MODE_SHIFT                  8
 269 #define     RADEON_SURF_MODE_LINEAR_ALIGNED         1
 270 #define     RADEON_SURF_MODE_1D                     2
 271 #define     RADEON_SURF_MODE_2D                     3
 272 #define RADEON_SURF_SCANOUT                     (1 << 16)
 273 #define RADEON_SURF_ZBUFFER                     (1 << 17)
 274 #define RADEON_SURF_SBUFFER                     (1 << 18)
 275 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
 276 #define RADEON_SURF_HAS_SBUFFER_MIPTREE         (1 << 19)
 277 #define RADEON_SURF_HAS_TILE_MODE_INDEX         (1 << 20)
 278 #define RADEON_SURF_FMASK                       (1 << 21)
 279 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
 280
 281 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
 282 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
 283 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
 284
 285 struct radeon_surf_level {
 286     uint64_t                    offset;
 287     uint64_t                    slice_size;
 288     uint32_t                    npix_x;
 289     uint32_t                    npix_y;
 290     uint32_t                    npix_z;
 291     uint32_t                    nblk_x;
 292     uint32_t                    nblk_y;
 293     uint32_t                    nblk_z;
 294     uint32_t                    pitch_bytes;
 295     uint32_t                    mode;
 296     uint64_t                    dcc_offset;
 297     uint64_t                    dcc_fast_clear_size;
 298     bool                        dcc_enabled;
 299 };
 300
 301 struct radeon_surf {
 302     /* These are inputs to the calculator. */
 303     uint32_t                    npix_x;
 304     uint32_t                    npix_y;
 305     uint32_t                    npix_z;
 306     uint32_t                    blk_w;
 307     uint32_t                    blk_h;
 308     uint32_t                    blk_d;
 309     uint32_t                    array_size;
 310     uint32_t                    last_level;
 311     uint32_t                    bpe;
 312     uint32_t                    nsamples;
 313     uint32_t                    flags;
 314
 315     /* These are return values. Some of them can be set by the caller, but
 316      * they will be treated as hints (e.g. bankw, bankh) and might be
 317      * changed by the calculator.
 318      */
 319     uint64_t                    bo_size;
 320     uint64_t                    bo_alignment;
 321     /* This applies to EG and later. */
 322     uint32_t                    bankw;
 323     uint32_t                    bankh;
 324     uint32_t                    mtilea;
 325     uint32_t                    tile_split;
 326     uint32_t                    stencil_tile_split;
 327     struct radeon_surf_level    level[RADEON_SURF_MAX_LEVEL];
 328     struct radeon_surf_level    stencil_level[RADEON_SURF_MAX_LEVEL];
 329     uint32_t                    tiling_index[RADEON_SURF_MAX_LEVEL];
 330     uint32_t                    stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
 331     uint32_t                    pipe_config;
 332     uint32_t                    num_banks;
 333     uint32_t                    macro_tile_index;
 334     uint32_t                    micro_tile_mode; /* displayable, thin, depth, rotated */
 335
 336     /* Whether the depth miptree or stencil miptree as used by the DB are
 337      * adjusted from their TC compatible form to ensure depth/stencil
 338      * compatibility. If either is true, the corresponding plane cannot be
 339      * sampled from.
 340      */
 341     bool                        depth_adjusted;
 342     bool                        stencil_adjusted;
 343
 344     uint64_t                    dcc_size;
 345     uint64_t                    dcc_alignment;
 346 };
 347
 348 struct radeon_bo_list_item {
 349     uint64_t bo_size;
 350     uint64_t vm_address;
 351     uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
 352 };
 353
 354 struct radeon_winsys {
 355     /**
 356      * The screen object this winsys was created for
 357      */
 358     struct pipe_screen *screen;
 359
 360     /**
 361      * Decrement the winsys reference count.
 362      *
 363      * \param ws  The winsys this function is called for.
 364      * \return    True if the winsys and screen should be destroyed.
 365      */
 366     bool (*unref)(struct radeon_winsys *ws);
 367
 368     /**
 369      * Destroy this winsys.
 370      *
 371      * \param ws        The winsys this function is called from.
 372      */
 373     void (*destroy)(struct radeon_winsys *ws);
 374
 375     /**
 376      * Query an info structure from winsys.
 377      *
 378      * \param ws        The winsys this function is called from.
 379      * \param info      Return structure
 380      */
 381     void (*query_info)(struct radeon_winsys *ws,
 382                        struct radeon_info *info);
 383
 384     /**************************************************************************
 385      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 386      *
 387      * Remember that gallium gets to choose the interface it needs, and the
 388      * window systems must then implement that interface (rather than the
 389      * other way around...).
 390      *************************************************************************/
 391
 392     /**
 393      * Create a buffer object.
 394      *
 395      * \param ws        The winsys this function is called from.
 396      * \param size      The size to allocate.
 397      * \param alignment An alignment of the buffer in memory.
 398      * \param use_reusable_pool Whether the cache buffer manager should be used.
 399      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 400      * \return          The created buffer object.
 401      */
 402     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 403                                        uint64_t size,
 404                                        unsigned alignment,
 405                                        enum radeon_bo_domain domain,
 406                                        enum radeon_bo_flag flags);
 407
 408     /**
 409      * Map the entire data store of a buffer object into the client's address
 410      * space.
 411      *
 412      * \param buf       A winsys buffer object to map.
 413      * \param cs        A command stream to flush if the buffer is referenced by it.
 414      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 415      * \return          The pointer at the beginning of the buffer.
 416      */
 417     void *(*buffer_map)(struct pb_buffer *buf,
 418                         struct radeon_winsys_cs *cs,
 419                         enum pipe_transfer_usage usage);
 420
 421     /**
 422      * Unmap a buffer object from the client's address space.
 423      *
 424      * \param buf       A winsys buffer object to unmap.
 425      */
 426     void (*buffer_unmap)(struct pb_buffer *buf);
 427
 428     /**
 429      * Wait for the buffer and return true if the buffer is not used
 430      * by the device.
 431      *
 432      * The timeout of 0 will only return the status.
 433      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
 434      * is idle.
 435      */
 436     bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
 437                         enum radeon_bo_usage usage);
 438
 439     /**
 440      * Return buffer metadata.
 441      * (tiling info for display code, DRI sharing, and other data)
 442      *
 443      * \param buf       A winsys buffer object to get the flags from.
 444      * \param md        Metadata
 445      */
 446     void (*buffer_get_metadata)(struct pb_buffer *buf,
 447                                 struct radeon_bo_metadata *md);
 448
 449     /**
 450      * Set buffer metadata.
 451      * (tiling info for display code, DRI sharing, and other data)
 452      *
 453      * \param buf       A winsys buffer object to set the flags for.
 454      * \param md        Metadata
 455      */
 456     void (*buffer_set_metadata)(struct pb_buffer *buf,
 457                                 struct radeon_bo_metadata *md);
 458
 459     /**
 460      * Get a winsys buffer from a winsys handle. The internal structure
 461      * of the handle is platform-specific and only a winsys should access it.
 462      *
 463      * \param ws        The winsys this function is called from.
 464      * \param whandle   A winsys handle pointer as was received from a state
 465      *                  tracker.
 466      * \param stride    The returned buffer stride in bytes.
 467      */
 468     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 469                                             struct winsys_handle *whandle,
 470                                             unsigned *stride, unsigned *offset);
 471
 472     /**
 473      * Get a winsys buffer from a user pointer. The resulting buffer can't
 474      * be exported. Both pointer and size must be page aligned.
 475      *
 476      * \param ws        The winsys this function is called from.
 477      * \param pointer   User pointer to turn into a buffer object.
 478      * \param Size      Size in bytes for the new buffer.
 479      */
 480     struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
 481                                          void *pointer, uint64_t size);
 482
 483     /**
 484      * Whether the buffer was created from a user pointer.
 485      *
 486      * \param buf       A winsys buffer object
 487      * \return          whether \p buf was created via buffer_from_ptr
 488      */
 489     bool (*buffer_is_user_ptr)(struct pb_buffer *buf);
 490
 491     /**
 492      * Get a winsys handle from a winsys buffer. The internal structure
 493      * of the handle is platform-specific and only a winsys should access it.
 494      *
 495      * \param buf       A winsys buffer object to get the handle from.
 496      * \param whandle   A winsys handle pointer.
 497      * \param stride    A stride of the buffer in bytes, for texturing.
 498      * \return          true on success.
 499      */
 500     bool (*buffer_get_handle)(struct pb_buffer *buf,
 501                               unsigned stride, unsigned offset,
 502                               unsigned slice_size,
 503                               struct winsys_handle *whandle);
 504
 505     /**
 506      * Return the virtual address of a buffer.
 507      *
 508      * \param buf       A winsys buffer object
 509      * \return          virtual address
 510      */
 511     uint64_t (*buffer_get_virtual_address)(struct pb_buffer *buf);
 512
 513     /**
 514      * Query the initial placement of the buffer from the kernel driver.
 515      */
 516     enum radeon_bo_domain (*buffer_get_initial_domain)(struct pb_buffer *buf);
 517
 518     /**************************************************************************
 519      * Command submission.
 520      *
 521      * Each pipe context should create its own command stream and submit
 522      * commands independently of other contexts.
 523      *************************************************************************/
 524
 525     /**
 526      * Create a command submission context.
 527      * Various command streams can be submitted to the same context.
 528      */
 529     struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 530
 531     /**
 532      * Destroy a context.
 533      */
 534     void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 535
 536     /**
 537      * Query a GPU reset status.
 538      */
 539     enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
 540
 541     /**
 542      * Create a command stream.
 543      *
 544      * \param ctx       The submission context
 545      * \param ring_type The ring type (GFX, DMA, UVD)
 546      * \param flush     Flush callback function associated with the command stream.
 547      * \param user      User pointer that will be passed to the flush callback.
 548      */
 549     struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys_ctx *ctx,
 550                                           enum ring_type ring_type,
 551                                           void (*flush)(void *ctx, unsigned flags,
 552                                                         struct pipe_fence_handle **fence),
 553                                           void *flush_ctx);
 554
 555     /**
 556      * Add a constant engine IB to a graphics CS. This makes the graphics CS
 557      * from "cs_create" a group of two IBs that share a buffer list and are
 558      * flushed together.
 559      *
 560      * The returned constant CS is only a stream for writing packets to the new
 561      * IB. Calling other winsys functions with it is not allowed, not even
 562      * "cs_destroy".
 563      *
 564      * In order to add buffers and check memory usage, use the graphics CS.
 565      * In order to flush it, use the graphics CS, which will flush both IBs.
 566      * Destroying the graphics CS will destroy both of them.
 567      *
 568      * \param cs  The graphics CS from "cs_create" that will hold the buffer
 569      *            list and will be used for flushing.
 570      */
 571     struct radeon_winsys_cs *(*cs_add_const_ib)(struct radeon_winsys_cs *cs);
 572
 573      /**
 574      * Add a constant engine preamble IB to a graphics CS. This add an extra IB
 575      * in similar manner to cs_add_const_ib. This should always be called after
 576      * cs_add_const_ib.
 577      *
 578      * The returned IB is a constant engine IB that only gets flushed if the
 579      * context changed.
 580      *
 581      * \param cs  The graphics CS from "cs_create" that will hold the buffer
 582      *            list and will be used for flushing.
 583      */
 584     struct radeon_winsys_cs *(*cs_add_const_preamble_ib)(struct radeon_winsys_cs *cs);
 585     /**
 586      * Destroy a command stream.
 587      *
 588      * \param cs        A command stream to destroy.
 589      */
 590     void (*cs_destroy)(struct radeon_winsys_cs *cs);
 591
 592     /**
 593      * Add a buffer. Each buffer used by a CS must be added using this function.
 594      *
 595      * \param cs      Command stream
 596      * \param buf     Buffer
 597      * \param usage   Whether the buffer is used for read and/or write.
 598      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 599      * \param priority  A higher number means a greater chance of being
 600      *                  placed in the requested domain. 15 is the maximum.
 601      * \return Buffer index.
 602      */
 603     unsigned (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 604                              struct pb_buffer *buf,
 605                              enum radeon_bo_usage usage,
 606                              enum radeon_bo_domain domain,
 607                              enum radeon_bo_priority priority);
 608
 609     /**
 610      * Return the index of an already-added buffer.
 611      *
 612      * Not supported on amdgpu. Drivers with GPUVM should not care about
 613      * buffer indices.
 614      *
 615      * \param cs        Command stream
 616      * \param buf       Buffer
 617      * \return          The buffer index, or -1 if the buffer has not been added.
 618      */
 619     int (*cs_lookup_buffer)(struct radeon_winsys_cs *cs,
 620                             struct pb_buffer *buf);
 621
 622     /**
 623      * Return true if there is enough memory in VRAM and GTT for the buffers
 624      * added so far. If the validation fails, all buffers which have
 625      * been added since the last call of cs_validate will be removed and
 626      * the CS will be flushed (provided there are still any buffers).
 627      *
 628      * \param cs        A command stream to validate.
 629      */
 630     bool (*cs_validate)(struct radeon_winsys_cs *cs);
 631
 632     /**
 633      * Check whether the given number of dwords is available in the IB.
 634      * Optionally chain a new chunk of the IB if necessary and supported.
 635      *
 636      * \param cs        A command stream.
 637      * \param dw        Number of CS dwords requested by the caller.
 638      */
 639     bool (*cs_check_space)(struct radeon_winsys_cs *cs, unsigned dw);
 640
 641     /**
 642      * Return the buffer list.
 643      *
 644      * \param cs    Command stream
 645      * \param list  Returned buffer list. Set to NULL to query the count only.
 646      * \return      The buffer count.
 647      */
 648     unsigned (*cs_get_buffer_list)(struct radeon_winsys_cs *cs,
 649                                    struct radeon_bo_list_item *list);
 650
 651     /**
 652      * Flush a command stream.
 653      *
 654      * \param cs          A command stream to flush.
 655      * \param flags,      RADEON_FLUSH_ASYNC or 0.
 656      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 657      *                    after the CS and is returned through this parameter.
 658      * \return Negative POSIX error code or 0 for success.
 659      *         Asynchronous submissions never return an error.
 660      */
 661     int (*cs_flush)(struct radeon_winsys_cs *cs,
 662                     unsigned flags,
 663                     struct pipe_fence_handle **fence);
 664
 665     /**
 666      * Create a fence before the CS is flushed.
 667      * The user must flush manually to complete the initializaton of the fence.
 668      * The fence must not be used before the flush.
 669      */
 670     struct pipe_fence_handle *(*cs_get_next_fence)(struct radeon_winsys_cs *cs);
 671
 672     /**
 673      * Return true if a buffer is referenced by a command stream.
 674      *
 675      * \param cs        A command stream.
 676      * \param buf       A winsys buffer.
 677      */
 678     bool (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
 679                                     struct pb_buffer *buf,
 680                                     enum radeon_bo_usage usage);
 681
 682     /**
 683      * Request access to a feature for a command stream.
 684      *
 685      * \param cs        A command stream.
 686      * \param fid       Feature ID, one of RADEON_FID_*
 687      * \param enable    Whether to enable or disable the feature.
 688      */
 689     bool (*cs_request_feature)(struct radeon_winsys_cs *cs,
 690                                enum radeon_feature_id fid,
 691                                bool enable);
 692      /**
 693       * Make sure all asynchronous flush of the cs have completed
 694       *
 695       * \param cs        A command stream.
 696       */
 697     void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
 698
 699     /**
 700      * Wait for the fence and return true if the fence has been signalled.
 701      * The timeout of 0 will only return the status.
 702      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 703      * is signalled.
 704      */
 705     bool (*fence_wait)(struct radeon_winsys *ws,
 706                        struct pipe_fence_handle *fence,
 707                        uint64_t timeout);
 708
 709     /**
 710      * Reference counting for fences.
 711      */
 712     void (*fence_reference)(struct pipe_fence_handle **dst,
 713                             struct pipe_fence_handle *src);
 714
 715     /**
 716      * Initialize surface
 717      *
 718      * \param ws        The winsys this function is called from.
 719      * \param surf      Surface structure ptr
 720      */
 721     int (*surface_init)(struct radeon_winsys *ws,
 722                         struct radeon_surf *surf);
 723
 724     /**
 725      * Find best values for a surface
 726      *
 727      * \param ws        The winsys this function is called from.
 728      * \param surf      Surface structure ptr
 729      */
 730     int (*surface_best)(struct radeon_winsys *ws,
 731                         struct radeon_surf *surf);
 732
 733     uint64_t (*query_value)(struct radeon_winsys *ws,
 734                             enum radeon_value_id value);
 735
 736     bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 737                            unsigned num_registers, uint32_t *out);
 738 };
 739
 740 static inline bool radeon_emitted(struct radeon_winsys_cs *cs, unsigned num_dw)
 741 {
 742     return cs && (cs->prev_dw + cs->current.cdw > num_dw);
 743 }
 744
 745 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 746 {
 747     cs->current.buf[cs->current.cdw++] = value;
 748 }
 749
 750 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 751                                      const uint32_t *values, unsigned count)
 752 {
 753     memcpy(cs->current.buf + cs->current.cdw, values, count * 4);
 754     cs->current.cdw += count;
 755 }
 756
 757 #endif