src/gallium/drivers/radeon/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #ifndef RADEON_WINSYS_H
  25 #define RADEON_WINSYS_H
  26
  27 /* The public winsys interface header for the radeon driver. */
  28
  29 #include "pipebuffer/pb_buffer.h"
  30
  31 #define RADEON_FLUSH_ASYNC              (1 << 0)
  32 #define RADEON_FLUSH_KEEP_TILING_FLAGS  (1 << 1)
  33 #define RADEON_FLUSH_END_OF_FRAME       (1 << 2)
  34
  35 /* Tiling flags. */
  36 enum radeon_bo_layout {
  37     RADEON_LAYOUT_LINEAR = 0,
  38     RADEON_LAYOUT_TILED,
  39     RADEON_LAYOUT_SQUARETILED,
  40
  41     RADEON_LAYOUT_UNKNOWN
  42 };
  43
  44 enum radeon_bo_domain { /* bitfield */
  45     RADEON_DOMAIN_GTT  = 2,
  46     RADEON_DOMAIN_VRAM = 4,
  47     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  48 };
  49
  50 enum radeon_bo_flag { /* bitfield */
  51     RADEON_FLAG_GTT_WC =        (1 << 0),
  52     RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  53     RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  54 };
  55
  56 enum radeon_bo_usage { /* bitfield */
  57     RADEON_USAGE_READ = 2,
  58     RADEON_USAGE_WRITE = 4,
  59     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
  60 };
  61
  62 enum radeon_family {
  63     CHIP_UNKNOWN = 0,
  64     CHIP_R300, /* R3xx-based cores. */
  65     CHIP_R350,
  66     CHIP_RV350,
  67     CHIP_RV370,
  68     CHIP_RV380,
  69     CHIP_RS400,
  70     CHIP_RC410,
  71     CHIP_RS480,
  72     CHIP_R420,     /* R4xx-based cores. */
  73     CHIP_R423,
  74     CHIP_R430,
  75     CHIP_R480,
  76     CHIP_R481,
  77     CHIP_RV410,
  78     CHIP_RS600,
  79     CHIP_RS690,
  80     CHIP_RS740,
  81     CHIP_RV515,    /* R5xx-based cores. */
  82     CHIP_R520,
  83     CHIP_RV530,
  84     CHIP_R580,
  85     CHIP_RV560,
  86     CHIP_RV570,
  87     CHIP_R600,
  88     CHIP_RV610,
  89     CHIP_RV630,
  90     CHIP_RV670,
  91     CHIP_RV620,
  92     CHIP_RV635,
  93     CHIP_RS780,
  94     CHIP_RS880,
  95     CHIP_RV770,
  96     CHIP_RV730,
  97     CHIP_RV710,
  98     CHIP_RV740,
  99     CHIP_CEDAR,
 100     CHIP_REDWOOD,
 101     CHIP_JUNIPER,
 102     CHIP_CYPRESS,
 103     CHIP_HEMLOCK,
 104     CHIP_PALM,
 105     CHIP_SUMO,
 106     CHIP_SUMO2,
 107     CHIP_BARTS,
 108     CHIP_TURKS,
 109     CHIP_CAICOS,
 110     CHIP_CAYMAN,
 111     CHIP_ARUBA,
 112     CHIP_TAHITI,
 113     CHIP_PITCAIRN,
 114     CHIP_VERDE,
 115     CHIP_OLAND,
 116     CHIP_HAINAN,
 117     CHIP_BONAIRE,
 118     CHIP_KAVERI,
 119     CHIP_KABINI,
 120     CHIP_HAWAII,
 121     CHIP_MULLINS,
 122     CHIP_TONGA,
 123     CHIP_ICELAND,
 124     CHIP_CARRIZO,
 125     CHIP_FIJI,
 126     CHIP_STONEY,
 127     CHIP_POLARIS10,
 128     CHIP_POLARIS11,
 129     CHIP_LAST,
 130 };
 131
 132 enum chip_class {
 133     CLASS_UNKNOWN = 0,
 134     R300,
 135     R400,
 136     R500,
 137     R600,
 138     R700,
 139     EVERGREEN,
 140     CAYMAN,
 141     SI,
 142     CIK,
 143     VI,
 144 };
 145
 146 enum ring_type {
 147     RING_GFX = 0,
 148     RING_COMPUTE,
 149     RING_DMA,
 150     RING_UVD,
 151     RING_VCE,
 152     RING_LAST,
 153 };
 154
 155 enum radeon_value_id {
 156     RADEON_REQUESTED_VRAM_MEMORY,
 157     RADEON_REQUESTED_GTT_MEMORY,
 158     RADEON_BUFFER_WAIT_TIME_NS,
 159     RADEON_TIMESTAMP,
 160     RADEON_NUM_CS_FLUSHES,
 161     RADEON_NUM_BYTES_MOVED,
 162     RADEON_VRAM_USAGE,
 163     RADEON_GTT_USAGE,
 164     RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
 165     RADEON_CURRENT_SCLK,
 166     RADEON_CURRENT_MCLK,
 167     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
 168 };
 169
 170 /* Each group of four has the same priority. */
 171 enum radeon_bo_priority {
 172     RADEON_PRIO_FENCE = 0,
 173     RADEON_PRIO_TRACE,
 174     RADEON_PRIO_SO_FILLED_SIZE,
 175     RADEON_PRIO_QUERY,
 176
 177     RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
 178     RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
 179     RADEON_PRIO_DRAW_INDIRECT,
 180     RADEON_PRIO_INDEX_BUFFER,
 181
 182     RADEON_PRIO_CP_DMA = 8,
 183
 184     RADEON_PRIO_VCE = 12,
 185     RADEON_PRIO_UVD,
 186     RADEON_PRIO_SDMA_BUFFER,
 187     RADEON_PRIO_SDMA_TEXTURE,
 188
 189     RADEON_PRIO_USER_SHADER = 16,
 190     RADEON_PRIO_INTERNAL_SHADER, /* fetch shader, etc. */
 191
 192     /* gap: 20 */
 193
 194     RADEON_PRIO_CONST_BUFFER = 24,
 195     RADEON_PRIO_DESCRIPTORS,
 196     RADEON_PRIO_BORDER_COLORS,
 197
 198     RADEON_PRIO_SAMPLER_BUFFER = 28,
 199     RADEON_PRIO_VERTEX_BUFFER,
 200
 201     RADEON_PRIO_SHADER_RW_BUFFER = 32,
 202     RADEON_PRIO_RINGS_STREAMOUT,
 203     RADEON_PRIO_SCRATCH_BUFFER,
 204     RADEON_PRIO_COMPUTE_GLOBAL,
 205
 206     RADEON_PRIO_SAMPLER_TEXTURE = 36,
 207     RADEON_PRIO_SHADER_RW_IMAGE,
 208
 209     RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 40,
 210
 211     RADEON_PRIO_COLOR_BUFFER = 44,
 212
 213     RADEON_PRIO_DEPTH_BUFFER = 48,
 214
 215     RADEON_PRIO_COLOR_BUFFER_MSAA = 52,
 216
 217     RADEON_PRIO_DEPTH_BUFFER_MSAA = 56,
 218
 219     RADEON_PRIO_CMASK = 60,
 220     RADEON_PRIO_DCC,
 221     RADEON_PRIO_HTILE,
 222     /* 63 is the maximum value */
 223 };
 224
 225 struct winsys_handle;
 226 struct radeon_winsys_ctx;
 227
 228 struct radeon_winsys_cs_chunk {
 229     unsigned cdw;  /* Number of used dwords. */
 230     unsigned max_dw; /* Maximum number of dwords. */
 231     uint32_t *buf; /* The base pointer of the chunk. */
 232 };
 233
 234 struct radeon_winsys_cs {
 235     struct radeon_winsys_cs_chunk current;
 236     struct radeon_winsys_cs_chunk *prev;
 237     unsigned                      num_prev; /* Number of previous chunks. */
 238     unsigned                      max_prev; /* Space in array pointed to by prev. */
 239     unsigned                      prev_dw; /* Total number of dwords in previous chunks. */
 240 };
 241
 242 struct radeon_info {
 243     /* PCI info: domain:bus:dev:func */
 244     uint32_t                    pci_domain;
 245     uint32_t                    pci_bus;
 246     uint32_t                    pci_dev;
 247     uint32_t                    pci_func;
 248
 249     /* Device info. */
 250     uint32_t                    pci_id;
 251     enum radeon_family          family;
 252     enum chip_class             chip_class;
 253     uint32_t                    gart_page_size;
 254     uint64_t                    gart_size;
 255     uint64_t                    vram_size;
 256     uint64_t                    max_alloc_size;
 257     bool                        has_dedicated_vram;
 258     bool                        has_virtual_memory;
 259     bool                        gfx_ib_pad_with_type2;
 260     bool                        has_sdma;
 261     bool                        has_uvd;
 262     uint32_t                    uvd_fw_version;
 263     uint32_t                    vce_fw_version;
 264     uint32_t                    vce_harvest_config;
 265     uint32_t                    clock_crystal_freq;
 266
 267     /* Kernel info. */
 268     uint32_t                    drm_major; /* version */
 269     uint32_t                    drm_minor;
 270     uint32_t                    drm_patchlevel;
 271     bool                        has_userptr;
 272
 273     /* Shader cores. */
 274     uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
 275     uint32_t                    max_shader_clock;
 276     uint32_t                    num_good_compute_units;
 277     uint32_t                    max_se; /* shader engines */
 278     uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 279
 280     /* Render backends (color + depth blocks). */
 281     uint32_t                    r300_num_gb_pipes;
 282     uint32_t                    r300_num_z_pipes;
 283     uint32_t                    r600_gb_backend_map; /* R600 harvest config */
 284     bool                        r600_gb_backend_map_valid;
 285     uint32_t                    r600_num_banks;
 286     uint32_t                    num_render_backends;
 287     uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
 288     uint32_t                    pipe_interleave_bytes;
 289     uint32_t                    enabled_rb_mask; /* GCN harvest config */
 290
 291     /* Tile modes. */
 292     uint32_t                    si_tile_mode_array[32];
 293     uint32_t                    cik_macrotile_mode_array[16];
 294 };
 295
 296 /* Tiling info for display code, DRI sharing, and other data. */
 297 struct radeon_bo_metadata {
 298     /* Tiling flags describing the texture layout for display code
 299      * and DRI sharing.
 300      */
 301     enum radeon_bo_layout   microtile;
 302     enum radeon_bo_layout   macrotile;
 303     unsigned                pipe_config;
 304     unsigned                bankw;
 305     unsigned                bankh;
 306     unsigned                tile_split;
 307     unsigned                mtilea;
 308     unsigned                num_banks;
 309     unsigned                stride;
 310     bool                    scanout;
 311
 312     /* Additional metadata associated with the buffer, in bytes.
 313      * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 314      * Supported by amdgpu only.
 315      */
 316     uint32_t                size_metadata;
 317     uint32_t                metadata[64];
 318 };
 319
 320 enum radeon_feature_id {
 321     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 322     RADEON_FID_R300_CMASK_ACCESS,
 323 };
 324
 325 #define RADEON_SURF_MAX_LEVEL                   32
 326
 327 #define RADEON_SURF_TYPE_MASK                   0xFF
 328 #define RADEON_SURF_TYPE_SHIFT                  0
 329 #define     RADEON_SURF_TYPE_1D                     0
 330 #define     RADEON_SURF_TYPE_2D                     1
 331 #define     RADEON_SURF_TYPE_3D                     2
 332 #define     RADEON_SURF_TYPE_CUBEMAP                3
 333 #define     RADEON_SURF_TYPE_1D_ARRAY               4
 334 #define     RADEON_SURF_TYPE_2D_ARRAY               5
 335 #define RADEON_SURF_MODE_MASK                   0xFF
 336 #define RADEON_SURF_MODE_SHIFT                  8
 337 #define     RADEON_SURF_MODE_LINEAR_ALIGNED         1
 338 #define     RADEON_SURF_MODE_1D                     2
 339 #define     RADEON_SURF_MODE_2D                     3
 340 #define RADEON_SURF_SCANOUT                     (1 << 16)
 341 #define RADEON_SURF_ZBUFFER                     (1 << 17)
 342 #define RADEON_SURF_SBUFFER                     (1 << 18)
 343 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
 344 #define RADEON_SURF_HAS_SBUFFER_MIPTREE         (1 << 19)
 345 #define RADEON_SURF_HAS_TILE_MODE_INDEX         (1 << 20)
 346 #define RADEON_SURF_FMASK                       (1 << 21)
 347 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
 348
 349 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
 350 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
 351 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
 352
 353 struct radeon_surf_level {
 354     uint64_t                    offset;
 355     uint64_t                    slice_size;
 356     uint32_t                    npix_x;
 357     uint32_t                    npix_y;
 358     uint32_t                    npix_z;
 359     uint32_t                    nblk_x;
 360     uint32_t                    nblk_y;
 361     uint32_t                    nblk_z;
 362     uint32_t                    pitch_bytes;
 363     uint32_t                    mode;
 364     uint64_t                    dcc_offset;
 365     uint64_t                    dcc_fast_clear_size;
 366     bool                        dcc_enabled;
 367 };
 368
 369 struct radeon_surf {
 370     /* These are inputs to the calculator. */
 371     uint32_t                    npix_x;
 372     uint32_t                    npix_y;
 373     uint32_t                    npix_z;
 374     uint32_t                    blk_w;
 375     uint32_t                    blk_h;
 376     uint32_t                    blk_d;
 377     uint32_t                    array_size;
 378     uint32_t                    last_level;
 379     uint32_t                    bpe;
 380     uint32_t                    nsamples;
 381     uint32_t                    flags;
 382
 383     /* These are return values. Some of them can be set by the caller, but
 384      * they will be treated as hints (e.g. bankw, bankh) and might be
 385      * changed by the calculator.
 386      */
 387     uint64_t                    bo_size;
 388     uint64_t                    bo_alignment;
 389     /* This applies to EG and later. */
 390     uint32_t                    bankw;
 391     uint32_t                    bankh;
 392     uint32_t                    mtilea;
 393     uint32_t                    tile_split;
 394     uint32_t                    stencil_tile_split;
 395     struct radeon_surf_level    level[RADEON_SURF_MAX_LEVEL];
 396     struct radeon_surf_level    stencil_level[RADEON_SURF_MAX_LEVEL];
 397     uint32_t                    tiling_index[RADEON_SURF_MAX_LEVEL];
 398     uint32_t                    stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
 399     uint32_t                    pipe_config;
 400     uint32_t                    num_banks;
 401     uint32_t                    macro_tile_index;
 402     uint32_t                    micro_tile_mode; /* displayable, thin, depth, rotated */
 403
 404     /* Whether the depth miptree or stencil miptree as used by the DB are
 405      * adjusted from their TC compatible form to ensure depth/stencil
 406      * compatibility. If either is true, the corresponding plane cannot be
 407      * sampled from.
 408      */
 409     bool                        depth_adjusted;
 410     bool                        stencil_adjusted;
 411
 412     uint64_t                    dcc_size;
 413     uint64_t                    dcc_alignment;
 414 };
 415
 416 struct radeon_bo_list_item {
 417     struct pb_buffer *buf;
 418     uint64_t vm_address;
 419     uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
 420 };
 421
 422 struct radeon_winsys {
 423     /**
 424      * The screen object this winsys was created for
 425      */
 426     struct pipe_screen *screen;
 427
 428     /**
 429      * Decrement the winsys reference count.
 430      *
 431      * \param ws  The winsys this function is called for.
 432      * \return    True if the winsys and screen should be destroyed.
 433      */
 434     bool (*unref)(struct radeon_winsys *ws);
 435
 436     /**
 437      * Destroy this winsys.
 438      *
 439      * \param ws        The winsys this function is called from.
 440      */
 441     void (*destroy)(struct radeon_winsys *ws);
 442
 443     /**
 444      * Query an info structure from winsys.
 445      *
 446      * \param ws        The winsys this function is called from.
 447      * \param info      Return structure
 448      */
 449     void (*query_info)(struct radeon_winsys *ws,
 450                        struct radeon_info *info);
 451
 452     /**************************************************************************
 453      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 454      *
 455      * Remember that gallium gets to choose the interface it needs, and the
 456      * window systems must then implement that interface (rather than the
 457      * other way around...).
 458      *************************************************************************/
 459
 460     /**
 461      * Create a buffer object.
 462      *
 463      * \param ws        The winsys this function is called from.
 464      * \param size      The size to allocate.
 465      * \param alignment An alignment of the buffer in memory.
 466      * \param use_reusable_pool Whether the cache buffer manager should be used.
 467      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 468      * \return          The created buffer object.
 469      */
 470     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 471                                        uint64_t size,
 472                                        unsigned alignment,
 473                                        enum radeon_bo_domain domain,
 474                                        enum radeon_bo_flag flags);
 475
 476     /**
 477      * Map the entire data store of a buffer object into the client's address
 478      * space.
 479      *
 480      * \param buf       A winsys buffer object to map.
 481      * \param cs        A command stream to flush if the buffer is referenced by it.
 482      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 483      * \return          The pointer at the beginning of the buffer.
 484      */
 485     void *(*buffer_map)(struct pb_buffer *buf,
 486                         struct radeon_winsys_cs *cs,
 487                         enum pipe_transfer_usage usage);
 488
 489     /**
 490      * Unmap a buffer object from the client's address space.
 491      *
 492      * \param buf       A winsys buffer object to unmap.
 493      */
 494     void (*buffer_unmap)(struct pb_buffer *buf);
 495
 496     /**
 497      * Wait for the buffer and return true if the buffer is not used
 498      * by the device.
 499      *
 500      * The timeout of 0 will only return the status.
 501      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
 502      * is idle.
 503      */
 504     bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
 505                         enum radeon_bo_usage usage);
 506
 507     /**
 508      * Return buffer metadata.
 509      * (tiling info for display code, DRI sharing, and other data)
 510      *
 511      * \param buf       A winsys buffer object to get the flags from.
 512      * \param md        Metadata
 513      */
 514     void (*buffer_get_metadata)(struct pb_buffer *buf,
 515                                 struct radeon_bo_metadata *md);
 516
 517     /**
 518      * Set buffer metadata.
 519      * (tiling info for display code, DRI sharing, and other data)
 520      *
 521      * \param buf       A winsys buffer object to set the flags for.
 522      * \param md        Metadata
 523      */
 524     void (*buffer_set_metadata)(struct pb_buffer *buf,
 525                                 struct radeon_bo_metadata *md);
 526
 527     /**
 528      * Get a winsys buffer from a winsys handle. The internal structure
 529      * of the handle is platform-specific and only a winsys should access it.
 530      *
 531      * \param ws        The winsys this function is called from.
 532      * \param whandle   A winsys handle pointer as was received from a state
 533      *                  tracker.
 534      * \param stride    The returned buffer stride in bytes.
 535      */
 536     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 537                                             struct winsys_handle *whandle,
 538                                             unsigned *stride, unsigned *offset);
 539
 540     /**
 541      * Get a winsys buffer from a user pointer. The resulting buffer can't
 542      * be exported. Both pointer and size must be page aligned.
 543      *
 544      * \param ws        The winsys this function is called from.
 545      * \param pointer   User pointer to turn into a buffer object.
 546      * \param Size      Size in bytes for the new buffer.
 547      */
 548     struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
 549                                          void *pointer, uint64_t size);
 550
 551     /**
 552      * Whether the buffer was created from a user pointer.
 553      *
 554      * \param buf       A winsys buffer object
 555      * \return          whether \p buf was created via buffer_from_ptr
 556      */
 557     bool (*buffer_is_user_ptr)(struct pb_buffer *buf);
 558
 559     /**
 560      * Get a winsys handle from a winsys buffer. The internal structure
 561      * of the handle is platform-specific and only a winsys should access it.
 562      *
 563      * \param buf       A winsys buffer object to get the handle from.
 564      * \param whandle   A winsys handle pointer.
 565      * \param stride    A stride of the buffer in bytes, for texturing.
 566      * \return          true on success.
 567      */
 568     bool (*buffer_get_handle)(struct pb_buffer *buf,
 569                               unsigned stride, unsigned offset,
 570                               unsigned slice_size,
 571                               struct winsys_handle *whandle);
 572
 573     /**
 574      * Return the virtual address of a buffer.
 575      *
 576      * \param buf       A winsys buffer object
 577      * \return          virtual address
 578      */
 579     uint64_t (*buffer_get_virtual_address)(struct pb_buffer *buf);
 580
 581     /**
 582      * Query the initial placement of the buffer from the kernel driver.
 583      */
 584     enum radeon_bo_domain (*buffer_get_initial_domain)(struct pb_buffer *buf);
 585
 586     /**************************************************************************
 587      * Command submission.
 588      *
 589      * Each pipe context should create its own command stream and submit
 590      * commands independently of other contexts.
 591      *************************************************************************/
 592
 593     /**
 594      * Create a command submission context.
 595      * Various command streams can be submitted to the same context.
 596      */
 597     struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 598
 599     /**
 600      * Destroy a context.
 601      */
 602     void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 603
 604     /**
 605      * Query a GPU reset status.
 606      */
 607     enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
 608
 609     /**
 610      * Create a command stream.
 611      *
 612      * \param ctx       The submission context
 613      * \param ring_type The ring type (GFX, DMA, UVD)
 614      * \param flush     Flush callback function associated with the command stream.
 615      * \param user      User pointer that will be passed to the flush callback.
 616      */
 617     struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys_ctx *ctx,
 618                                           enum ring_type ring_type,
 619                                           void (*flush)(void *ctx, unsigned flags,
 620                                                         struct pipe_fence_handle **fence),
 621                                           void *flush_ctx);
 622
 623     /**
 624      * Add a constant engine IB to a graphics CS. This makes the graphics CS
 625      * from "cs_create" a group of two IBs that share a buffer list and are
 626      * flushed together.
 627      *
 628      * The returned constant CS is only a stream for writing packets to the new
 629      * IB. Calling other winsys functions with it is not allowed, not even
 630      * "cs_destroy".
 631      *
 632      * In order to add buffers and check memory usage, use the graphics CS.
 633      * In order to flush it, use the graphics CS, which will flush both IBs.
 634      * Destroying the graphics CS will destroy both of them.
 635      *
 636      * \param cs  The graphics CS from "cs_create" that will hold the buffer
 637      *            list and will be used for flushing.
 638      */
 639     struct radeon_winsys_cs *(*cs_add_const_ib)(struct radeon_winsys_cs *cs);
 640
 641      /**
 642      * Add a constant engine preamble IB to a graphics CS. This add an extra IB
 643      * in similar manner to cs_add_const_ib. This should always be called after
 644      * cs_add_const_ib.
 645      *
 646      * The returned IB is a constant engine IB that only gets flushed if the
 647      * context changed.
 648      *
 649      * \param cs  The graphics CS from "cs_create" that will hold the buffer
 650      *            list and will be used for flushing.
 651      */
 652     struct radeon_winsys_cs *(*cs_add_const_preamble_ib)(struct radeon_winsys_cs *cs);
 653     /**
 654      * Destroy a command stream.
 655      *
 656      * \param cs        A command stream to destroy.
 657      */
 658     void (*cs_destroy)(struct radeon_winsys_cs *cs);
 659
 660     /**
 661      * Add a buffer. Each buffer used by a CS must be added using this function.
 662      *
 663      * \param cs      Command stream
 664      * \param buf     Buffer
 665      * \param usage   Whether the buffer is used for read and/or write.
 666      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 667      * \param priority  A higher number means a greater chance of being
 668      *                  placed in the requested domain. 15 is the maximum.
 669      * \return Buffer index.
 670      */
 671     unsigned (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 672                              struct pb_buffer *buf,
 673                              enum radeon_bo_usage usage,
 674                              enum radeon_bo_domain domain,
 675                              enum radeon_bo_priority priority);
 676
 677     /**
 678      * Return the index of an already-added buffer.
 679      *
 680      * \param cs        Command stream
 681      * \param buf       Buffer
 682      * \return          The buffer index, or -1 if the buffer has not been added.
 683      */
 684     int (*cs_lookup_buffer)(struct radeon_winsys_cs *cs,
 685                             struct pb_buffer *buf);
 686
 687     /**
 688      * Return true if there is enough memory in VRAM and GTT for the buffers
 689      * added so far. If the validation fails, all buffers which have
 690      * been added since the last call of cs_validate will be removed and
 691      * the CS will be flushed (provided there are still any buffers).
 692      *
 693      * \param cs        A command stream to validate.
 694      */
 695     bool (*cs_validate)(struct radeon_winsys_cs *cs);
 696
 697     /**
 698      * Check whether the given number of dwords is available in the IB.
 699      * Optionally chain a new chunk of the IB if necessary and supported.
 700      *
 701      * \param cs        A command stream.
 702      * \param dw        Number of CS dwords requested by the caller.
 703      */
 704     bool (*cs_check_space)(struct radeon_winsys_cs *cs, unsigned dw);
 705
 706     /**
 707      * Return true if there is enough memory in VRAM and GTT for the buffers
 708      * added so far.
 709      *
 710      * \param cs        A command stream to validate.
 711      * \param vram      VRAM memory size pending to be use
 712      * \param gtt       GTT memory size pending to be use
 713      */
 714     bool (*cs_memory_below_limit)(struct radeon_winsys_cs *cs,
 715                                   uint64_t vram, uint64_t gtt);
 716
 717     uint64_t (*cs_query_memory_usage)(struct radeon_winsys_cs *cs);
 718
 719     /**
 720      * Return the buffer list.
 721      *
 722      * \param cs    Command stream
 723      * \param list  Returned buffer list. Set to NULL to query the count only.
 724      * \return      The buffer count.
 725      */
 726     unsigned (*cs_get_buffer_list)(struct radeon_winsys_cs *cs,
 727                                    struct radeon_bo_list_item *list);
 728
 729     /**
 730      * Flush a command stream.
 731      *
 732      * \param cs          A command stream to flush.
 733      * \param flags,      RADEON_FLUSH_ASYNC or 0.
 734      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 735      *                    after the CS and is returned through this parameter.
 736      */
 737     void (*cs_flush)(struct radeon_winsys_cs *cs,
 738                      unsigned flags,
 739                      struct pipe_fence_handle **fence);
 740
 741     /**
 742      * Return true if a buffer is referenced by a command stream.
 743      *
 744      * \param cs        A command stream.
 745      * \param buf       A winsys buffer.
 746      */
 747     bool (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
 748                                     struct pb_buffer *buf,
 749                                     enum radeon_bo_usage usage);
 750
 751     /**
 752      * Request access to a feature for a command stream.
 753      *
 754      * \param cs        A command stream.
 755      * \param fid       Feature ID, one of RADEON_FID_*
 756      * \param enable    Whether to enable or disable the feature.
 757      */
 758     bool (*cs_request_feature)(struct radeon_winsys_cs *cs,
 759                                enum radeon_feature_id fid,
 760                                bool enable);
 761      /**
 762       * Make sure all asynchronous flush of the cs have completed
 763       *
 764       * \param cs        A command stream.
 765       */
 766     void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
 767
 768     /**
 769      * Wait for the fence and return true if the fence has been signalled.
 770      * The timeout of 0 will only return the status.
 771      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 772      * is signalled.
 773      */
 774     bool (*fence_wait)(struct radeon_winsys *ws,
 775                        struct pipe_fence_handle *fence,
 776                        uint64_t timeout);
 777
 778     /**
 779      * Reference counting for fences.
 780      */
 781     void (*fence_reference)(struct pipe_fence_handle **dst,
 782                             struct pipe_fence_handle *src);
 783
 784     /**
 785      * Initialize surface
 786      *
 787      * \param ws        The winsys this function is called from.
 788      * \param surf      Surface structure ptr
 789      */
 790     int (*surface_init)(struct radeon_winsys *ws,
 791                         struct radeon_surf *surf);
 792
 793     /**
 794      * Find best values for a surface
 795      *
 796      * \param ws        The winsys this function is called from.
 797      * \param surf      Surface structure ptr
 798      */
 799     int (*surface_best)(struct radeon_winsys *ws,
 800                         struct radeon_surf *surf);
 801
 802     uint64_t (*query_value)(struct radeon_winsys *ws,
 803                             enum radeon_value_id value);
 804
 805     bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 806                            unsigned num_registers, uint32_t *out);
 807 };
 808
 809 static inline bool radeon_emitted(struct radeon_winsys_cs *cs, unsigned num_dw)
 810 {
 811     return cs && (cs->prev_dw + cs->current.cdw > num_dw);
 812 }
 813
 814 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 815 {
 816     cs->current.buf[cs->current.cdw++] = value;
 817 }
 818
 819 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 820                                      const uint32_t *values, unsigned count)
 821 {
 822     memcpy(cs->current.buf + cs->current.cdw, values, count * 4);
 823     cs->current.cdw += count;
 824 }
 825
 826 #endif