2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 #ifndef RADEON_WINSYS_H
25 #define RADEON_WINSYS_H
27 /* The public winsys interface header for the radeon driver. */
29 #include "pipebuffer/pb_buffer.h"
31 #include "amd/common/amd_family.h"
33 #define RADEON_FLUSH_ASYNC (1 << 0)
34 #define RADEON_FLUSH_END_OF_FRAME (1 << 1)
37 enum radeon_bo_layout
{
38 RADEON_LAYOUT_LINEAR
= 0,
40 RADEON_LAYOUT_SQUARETILED
,
45 enum radeon_bo_domain
{ /* bitfield */
46 RADEON_DOMAIN_GTT
= 2,
47 RADEON_DOMAIN_VRAM
= 4,
48 RADEON_DOMAIN_VRAM_GTT
= RADEON_DOMAIN_VRAM
| RADEON_DOMAIN_GTT
51 enum radeon_bo_flag
{ /* bitfield */
52 RADEON_FLAG_GTT_WC
= (1 << 0),
53 RADEON_FLAG_CPU_ACCESS
= (1 << 1),
54 RADEON_FLAG_NO_CPU_ACCESS
= (1 << 2),
55 RADEON_FLAG_HANDLE
= (1 << 3), /* the buffer most not be suballocated */
58 enum radeon_bo_usage
{ /* bitfield */
59 RADEON_USAGE_READ
= 2,
60 RADEON_USAGE_WRITE
= 4,
61 RADEON_USAGE_READWRITE
= RADEON_USAGE_READ
| RADEON_USAGE_WRITE
,
63 /* The winsys ensures that the CS submission will be scheduled after
64 * previously flushed CSs referencing this BO in a conflicting way.
66 RADEON_USAGE_SYNCHRONIZED
= 8
78 enum radeon_value_id
{
79 RADEON_REQUESTED_VRAM_MEMORY
,
80 RADEON_REQUESTED_GTT_MEMORY
,
83 RADEON_BUFFER_WAIT_TIME_NS
,
85 RADEON_NUM_CS_FLUSHES
,
86 RADEON_NUM_BYTES_MOVED
,
90 RADEON_GPU_TEMPERATURE
, /* DRM 2.42.0 */
93 RADEON_GPU_RESET_COUNTER
, /* DRM 2.43.0 */
96 /* Each group of four has the same priority. */
97 enum radeon_bo_priority
{
98 RADEON_PRIO_FENCE
= 0,
100 RADEON_PRIO_SO_FILLED_SIZE
,
103 RADEON_PRIO_IB1
= 4, /* main IB submitted to the kernel */
104 RADEON_PRIO_IB2
, /* IB executed with INDIRECT_BUFFER */
105 RADEON_PRIO_DRAW_INDIRECT
,
106 RADEON_PRIO_INDEX_BUFFER
,
110 RADEON_PRIO_SDMA_BUFFER
,
111 RADEON_PRIO_SDMA_TEXTURE
,
113 RADEON_PRIO_CP_DMA
= 12,
115 RADEON_PRIO_CONST_BUFFER
= 16,
116 RADEON_PRIO_DESCRIPTORS
,
117 RADEON_PRIO_BORDER_COLORS
,
119 RADEON_PRIO_SAMPLER_BUFFER
= 20,
120 RADEON_PRIO_VERTEX_BUFFER
,
122 RADEON_PRIO_SHADER_RW_BUFFER
= 24,
123 RADEON_PRIO_COMPUTE_GLOBAL
,
125 RADEON_PRIO_SAMPLER_TEXTURE
= 28,
126 RADEON_PRIO_SHADER_RW_IMAGE
,
128 RADEON_PRIO_SAMPLER_TEXTURE_MSAA
= 32,
130 RADEON_PRIO_COLOR_BUFFER
= 36,
132 RADEON_PRIO_DEPTH_BUFFER
= 40,
134 RADEON_PRIO_COLOR_BUFFER_MSAA
= 44,
136 RADEON_PRIO_DEPTH_BUFFER_MSAA
= 48,
138 RADEON_PRIO_CMASK
= 52,
141 RADEON_PRIO_SHADER_BINARY
, /* the hw can't hide instruction cache misses */
143 RADEON_PRIO_SHADER_RINGS
= 56,
145 RADEON_PRIO_SCRATCH_BUFFER
= 60,
146 /* 63 is the maximum value */
149 struct winsys_handle
;
150 struct radeon_winsys_ctx
;
152 struct radeon_winsys_cs_chunk
{
153 unsigned cdw
; /* Number of used dwords. */
154 unsigned max_dw
; /* Maximum number of dwords. */
155 uint32_t *buf
; /* The base pointer of the chunk. */
158 struct radeon_winsys_cs
{
159 struct radeon_winsys_cs_chunk current
;
160 struct radeon_winsys_cs_chunk
*prev
;
161 unsigned num_prev
; /* Number of previous chunks. */
162 unsigned max_prev
; /* Space in array pointed to by prev. */
163 unsigned prev_dw
; /* Total number of dwords in previous chunks. */
165 /* Memory usage of the buffer list. These are always 0 for CE and preamble
172 /* PCI info: domain:bus:dev:func */
180 enum radeon_family family
;
181 enum chip_class chip_class
;
182 uint32_t gart_page_size
;
185 uint64_t max_alloc_size
;
186 uint32_t min_alloc_size
;
187 bool has_dedicated_vram
;
188 bool has_virtual_memory
;
189 bool gfx_ib_pad_with_type2
;
192 uint32_t uvd_fw_version
;
193 uint32_t vce_fw_version
;
194 uint32_t me_fw_version
;
195 uint32_t pfp_fw_version
;
196 uint32_t ce_fw_version
;
197 uint32_t vce_harvest_config
;
198 uint32_t clock_crystal_freq
;
201 uint32_t drm_major
; /* version */
203 uint32_t drm_patchlevel
;
207 uint32_t r600_max_quad_pipes
; /* wave size / 16 */
208 uint32_t max_shader_clock
;
209 uint32_t num_good_compute_units
;
210 uint32_t max_se
; /* shader engines */
211 uint32_t max_sh_per_se
; /* shader arrays per shader engine */
213 /* Render backends (color + depth blocks). */
214 uint32_t r300_num_gb_pipes
;
215 uint32_t r300_num_z_pipes
;
216 uint32_t r600_gb_backend_map
; /* R600 harvest config */
217 bool r600_gb_backend_map_valid
;
218 uint32_t r600_num_banks
;
219 uint32_t num_render_backends
;
220 uint32_t num_tile_pipes
; /* pipe count from PIPE_CONFIG */
221 uint32_t pipe_interleave_bytes
;
222 uint32_t enabled_rb_mask
; /* GCN harvest config */
225 uint32_t si_tile_mode_array
[32];
226 uint32_t cik_macrotile_mode_array
[16];
229 /* Tiling info for display code, DRI sharing, and other data. */
230 struct radeon_bo_metadata
{
231 /* Tiling flags describing the texture layout for display code
234 enum radeon_bo_layout microtile
;
235 enum radeon_bo_layout macrotile
;
236 unsigned pipe_config
;
245 /* Additional metadata associated with the buffer, in bytes.
246 * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
247 * Supported by amdgpu only.
249 uint32_t size_metadata
;
250 uint32_t metadata
[64];
253 enum radeon_feature_id
{
254 RADEON_FID_R300_HYPERZ_ACCESS
, /* ZMask + HiZ */
255 RADEON_FID_R300_CMASK_ACCESS
,
258 #define RADEON_SURF_MAX_LEVEL 32
260 #define RADEON_SURF_TYPE_MASK 0xFF
261 #define RADEON_SURF_TYPE_SHIFT 0
262 #define RADEON_SURF_TYPE_1D 0
263 #define RADEON_SURF_TYPE_2D 1
264 #define RADEON_SURF_TYPE_3D 2
265 #define RADEON_SURF_TYPE_CUBEMAP 3
266 #define RADEON_SURF_TYPE_1D_ARRAY 4
267 #define RADEON_SURF_TYPE_2D_ARRAY 5
268 #define RADEON_SURF_MODE_MASK 0xFF
269 #define RADEON_SURF_MODE_SHIFT 8
270 #define RADEON_SURF_MODE_LINEAR_ALIGNED 1
271 #define RADEON_SURF_MODE_1D 2
272 #define RADEON_SURF_MODE_2D 3
273 #define RADEON_SURF_SCANOUT (1 << 16)
274 #define RADEON_SURF_ZBUFFER (1 << 17)
275 #define RADEON_SURF_SBUFFER (1 << 18)
276 #define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
277 #define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19)
278 #define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20)
279 #define RADEON_SURF_FMASK (1 << 21)
280 #define RADEON_SURF_DISABLE_DCC (1 << 22)
281 #define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23)
282 #define RADEON_SURF_IMPORTED (1 << 24)
284 #define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
285 #define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
286 #define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
288 struct radeon_surf_level
{
297 uint32_t pitch_bytes
;
300 uint64_t dcc_fast_clear_size
;
305 /* These are inputs to the calculator. */
318 /* These are return values. Some of them can be set by the caller, but
319 * they will be treated as hints (e.g. bankw, bankh) and might be
320 * changed by the calculator.
323 uint64_t bo_alignment
;
324 /* This applies to EG and later. */
329 uint32_t stencil_tile_split
;
330 struct radeon_surf_level level
[RADEON_SURF_MAX_LEVEL
];
331 struct radeon_surf_level stencil_level
[RADEON_SURF_MAX_LEVEL
];
332 uint32_t tiling_index
[RADEON_SURF_MAX_LEVEL
];
333 uint32_t stencil_tiling_index
[RADEON_SURF_MAX_LEVEL
];
334 uint32_t pipe_config
;
336 uint32_t macro_tile_index
;
337 uint32_t micro_tile_mode
; /* displayable, thin, depth, rotated */
339 /* Whether the depth miptree or stencil miptree as used by the DB are
340 * adjusted from their TC compatible form to ensure depth/stencil
341 * compatibility. If either is true, the corresponding plane cannot be
345 bool stencil_adjusted
;
348 uint64_t dcc_alignment
;
349 /* TC-compatible HTILE only. */
351 uint64_t htile_alignment
;
354 struct radeon_bo_list_item
{
357 uint64_t priority_usage
; /* mask of (1 << RADEON_PRIO_*) */
360 struct radeon_winsys
{
362 * The screen object this winsys was created for
364 struct pipe_screen
*screen
;
367 * Decrement the winsys reference count.
369 * \param ws The winsys this function is called for.
370 * \return True if the winsys and screen should be destroyed.
372 bool (*unref
)(struct radeon_winsys
*ws
);
375 * Destroy this winsys.
377 * \param ws The winsys this function is called from.
379 void (*destroy
)(struct radeon_winsys
*ws
);
382 * Query an info structure from winsys.
384 * \param ws The winsys this function is called from.
385 * \param info Return structure
387 void (*query_info
)(struct radeon_winsys
*ws
,
388 struct radeon_info
*info
);
390 /**************************************************************************
391 * Buffer management. Buffer attributes are mostly fixed over its lifetime.
393 * Remember that gallium gets to choose the interface it needs, and the
394 * window systems must then implement that interface (rather than the
395 * other way around...).
396 *************************************************************************/
399 * Create a buffer object.
401 * \param ws The winsys this function is called from.
402 * \param size The size to allocate.
403 * \param alignment An alignment of the buffer in memory.
404 * \param use_reusable_pool Whether the cache buffer manager should be used.
405 * \param domain A bitmask of the RADEON_DOMAIN_* flags.
406 * \return The created buffer object.
408 struct pb_buffer
*(*buffer_create
)(struct radeon_winsys
*ws
,
411 enum radeon_bo_domain domain
,
412 enum radeon_bo_flag flags
);
415 * Map the entire data store of a buffer object into the client's address
418 * \param buf A winsys buffer object to map.
419 * \param cs A command stream to flush if the buffer is referenced by it.
420 * \param usage A bitmask of the PIPE_TRANSFER_* flags.
421 * \return The pointer at the beginning of the buffer.
423 void *(*buffer_map
)(struct pb_buffer
*buf
,
424 struct radeon_winsys_cs
*cs
,
425 enum pipe_transfer_usage usage
);
428 * Unmap a buffer object from the client's address space.
430 * \param buf A winsys buffer object to unmap.
432 void (*buffer_unmap
)(struct pb_buffer
*buf
);
435 * Wait for the buffer and return true if the buffer is not used
438 * The timeout of 0 will only return the status.
439 * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
442 bool (*buffer_wait
)(struct pb_buffer
*buf
, uint64_t timeout
,
443 enum radeon_bo_usage usage
);
446 * Return buffer metadata.
447 * (tiling info for display code, DRI sharing, and other data)
449 * \param buf A winsys buffer object to get the flags from.
452 void (*buffer_get_metadata
)(struct pb_buffer
*buf
,
453 struct radeon_bo_metadata
*md
);
456 * Set buffer metadata.
457 * (tiling info for display code, DRI sharing, and other data)
459 * \param buf A winsys buffer object to set the flags for.
462 void (*buffer_set_metadata
)(struct pb_buffer
*buf
,
463 struct radeon_bo_metadata
*md
);
466 * Get a winsys buffer from a winsys handle. The internal structure
467 * of the handle is platform-specific and only a winsys should access it.
469 * \param ws The winsys this function is called from.
470 * \param whandle A winsys handle pointer as was received from a state
472 * \param stride The returned buffer stride in bytes.
474 struct pb_buffer
*(*buffer_from_handle
)(struct radeon_winsys
*ws
,
475 struct winsys_handle
*whandle
,
476 unsigned *stride
, unsigned *offset
);
479 * Get a winsys buffer from a user pointer. The resulting buffer can't
480 * be exported. Both pointer and size must be page aligned.
482 * \param ws The winsys this function is called from.
483 * \param pointer User pointer to turn into a buffer object.
484 * \param Size Size in bytes for the new buffer.
486 struct pb_buffer
*(*buffer_from_ptr
)(struct radeon_winsys
*ws
,
487 void *pointer
, uint64_t size
);
490 * Whether the buffer was created from a user pointer.
492 * \param buf A winsys buffer object
493 * \return whether \p buf was created via buffer_from_ptr
495 bool (*buffer_is_user_ptr
)(struct pb_buffer
*buf
);
498 * Get a winsys handle from a winsys buffer. The internal structure
499 * of the handle is platform-specific and only a winsys should access it.
501 * \param buf A winsys buffer object to get the handle from.
502 * \param whandle A winsys handle pointer.
503 * \param stride A stride of the buffer in bytes, for texturing.
504 * \return true on success.
506 bool (*buffer_get_handle
)(struct pb_buffer
*buf
,
507 unsigned stride
, unsigned offset
,
509 struct winsys_handle
*whandle
);
512 * Return the virtual address of a buffer.
514 * When virtual memory is not in use, this is the offset relative to the
515 * relocation base (non-zero for sub-allocated buffers).
517 * \param buf A winsys buffer object
518 * \return virtual address
520 uint64_t (*buffer_get_virtual_address
)(struct pb_buffer
*buf
);
523 * Return the offset of this buffer relative to the relocation base.
524 * This is only non-zero for sub-allocated buffers.
526 * This is only supported in the radeon winsys, since amdgpu uses virtual
527 * addresses in submissions even for the video engines.
529 * \param buf A winsys buffer object
530 * \return the offset for relocations
532 unsigned (*buffer_get_reloc_offset
)(struct pb_buffer
*buf
);
535 * Query the initial placement of the buffer from the kernel driver.
537 enum radeon_bo_domain (*buffer_get_initial_domain
)(struct pb_buffer
*buf
);
539 /**************************************************************************
540 * Command submission.
542 * Each pipe context should create its own command stream and submit
543 * commands independently of other contexts.
544 *************************************************************************/
547 * Create a command submission context.
548 * Various command streams can be submitted to the same context.
550 struct radeon_winsys_ctx
*(*ctx_create
)(struct radeon_winsys
*ws
);
555 void (*ctx_destroy
)(struct radeon_winsys_ctx
*ctx
);
558 * Query a GPU reset status.
560 enum pipe_reset_status (*ctx_query_reset_status
)(struct radeon_winsys_ctx
*ctx
);
563 * Create a command stream.
565 * \param ctx The submission context
566 * \param ring_type The ring type (GFX, DMA, UVD)
567 * \param flush Flush callback function associated with the command stream.
568 * \param user User pointer that will be passed to the flush callback.
570 struct radeon_winsys_cs
*(*cs_create
)(struct radeon_winsys_ctx
*ctx
,
571 enum ring_type ring_type
,
572 void (*flush
)(void *ctx
, unsigned flags
,
573 struct pipe_fence_handle
**fence
),
577 * Add a constant engine IB to a graphics CS. This makes the graphics CS
578 * from "cs_create" a group of two IBs that share a buffer list and are
581 * The returned constant CS is only a stream for writing packets to the new
582 * IB. Calling other winsys functions with it is not allowed, not even
585 * In order to add buffers and check memory usage, use the graphics CS.
586 * In order to flush it, use the graphics CS, which will flush both IBs.
587 * Destroying the graphics CS will destroy both of them.
589 * \param cs The graphics CS from "cs_create" that will hold the buffer
590 * list and will be used for flushing.
592 struct radeon_winsys_cs
*(*cs_add_const_ib
)(struct radeon_winsys_cs
*cs
);
595 * Add a constant engine preamble IB to a graphics CS. This add an extra IB
596 * in similar manner to cs_add_const_ib. This should always be called after
599 * The returned IB is a constant engine IB that only gets flushed if the
602 * \param cs The graphics CS from "cs_create" that will hold the buffer
603 * list and will be used for flushing.
605 struct radeon_winsys_cs
*(*cs_add_const_preamble_ib
)(struct radeon_winsys_cs
*cs
);
607 * Destroy a command stream.
609 * \param cs A command stream to destroy.
611 void (*cs_destroy
)(struct radeon_winsys_cs
*cs
);
614 * Add a buffer. Each buffer used by a CS must be added using this function.
616 * \param cs Command stream
618 * \param usage Whether the buffer is used for read and/or write.
619 * \param domain Bitmask of the RADEON_DOMAIN_* flags.
620 * \param priority A higher number means a greater chance of being
621 * placed in the requested domain. 15 is the maximum.
622 * \return Buffer index.
624 unsigned (*cs_add_buffer
)(struct radeon_winsys_cs
*cs
,
625 struct pb_buffer
*buf
,
626 enum radeon_bo_usage usage
,
627 enum radeon_bo_domain domain
,
628 enum radeon_bo_priority priority
);
631 * Return the index of an already-added buffer.
633 * Not supported on amdgpu. Drivers with GPUVM should not care about
636 * \param cs Command stream
638 * \return The buffer index, or -1 if the buffer has not been added.
640 int (*cs_lookup_buffer
)(struct radeon_winsys_cs
*cs
,
641 struct pb_buffer
*buf
);
644 * Return true if there is enough memory in VRAM and GTT for the buffers
645 * added so far. If the validation fails, all buffers which have
646 * been added since the last call of cs_validate will be removed and
647 * the CS will be flushed (provided there are still any buffers).
649 * \param cs A command stream to validate.
651 bool (*cs_validate
)(struct radeon_winsys_cs
*cs
);
654 * Check whether the given number of dwords is available in the IB.
655 * Optionally chain a new chunk of the IB if necessary and supported.
657 * \param cs A command stream.
658 * \param dw Number of CS dwords requested by the caller.
660 bool (*cs_check_space
)(struct radeon_winsys_cs
*cs
, unsigned dw
);
663 * Return the buffer list.
665 * This is the buffer list as passed to the kernel, i.e. it only contains
666 * the parent buffers of sub-allocated buffers.
668 * \param cs Command stream
669 * \param list Returned buffer list. Set to NULL to query the count only.
670 * \return The buffer count.
672 unsigned (*cs_get_buffer_list
)(struct radeon_winsys_cs
*cs
,
673 struct radeon_bo_list_item
*list
);
676 * Flush a command stream.
678 * \param cs A command stream to flush.
679 * \param flags, RADEON_FLUSH_ASYNC or 0.
680 * \param fence Pointer to a fence. If non-NULL, a fence is inserted
681 * after the CS and is returned through this parameter.
682 * \return Negative POSIX error code or 0 for success.
683 * Asynchronous submissions never return an error.
685 int (*cs_flush
)(struct radeon_winsys_cs
*cs
,
687 struct pipe_fence_handle
**fence
);
690 * Create a fence before the CS is flushed.
691 * The user must flush manually to complete the initializaton of the fence.
692 * The fence must not be used before the flush.
694 struct pipe_fence_handle
*(*cs_get_next_fence
)(struct radeon_winsys_cs
*cs
);
697 * Return true if a buffer is referenced by a command stream.
699 * \param cs A command stream.
700 * \param buf A winsys buffer.
702 bool (*cs_is_buffer_referenced
)(struct radeon_winsys_cs
*cs
,
703 struct pb_buffer
*buf
,
704 enum radeon_bo_usage usage
);
707 * Request access to a feature for a command stream.
709 * \param cs A command stream.
710 * \param fid Feature ID, one of RADEON_FID_*
711 * \param enable Whether to enable or disable the feature.
713 bool (*cs_request_feature
)(struct radeon_winsys_cs
*cs
,
714 enum radeon_feature_id fid
,
717 * Make sure all asynchronous flush of the cs have completed
719 * \param cs A command stream.
721 void (*cs_sync_flush
)(struct radeon_winsys_cs
*cs
);
724 * Wait for the fence and return true if the fence has been signalled.
725 * The timeout of 0 will only return the status.
726 * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
729 bool (*fence_wait
)(struct radeon_winsys
*ws
,
730 struct pipe_fence_handle
*fence
,
734 * Reference counting for fences.
736 void (*fence_reference
)(struct pipe_fence_handle
**dst
,
737 struct pipe_fence_handle
*src
);
742 * \param ws The winsys this function is called from.
743 * \param surf Surface structure ptr
745 int (*surface_init
)(struct radeon_winsys
*ws
,
746 struct radeon_surf
*surf
);
748 uint64_t (*query_value
)(struct radeon_winsys
*ws
,
749 enum radeon_value_id value
);
751 bool (*read_registers
)(struct radeon_winsys
*ws
, unsigned reg_offset
,
752 unsigned num_registers
, uint32_t *out
);
755 static inline bool radeon_emitted(struct radeon_winsys_cs
*cs
, unsigned num_dw
)
757 return cs
&& (cs
->prev_dw
+ cs
->current
.cdw
> num_dw
);
760 static inline void radeon_emit(struct radeon_winsys_cs
*cs
, uint32_t value
)
762 cs
->current
.buf
[cs
->current
.cdw
++] = value
;
765 static inline void radeon_emit_array(struct radeon_winsys_cs
*cs
,
766 const uint32_t *values
, unsigned count
)
768 memcpy(cs
->current
.buf
+ cs
->current
.cdw
, values
, count
* 4);
769 cs
->current
.cdw
+= count
;