src/gallium/drivers/radeon/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #ifndef RADEON_WINSYS_H
  25 #define RADEON_WINSYS_H
  26
  27 /* The public winsys interface header for the radeon driver. */
  28
  29 #include "pipebuffer/pb_buffer.h"
  30
  31 #define RADEON_FLUSH_ASYNC              (1 << 0)
  32 #define RADEON_FLUSH_END_OF_FRAME       (1 << 1)
  33
  34 /* Tiling flags. */
  35 enum radeon_bo_layout {
  36     RADEON_LAYOUT_LINEAR = 0,
  37     RADEON_LAYOUT_TILED,
  38     RADEON_LAYOUT_SQUARETILED,
  39
  40     RADEON_LAYOUT_UNKNOWN
  41 };
  42
  43 enum radeon_bo_domain { /* bitfield */
  44     RADEON_DOMAIN_GTT  = 2,
  45     RADEON_DOMAIN_VRAM = 4,
  46     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  47 };
  48
  49 enum radeon_bo_flag { /* bitfield */
  50     RADEON_FLAG_GTT_WC =        (1 << 0),
  51     RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  52     RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  53 };
  54
  55 enum radeon_bo_usage { /* bitfield */
  56     RADEON_USAGE_READ = 2,
  57     RADEON_USAGE_WRITE = 4,
  58     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
  59 };
  60
  61 enum radeon_family {
  62     CHIP_UNKNOWN = 0,
  63     CHIP_R300, /* R3xx-based cores. */
  64     CHIP_R350,
  65     CHIP_RV350,
  66     CHIP_RV370,
  67     CHIP_RV380,
  68     CHIP_RS400,
  69     CHIP_RC410,
  70     CHIP_RS480,
  71     CHIP_R420,     /* R4xx-based cores. */
  72     CHIP_R423,
  73     CHIP_R430,
  74     CHIP_R480,
  75     CHIP_R481,
  76     CHIP_RV410,
  77     CHIP_RS600,
  78     CHIP_RS690,
  79     CHIP_RS740,
  80     CHIP_RV515,    /* R5xx-based cores. */
  81     CHIP_R520,
  82     CHIP_RV530,
  83     CHIP_R580,
  84     CHIP_RV560,
  85     CHIP_RV570,
  86     CHIP_R600,
  87     CHIP_RV610,
  88     CHIP_RV630,
  89     CHIP_RV670,
  90     CHIP_RV620,
  91     CHIP_RV635,
  92     CHIP_RS780,
  93     CHIP_RS880,
  94     CHIP_RV770,
  95     CHIP_RV730,
  96     CHIP_RV710,
  97     CHIP_RV740,
  98     CHIP_CEDAR,
  99     CHIP_REDWOOD,
 100     CHIP_JUNIPER,
 101     CHIP_CYPRESS,
 102     CHIP_HEMLOCK,
 103     CHIP_PALM,
 104     CHIP_SUMO,
 105     CHIP_SUMO2,
 106     CHIP_BARTS,
 107     CHIP_TURKS,
 108     CHIP_CAICOS,
 109     CHIP_CAYMAN,
 110     CHIP_ARUBA,
 111     CHIP_TAHITI,
 112     CHIP_PITCAIRN,
 113     CHIP_VERDE,
 114     CHIP_OLAND,
 115     CHIP_HAINAN,
 116     CHIP_BONAIRE,
 117     CHIP_KAVERI,
 118     CHIP_KABINI,
 119     CHIP_HAWAII,
 120     CHIP_MULLINS,
 121     CHIP_TONGA,
 122     CHIP_ICELAND,
 123     CHIP_CARRIZO,
 124     CHIP_FIJI,
 125     CHIP_STONEY,
 126     CHIP_POLARIS10,
 127     CHIP_POLARIS11,
 128     CHIP_LAST,
 129 };
 130
 131 enum chip_class {
 132     CLASS_UNKNOWN = 0,
 133     R300,
 134     R400,
 135     R500,
 136     R600,
 137     R700,
 138     EVERGREEN,
 139     CAYMAN,
 140     SI,
 141     CIK,
 142     VI,
 143 };
 144
 145 enum ring_type {
 146     RING_GFX = 0,
 147     RING_COMPUTE,
 148     RING_DMA,
 149     RING_UVD,
 150     RING_VCE,
 151     RING_LAST,
 152 };
 153
 154 enum radeon_value_id {
 155     RADEON_REQUESTED_VRAM_MEMORY,
 156     RADEON_REQUESTED_GTT_MEMORY,
 157     RADEON_MAPPED_VRAM,
 158     RADEON_MAPPED_GTT,
 159     RADEON_BUFFER_WAIT_TIME_NS,
 160     RADEON_TIMESTAMP,
 161     RADEON_NUM_CS_FLUSHES,
 162     RADEON_NUM_BYTES_MOVED,
 163     RADEON_VRAM_USAGE,
 164     RADEON_GTT_USAGE,
 165     RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
 166     RADEON_CURRENT_SCLK,
 167     RADEON_CURRENT_MCLK,
 168     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
 169 };
 170
 171 /* Each group of four has the same priority. */
 172 enum radeon_bo_priority {
 173     RADEON_PRIO_FENCE = 0,
 174     RADEON_PRIO_TRACE,
 175     RADEON_PRIO_SO_FILLED_SIZE,
 176     RADEON_PRIO_QUERY,
 177
 178     RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
 179     RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
 180     RADEON_PRIO_DRAW_INDIRECT,
 181     RADEON_PRIO_INDEX_BUFFER,
 182
 183     RADEON_PRIO_VCE = 8,
 184     RADEON_PRIO_UVD,
 185     RADEON_PRIO_SDMA_BUFFER,
 186     RADEON_PRIO_SDMA_TEXTURE,
 187
 188     RADEON_PRIO_CP_DMA = 12,
 189     RADEON_PRIO_USER_SHADER,
 190     RADEON_PRIO_INTERNAL_SHADER, /* fetch shader, etc. */
 191
 192     RADEON_PRIO_CONST_BUFFER = 16,
 193     RADEON_PRIO_DESCRIPTORS,
 194     RADEON_PRIO_BORDER_COLORS,
 195
 196     RADEON_PRIO_SAMPLER_BUFFER = 20,
 197     RADEON_PRIO_VERTEX_BUFFER,
 198
 199     RADEON_PRIO_SHADER_RW_BUFFER = 24,
 200     RADEON_PRIO_SCRATCH_BUFFER,
 201     RADEON_PRIO_COMPUTE_GLOBAL,
 202
 203     RADEON_PRIO_SAMPLER_TEXTURE = 28,
 204     RADEON_PRIO_SHADER_RW_IMAGE,
 205
 206     RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 32,
 207
 208     RADEON_PRIO_COLOR_BUFFER = 36,
 209
 210     RADEON_PRIO_DEPTH_BUFFER = 40,
 211
 212     RADEON_PRIO_COLOR_BUFFER_MSAA = 44,
 213
 214     RADEON_PRIO_DEPTH_BUFFER_MSAA = 48,
 215
 216     RADEON_PRIO_CMASK = 52,
 217     RADEON_PRIO_DCC,
 218     RADEON_PRIO_HTILE,
 219     RADEON_PRIO_SHADER_RINGS,
 220     /* 63 is the maximum value */
 221 };
 222
 223 struct winsys_handle;
 224 struct radeon_winsys_ctx;
 225
 226 struct radeon_winsys_cs_chunk {
 227     unsigned cdw;  /* Number of used dwords. */
 228     unsigned max_dw; /* Maximum number of dwords. */
 229     uint32_t *buf; /* The base pointer of the chunk. */
 230 };
 231
 232 struct radeon_winsys_cs {
 233     struct radeon_winsys_cs_chunk current;
 234     struct radeon_winsys_cs_chunk *prev;
 235     unsigned                      num_prev; /* Number of previous chunks. */
 236     unsigned                      max_prev; /* Space in array pointed to by prev. */
 237     unsigned                      prev_dw; /* Total number of dwords in previous chunks. */
 238
 239     /* Memory usage of the buffer list. These are always 0 for CE and preamble
 240      * IBs. */
 241     uint64_t                      used_vram;
 242     uint64_t                      used_gart;
 243 };
 244
 245 struct radeon_info {
 246     /* PCI info: domain:bus:dev:func */
 247     uint32_t                    pci_domain;
 248     uint32_t                    pci_bus;
 249     uint32_t                    pci_dev;
 250     uint32_t                    pci_func;
 251
 252     /* Device info. */
 253     uint32_t                    pci_id;
 254     enum radeon_family          family;
 255     enum chip_class             chip_class;
 256     uint32_t                    gart_page_size;
 257     uint64_t                    gart_size;
 258     uint64_t                    vram_size;
 259     uint64_t                    max_alloc_size;
 260     bool                        has_dedicated_vram;
 261     bool                        has_virtual_memory;
 262     bool                        gfx_ib_pad_with_type2;
 263     bool                        has_sdma;
 264     bool                        has_uvd;
 265     uint32_t                    uvd_fw_version;
 266     uint32_t                    vce_fw_version;
 267     uint32_t                    me_fw_version;
 268     uint32_t                    pfp_fw_version;
 269     uint32_t                    ce_fw_version;
 270     uint32_t                    vce_harvest_config;
 271     uint32_t                    clock_crystal_freq;
 272
 273     /* Kernel info. */
 274     uint32_t                    drm_major; /* version */
 275     uint32_t                    drm_minor;
 276     uint32_t                    drm_patchlevel;
 277     bool                        has_userptr;
 278
 279     /* Shader cores. */
 280     uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
 281     uint32_t                    max_shader_clock;
 282     uint32_t                    num_good_compute_units;
 283     uint32_t                    max_se; /* shader engines */
 284     uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 285
 286     /* Render backends (color + depth blocks). */
 287     uint32_t                    r300_num_gb_pipes;
 288     uint32_t                    r300_num_z_pipes;
 289     uint32_t                    r600_gb_backend_map; /* R600 harvest config */
 290     bool                        r600_gb_backend_map_valid;
 291     uint32_t                    r600_num_banks;
 292     uint32_t                    num_render_backends;
 293     uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
 294     uint32_t                    pipe_interleave_bytes;
 295     uint32_t                    enabled_rb_mask; /* GCN harvest config */
 296
 297     /* Tile modes. */
 298     uint32_t                    si_tile_mode_array[32];
 299     uint32_t                    cik_macrotile_mode_array[16];
 300 };
 301
 302 /* Tiling info for display code, DRI sharing, and other data. */
 303 struct radeon_bo_metadata {
 304     /* Tiling flags describing the texture layout for display code
 305      * and DRI sharing.
 306      */
 307     enum radeon_bo_layout   microtile;
 308     enum radeon_bo_layout   macrotile;
 309     unsigned                pipe_config;
 310     unsigned                bankw;
 311     unsigned                bankh;
 312     unsigned                tile_split;
 313     unsigned                mtilea;
 314     unsigned                num_banks;
 315     unsigned                stride;
 316     bool                    scanout;
 317
 318     /* Additional metadata associated with the buffer, in bytes.
 319      * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 320      * Supported by amdgpu only.
 321      */
 322     uint32_t                size_metadata;
 323     uint32_t                metadata[64];
 324 };
 325
 326 enum radeon_feature_id {
 327     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 328     RADEON_FID_R300_CMASK_ACCESS,
 329 };
 330
 331 #define RADEON_SURF_MAX_LEVEL                   32
 332
 333 #define RADEON_SURF_TYPE_MASK                   0xFF
 334 #define RADEON_SURF_TYPE_SHIFT                  0
 335 #define     RADEON_SURF_TYPE_1D                     0
 336 #define     RADEON_SURF_TYPE_2D                     1
 337 #define     RADEON_SURF_TYPE_3D                     2
 338 #define     RADEON_SURF_TYPE_CUBEMAP                3
 339 #define     RADEON_SURF_TYPE_1D_ARRAY               4
 340 #define     RADEON_SURF_TYPE_2D_ARRAY               5
 341 #define RADEON_SURF_MODE_MASK                   0xFF
 342 #define RADEON_SURF_MODE_SHIFT                  8
 343 #define     RADEON_SURF_MODE_LINEAR_ALIGNED         1
 344 #define     RADEON_SURF_MODE_1D                     2
 345 #define     RADEON_SURF_MODE_2D                     3
 346 #define RADEON_SURF_SCANOUT                     (1 << 16)
 347 #define RADEON_SURF_ZBUFFER                     (1 << 17)
 348 #define RADEON_SURF_SBUFFER                     (1 << 18)
 349 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
 350 #define RADEON_SURF_HAS_SBUFFER_MIPTREE         (1 << 19)
 351 #define RADEON_SURF_HAS_TILE_MODE_INDEX         (1 << 20)
 352 #define RADEON_SURF_FMASK                       (1 << 21)
 353 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
 354
 355 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
 356 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
 357 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
 358
 359 struct radeon_surf_level {
 360     uint64_t                    offset;
 361     uint64_t                    slice_size;
 362     uint32_t                    npix_x;
 363     uint32_t                    npix_y;
 364     uint32_t                    npix_z;
 365     uint32_t                    nblk_x;
 366     uint32_t                    nblk_y;
 367     uint32_t                    nblk_z;
 368     uint32_t                    pitch_bytes;
 369     uint32_t                    mode;
 370     uint64_t                    dcc_offset;
 371     uint64_t                    dcc_fast_clear_size;
 372     bool                        dcc_enabled;
 373 };
 374
 375 struct radeon_surf {
 376     /* These are inputs to the calculator. */
 377     uint32_t                    npix_x;
 378     uint32_t                    npix_y;
 379     uint32_t                    npix_z;
 380     uint32_t                    blk_w;
 381     uint32_t                    blk_h;
 382     uint32_t                    blk_d;
 383     uint32_t                    array_size;
 384     uint32_t                    last_level;
 385     uint32_t                    bpe;
 386     uint32_t                    nsamples;
 387     uint32_t                    flags;
 388
 389     /* These are return values. Some of them can be set by the caller, but
 390      * they will be treated as hints (e.g. bankw, bankh) and might be
 391      * changed by the calculator.
 392      */
 393     uint64_t                    bo_size;
 394     uint64_t                    bo_alignment;
 395     /* This applies to EG and later. */
 396     uint32_t                    bankw;
 397     uint32_t                    bankh;
 398     uint32_t                    mtilea;
 399     uint32_t                    tile_split;
 400     uint32_t                    stencil_tile_split;
 401     struct radeon_surf_level    level[RADEON_SURF_MAX_LEVEL];
 402     struct radeon_surf_level    stencil_level[RADEON_SURF_MAX_LEVEL];
 403     uint32_t                    tiling_index[RADEON_SURF_MAX_LEVEL];
 404     uint32_t                    stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
 405     uint32_t                    pipe_config;
 406     uint32_t                    num_banks;
 407     uint32_t                    macro_tile_index;
 408     uint32_t                    micro_tile_mode; /* displayable, thin, depth, rotated */
 409
 410     /* Whether the depth miptree or stencil miptree as used by the DB are
 411      * adjusted from their TC compatible form to ensure depth/stencil
 412      * compatibility. If either is true, the corresponding plane cannot be
 413      * sampled from.
 414      */
 415     bool                        depth_adjusted;
 416     bool                        stencil_adjusted;
 417
 418     uint64_t                    dcc_size;
 419     uint64_t                    dcc_alignment;
 420 };
 421
 422 struct radeon_bo_list_item {
 423     uint64_t bo_size;
 424     uint64_t vm_address;
 425     uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
 426 };
 427
 428 struct radeon_winsys {
 429     /**
 430      * The screen object this winsys was created for
 431      */
 432     struct pipe_screen *screen;
 433
 434     /**
 435      * Decrement the winsys reference count.
 436      *
 437      * \param ws  The winsys this function is called for.
 438      * \return    True if the winsys and screen should be destroyed.
 439      */
 440     bool (*unref)(struct radeon_winsys *ws);
 441
 442     /**
 443      * Destroy this winsys.
 444      *
 445      * \param ws        The winsys this function is called from.
 446      */
 447     void (*destroy)(struct radeon_winsys *ws);
 448
 449     /**
 450      * Query an info structure from winsys.
 451      *
 452      * \param ws        The winsys this function is called from.
 453      * \param info      Return structure
 454      */
 455     void (*query_info)(struct radeon_winsys *ws,
 456                        struct radeon_info *info);
 457
 458     /**************************************************************************
 459      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 460      *
 461      * Remember that gallium gets to choose the interface it needs, and the
 462      * window systems must then implement that interface (rather than the
 463      * other way around...).
 464      *************************************************************************/
 465
 466     /**
 467      * Create a buffer object.
 468      *
 469      * \param ws        The winsys this function is called from.
 470      * \param size      The size to allocate.
 471      * \param alignment An alignment of the buffer in memory.
 472      * \param use_reusable_pool Whether the cache buffer manager should be used.
 473      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 474      * \return          The created buffer object.
 475      */
 476     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 477                                        uint64_t size,
 478                                        unsigned alignment,
 479                                        enum radeon_bo_domain domain,
 480                                        enum radeon_bo_flag flags);
 481
 482     /**
 483      * Map the entire data store of a buffer object into the client's address
 484      * space.
 485      *
 486      * \param buf       A winsys buffer object to map.
 487      * \param cs        A command stream to flush if the buffer is referenced by it.
 488      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 489      * \return          The pointer at the beginning of the buffer.
 490      */
 491     void *(*buffer_map)(struct pb_buffer *buf,
 492                         struct radeon_winsys_cs *cs,
 493                         enum pipe_transfer_usage usage);
 494
 495     /**
 496      * Unmap a buffer object from the client's address space.
 497      *
 498      * \param buf       A winsys buffer object to unmap.
 499      */
 500     void (*buffer_unmap)(struct pb_buffer *buf);
 501
 502     /**
 503      * Wait for the buffer and return true if the buffer is not used
 504      * by the device.
 505      *
 506      * The timeout of 0 will only return the status.
 507      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
 508      * is idle.
 509      */
 510     bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
 511                         enum radeon_bo_usage usage);
 512
 513     /**
 514      * Return buffer metadata.
 515      * (tiling info for display code, DRI sharing, and other data)
 516      *
 517      * \param buf       A winsys buffer object to get the flags from.
 518      * \param md        Metadata
 519      */
 520     void (*buffer_get_metadata)(struct pb_buffer *buf,
 521                                 struct radeon_bo_metadata *md);
 522
 523     /**
 524      * Set buffer metadata.
 525      * (tiling info for display code, DRI sharing, and other data)
 526      *
 527      * \param buf       A winsys buffer object to set the flags for.
 528      * \param md        Metadata
 529      */
 530     void (*buffer_set_metadata)(struct pb_buffer *buf,
 531                                 struct radeon_bo_metadata *md);
 532
 533     /**
 534      * Get a winsys buffer from a winsys handle. The internal structure
 535      * of the handle is platform-specific and only a winsys should access it.
 536      *
 537      * \param ws        The winsys this function is called from.
 538      * \param whandle   A winsys handle pointer as was received from a state
 539      *                  tracker.
 540      * \param stride    The returned buffer stride in bytes.
 541      */
 542     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 543                                             struct winsys_handle *whandle,
 544                                             unsigned *stride, unsigned *offset);
 545
 546     /**
 547      * Get a winsys buffer from a user pointer. The resulting buffer can't
 548      * be exported. Both pointer and size must be page aligned.
 549      *
 550      * \param ws        The winsys this function is called from.
 551      * \param pointer   User pointer to turn into a buffer object.
 552      * \param Size      Size in bytes for the new buffer.
 553      */
 554     struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
 555                                          void *pointer, uint64_t size);
 556
 557     /**
 558      * Whether the buffer was created from a user pointer.
 559      *
 560      * \param buf       A winsys buffer object
 561      * \return          whether \p buf was created via buffer_from_ptr
 562      */
 563     bool (*buffer_is_user_ptr)(struct pb_buffer *buf);
 564
 565     /**
 566      * Get a winsys handle from a winsys buffer. The internal structure
 567      * of the handle is platform-specific and only a winsys should access it.
 568      *
 569      * \param buf       A winsys buffer object to get the handle from.
 570      * \param whandle   A winsys handle pointer.
 571      * \param stride    A stride of the buffer in bytes, for texturing.
 572      * \return          true on success.
 573      */
 574     bool (*buffer_get_handle)(struct pb_buffer *buf,
 575                               unsigned stride, unsigned offset,
 576                               unsigned slice_size,
 577                               struct winsys_handle *whandle);
 578
 579     /**
 580      * Return the virtual address of a buffer.
 581      *
 582      * \param buf       A winsys buffer object
 583      * \return          virtual address
 584      */
 585     uint64_t (*buffer_get_virtual_address)(struct pb_buffer *buf);
 586
 587     /**
 588      * Query the initial placement of the buffer from the kernel driver.
 589      */
 590     enum radeon_bo_domain (*buffer_get_initial_domain)(struct pb_buffer *buf);
 591
 592     /**************************************************************************
 593      * Command submission.
 594      *
 595      * Each pipe context should create its own command stream and submit
 596      * commands independently of other contexts.
 597      *************************************************************************/
 598
 599     /**
 600      * Create a command submission context.
 601      * Various command streams can be submitted to the same context.
 602      */
 603     struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 604
 605     /**
 606      * Destroy a context.
 607      */
 608     void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 609
 610     /**
 611      * Query a GPU reset status.
 612      */
 613     enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
 614
 615     /**
 616      * Create a command stream.
 617      *
 618      * \param ctx       The submission context
 619      * \param ring_type The ring type (GFX, DMA, UVD)
 620      * \param flush     Flush callback function associated with the command stream.
 621      * \param user      User pointer that will be passed to the flush callback.
 622      */
 623     struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys_ctx *ctx,
 624                                           enum ring_type ring_type,
 625                                           void (*flush)(void *ctx, unsigned flags,
 626                                                         struct pipe_fence_handle **fence),
 627                                           void *flush_ctx);
 628
 629     /**
 630      * Add a constant engine IB to a graphics CS. This makes the graphics CS
 631      * from "cs_create" a group of two IBs that share a buffer list and are
 632      * flushed together.
 633      *
 634      * The returned constant CS is only a stream for writing packets to the new
 635      * IB. Calling other winsys functions with it is not allowed, not even
 636      * "cs_destroy".
 637      *
 638      * In order to add buffers and check memory usage, use the graphics CS.
 639      * In order to flush it, use the graphics CS, which will flush both IBs.
 640      * Destroying the graphics CS will destroy both of them.
 641      *
 642      * \param cs  The graphics CS from "cs_create" that will hold the buffer
 643      *            list and will be used for flushing.
 644      */
 645     struct radeon_winsys_cs *(*cs_add_const_ib)(struct radeon_winsys_cs *cs);
 646
 647      /**
 648      * Add a constant engine preamble IB to a graphics CS. This add an extra IB
 649      * in similar manner to cs_add_const_ib. This should always be called after
 650      * cs_add_const_ib.
 651      *
 652      * The returned IB is a constant engine IB that only gets flushed if the
 653      * context changed.
 654      *
 655      * \param cs  The graphics CS from "cs_create" that will hold the buffer
 656      *            list and will be used for flushing.
 657      */
 658     struct radeon_winsys_cs *(*cs_add_const_preamble_ib)(struct radeon_winsys_cs *cs);
 659     /**
 660      * Destroy a command stream.
 661      *
 662      * \param cs        A command stream to destroy.
 663      */
 664     void (*cs_destroy)(struct radeon_winsys_cs *cs);
 665
 666     /**
 667      * Add a buffer. Each buffer used by a CS must be added using this function.
 668      *
 669      * \param cs      Command stream
 670      * \param buf     Buffer
 671      * \param usage   Whether the buffer is used for read and/or write.
 672      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 673      * \param priority  A higher number means a greater chance of being
 674      *                  placed in the requested domain. 15 is the maximum.
 675      * \return Buffer index.
 676      */
 677     unsigned (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 678                              struct pb_buffer *buf,
 679                              enum radeon_bo_usage usage,
 680                              enum radeon_bo_domain domain,
 681                              enum radeon_bo_priority priority);
 682
 683     /**
 684      * Return the index of an already-added buffer.
 685      *
 686      * \param cs        Command stream
 687      * \param buf       Buffer
 688      * \return          The buffer index, or -1 if the buffer has not been added.
 689      */
 690     int (*cs_lookup_buffer)(struct radeon_winsys_cs *cs,
 691                             struct pb_buffer *buf);
 692
 693     /**
 694      * Return true if there is enough memory in VRAM and GTT for the buffers
 695      * added so far. If the validation fails, all buffers which have
 696      * been added since the last call of cs_validate will be removed and
 697      * the CS will be flushed (provided there are still any buffers).
 698      *
 699      * \param cs        A command stream to validate.
 700      */
 701     bool (*cs_validate)(struct radeon_winsys_cs *cs);
 702
 703     /**
 704      * Check whether the given number of dwords is available in the IB.
 705      * Optionally chain a new chunk of the IB if necessary and supported.
 706      *
 707      * \param cs        A command stream.
 708      * \param dw        Number of CS dwords requested by the caller.
 709      */
 710     bool (*cs_check_space)(struct radeon_winsys_cs *cs, unsigned dw);
 711
 712     /**
 713      * Return the buffer list.
 714      *
 715      * \param cs    Command stream
 716      * \param list  Returned buffer list. Set to NULL to query the count only.
 717      * \return      The buffer count.
 718      */
 719     unsigned (*cs_get_buffer_list)(struct radeon_winsys_cs *cs,
 720                                    struct radeon_bo_list_item *list);
 721
 722     /**
 723      * Flush a command stream.
 724      *
 725      * \param cs          A command stream to flush.
 726      * \param flags,      RADEON_FLUSH_ASYNC or 0.
 727      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 728      *                    after the CS and is returned through this parameter.
 729      * \return Negative POSIX error code or 0 for success.
 730      *         Asynchronous submissions never return an error.
 731      */
 732     int (*cs_flush)(struct radeon_winsys_cs *cs,
 733                     unsigned flags,
 734                     struct pipe_fence_handle **fence);
 735
 736     /**
 737      * Create a fence before the CS is flushed.
 738      * The user must flush manually to complete the initializaton of the fence.
 739      * The fence must not be used before the flush.
 740      */
 741     struct pipe_fence_handle *(*cs_get_next_fence)(struct radeon_winsys_cs *cs);
 742
 743     /**
 744      * Return true if a buffer is referenced by a command stream.
 745      *
 746      * \param cs        A command stream.
 747      * \param buf       A winsys buffer.
 748      */
 749     bool (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
 750                                     struct pb_buffer *buf,
 751                                     enum radeon_bo_usage usage);
 752
 753     /**
 754      * Request access to a feature for a command stream.
 755      *
 756      * \param cs        A command stream.
 757      * \param fid       Feature ID, one of RADEON_FID_*
 758      * \param enable    Whether to enable or disable the feature.
 759      */
 760     bool (*cs_request_feature)(struct radeon_winsys_cs *cs,
 761                                enum radeon_feature_id fid,
 762                                bool enable);
 763      /**
 764       * Make sure all asynchronous flush of the cs have completed
 765       *
 766       * \param cs        A command stream.
 767       */
 768     void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
 769
 770     /**
 771      * Wait for the fence and return true if the fence has been signalled.
 772      * The timeout of 0 will only return the status.
 773      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 774      * is signalled.
 775      */
 776     bool (*fence_wait)(struct radeon_winsys *ws,
 777                        struct pipe_fence_handle *fence,
 778                        uint64_t timeout);
 779
 780     /**
 781      * Reference counting for fences.
 782      */
 783     void (*fence_reference)(struct pipe_fence_handle **dst,
 784                             struct pipe_fence_handle *src);
 785
 786     /**
 787      * Initialize surface
 788      *
 789      * \param ws        The winsys this function is called from.
 790      * \param surf      Surface structure ptr
 791      */
 792     int (*surface_init)(struct radeon_winsys *ws,
 793                         struct radeon_surf *surf);
 794
 795     /**
 796      * Find best values for a surface
 797      *
 798      * \param ws        The winsys this function is called from.
 799      * \param surf      Surface structure ptr
 800      */
 801     int (*surface_best)(struct radeon_winsys *ws,
 802                         struct radeon_surf *surf);
 803
 804     uint64_t (*query_value)(struct radeon_winsys *ws,
 805                             enum radeon_value_id value);
 806
 807     bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 808                            unsigned num_registers, uint32_t *out);
 809 };
 810
 811 static inline bool radeon_emitted(struct radeon_winsys_cs *cs, unsigned num_dw)
 812 {
 813     return cs && (cs->prev_dw + cs->current.cdw > num_dw);
 814 }
 815
 816 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 817 {
 818     cs->current.buf[cs->current.cdw++] = value;
 819 }
 820
 821 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 822                                      const uint32_t *values, unsigned count)
 823 {
 824     memcpy(cs->current.buf + cs->current.cdw, values, count * 4);
 825     cs->current.cdw += count;
 826 }
 827
 828 #endif