src/gallium/drivers/radeon/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #ifndef RADEON_WINSYS_H
  25 #define RADEON_WINSYS_H
  26
  27 /* The public winsys interface header for the radeon driver. */
  28
  29 #include "pipebuffer/pb_buffer.h"
  30
  31 #include "amd/common/amd_family.h"
  32
  33 #define RADEON_FLUSH_ASYNC              (1 << 0)
  34 #define RADEON_FLUSH_END_OF_FRAME       (1 << 1)
  35
  36 /* Tiling flags. */
  37 enum radeon_bo_layout {
  38     RADEON_LAYOUT_LINEAR = 0,
  39     RADEON_LAYOUT_TILED,
  40     RADEON_LAYOUT_SQUARETILED,
  41
  42     RADEON_LAYOUT_UNKNOWN
  43 };
  44
  45 enum radeon_bo_domain { /* bitfield */
  46     RADEON_DOMAIN_GTT  = 2,
  47     RADEON_DOMAIN_VRAM = 4,
  48     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  49 };
  50
  51 enum radeon_bo_flag { /* bitfield */
  52     RADEON_FLAG_GTT_WC =        (1 << 0),
  53     RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  54     RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  55     RADEON_FLAG_HANDLE =        (1 << 3), /* the buffer most not be suballocated */
  56 };
  57
  58 enum radeon_bo_usage { /* bitfield */
  59     RADEON_USAGE_READ = 2,
  60     RADEON_USAGE_WRITE = 4,
  61     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE,
  62
  63     /* The winsys ensures that the CS submission will be scheduled after
  64      * previously flushed CSs referencing this BO in a conflicting way.
  65      */
  66     RADEON_USAGE_SYNCHRONIZED = 8
  67 };
  68
  69 enum ring_type {
  70     RING_GFX = 0,
  71     RING_COMPUTE,
  72     RING_DMA,
  73     RING_UVD,
  74     RING_VCE,
  75     RING_LAST,
  76 };
  77
  78 enum radeon_value_id {
  79     RADEON_REQUESTED_VRAM_MEMORY,
  80     RADEON_REQUESTED_GTT_MEMORY,
  81     RADEON_MAPPED_VRAM,
  82     RADEON_MAPPED_GTT,
  83     RADEON_BUFFER_WAIT_TIME_NS,
  84     RADEON_NUM_MAPPED_BUFFERS,
  85     RADEON_TIMESTAMP,
  86     RADEON_NUM_GFX_IBS,
  87     RADEON_NUM_SDMA_IBS,
  88     RADEON_NUM_BYTES_MOVED,
  89     RADEON_NUM_EVICTIONS,
  90     RADEON_VRAM_USAGE,
  91     RADEON_VRAM_VIS_USAGE,
  92     RADEON_GTT_USAGE,
  93     RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
  94     RADEON_CURRENT_SCLK,
  95     RADEON_CURRENT_MCLK,
  96     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
  97     RADEON_CS_THREAD_TIME,
  98 };
  99
 100 /* Each group of four has the same priority. */
 101 enum radeon_bo_priority {
 102     RADEON_PRIO_FENCE = 0,
 103     RADEON_PRIO_TRACE,
 104     RADEON_PRIO_SO_FILLED_SIZE,
 105     RADEON_PRIO_QUERY,
 106
 107     RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
 108     RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
 109     RADEON_PRIO_DRAW_INDIRECT,
 110     RADEON_PRIO_INDEX_BUFFER,
 111
 112     RADEON_PRIO_VCE = 8,
 113     RADEON_PRIO_UVD,
 114     RADEON_PRIO_SDMA_BUFFER,
 115     RADEON_PRIO_SDMA_TEXTURE,
 116
 117     RADEON_PRIO_CP_DMA = 12,
 118
 119     RADEON_PRIO_CONST_BUFFER = 16,
 120     RADEON_PRIO_DESCRIPTORS,
 121     RADEON_PRIO_BORDER_COLORS,
 122
 123     RADEON_PRIO_SAMPLER_BUFFER = 20,
 124     RADEON_PRIO_VERTEX_BUFFER,
 125
 126     RADEON_PRIO_SHADER_RW_BUFFER = 24,
 127     RADEON_PRIO_COMPUTE_GLOBAL,
 128
 129     RADEON_PRIO_SAMPLER_TEXTURE = 28,
 130     RADEON_PRIO_SHADER_RW_IMAGE,
 131
 132     RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 32,
 133
 134     RADEON_PRIO_COLOR_BUFFER = 36,
 135
 136     RADEON_PRIO_DEPTH_BUFFER = 40,
 137
 138     RADEON_PRIO_COLOR_BUFFER_MSAA = 44,
 139
 140     RADEON_PRIO_DEPTH_BUFFER_MSAA = 48,
 141
 142     RADEON_PRIO_CMASK = 52,
 143     RADEON_PRIO_DCC,
 144     RADEON_PRIO_HTILE,
 145     RADEON_PRIO_SHADER_BINARY, /* the hw can't hide instruction cache misses */
 146
 147     RADEON_PRIO_SHADER_RINGS = 56,
 148
 149     RADEON_PRIO_SCRATCH_BUFFER = 60,
 150     /* 63 is the maximum value */
 151 };
 152
 153 struct winsys_handle;
 154 struct radeon_winsys_ctx;
 155
 156 struct radeon_winsys_cs_chunk {
 157     unsigned cdw;  /* Number of used dwords. */
 158     unsigned max_dw; /* Maximum number of dwords. */
 159     uint32_t *buf; /* The base pointer of the chunk. */
 160 };
 161
 162 struct radeon_winsys_cs {
 163     struct radeon_winsys_cs_chunk current;
 164     struct radeon_winsys_cs_chunk *prev;
 165     unsigned                      num_prev; /* Number of previous chunks. */
 166     unsigned                      max_prev; /* Space in array pointed to by prev. */
 167     unsigned                      prev_dw; /* Total number of dwords in previous chunks. */
 168
 169     /* Memory usage of the buffer list. These are always 0 for CE and preamble
 170      * IBs. */
 171     uint64_t                      used_vram;
 172     uint64_t                      used_gart;
 173 };
 174
 175 struct radeon_info {
 176     /* PCI info: domain:bus:dev:func */
 177     uint32_t                    pci_domain;
 178     uint32_t                    pci_bus;
 179     uint32_t                    pci_dev;
 180     uint32_t                    pci_func;
 181
 182     /* Device info. */
 183     uint32_t                    pci_id;
 184     enum radeon_family          family;
 185     enum chip_class             chip_class;
 186     uint32_t                    gart_page_size;
 187     uint64_t                    gart_size;
 188     uint64_t                    vram_size;
 189     uint64_t                    vram_vis_size;
 190     uint64_t                    max_alloc_size;
 191     uint32_t                    min_alloc_size;
 192     bool                        has_dedicated_vram;
 193     bool                        has_virtual_memory;
 194     bool                        gfx_ib_pad_with_type2;
 195     bool                        has_sdma;
 196     bool                        has_uvd;
 197     uint32_t                    uvd_fw_version;
 198     uint32_t                    vce_fw_version;
 199     uint32_t                    me_fw_version;
 200     uint32_t                    pfp_fw_version;
 201     uint32_t                    ce_fw_version;
 202     uint32_t                    vce_harvest_config;
 203     uint32_t                    clock_crystal_freq;
 204     uint32_t                    tcc_cache_line_size;
 205
 206     /* Kernel info. */
 207     uint32_t                    drm_major; /* version */
 208     uint32_t                    drm_minor;
 209     uint32_t                    drm_patchlevel;
 210     bool                        has_userptr;
 211
 212     /* Shader cores. */
 213     uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
 214     uint32_t                    max_shader_clock;
 215     uint32_t                    num_good_compute_units;
 216     uint32_t                    max_se; /* shader engines */
 217     uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 218
 219     /* Render backends (color + depth blocks). */
 220     uint32_t                    r300_num_gb_pipes;
 221     uint32_t                    r300_num_z_pipes;
 222     uint32_t                    r600_gb_backend_map; /* R600 harvest config */
 223     bool                        r600_gb_backend_map_valid;
 224     uint32_t                    r600_num_banks;
 225     uint32_t                    num_render_backends;
 226     uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
 227     uint32_t                    pipe_interleave_bytes;
 228     uint32_t                    enabled_rb_mask; /* GCN harvest config */
 229
 230     /* Tile modes. */
 231     uint32_t                    si_tile_mode_array[32];
 232     uint32_t                    cik_macrotile_mode_array[16];
 233 };
 234
 235 /* Tiling info for display code, DRI sharing, and other data. */
 236 struct radeon_bo_metadata {
 237     /* Tiling flags describing the texture layout for display code
 238      * and DRI sharing.
 239      */
 240     enum radeon_bo_layout   microtile;
 241     enum radeon_bo_layout   macrotile;
 242     unsigned                pipe_config;
 243     unsigned                bankw;
 244     unsigned                bankh;
 245     unsigned                tile_split;
 246     unsigned                mtilea;
 247     unsigned                num_banks;
 248     unsigned                stride;
 249     bool                    scanout;
 250
 251     /* Additional metadata associated with the buffer, in bytes.
 252      * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 253      * Supported by amdgpu only.
 254      */
 255     uint32_t                size_metadata;
 256     uint32_t                metadata[64];
 257 };
 258
 259 enum radeon_feature_id {
 260     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 261     RADEON_FID_R300_CMASK_ACCESS,
 262 };
 263
 264 #define RADEON_SURF_MAX_LEVELS                  15
 265
 266 enum radeon_surf_mode {
 267     RADEON_SURF_MODE_LINEAR_ALIGNED = 1,
 268     RADEON_SURF_MODE_1D = 2,
 269     RADEON_SURF_MODE_2D = 3,
 270 };
 271
 272 /* These are defined exactly like GB_TILE_MODEn.MICRO_TILE_MODE_NEW. */
 273 enum radeon_micro_mode {
 274     RADEON_MICRO_MODE_DISPLAY = 0,
 275     RADEON_MICRO_MODE_THIN = 1,
 276     RADEON_MICRO_MODE_DEPTH = 2,
 277     RADEON_MICRO_MODE_ROTATED = 3,
 278 };
 279
 280 /* the first 16 bits are reserved for libdrm_radeon, don't use them */
 281 #define RADEON_SURF_SCANOUT                     (1 << 16)
 282 #define RADEON_SURF_ZBUFFER                     (1 << 17)
 283 #define RADEON_SURF_SBUFFER                     (1 << 18)
 284 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
 285 /* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
 286 #define RADEON_SURF_FMASK                       (1 << 21)
 287 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
 288 #define RADEON_SURF_TC_COMPATIBLE_HTILE         (1 << 23)
 289 #define RADEON_SURF_IMPORTED                    (1 << 24)
 290 #define RADEON_SURF_OPTIMIZE_FOR_SPACE          (1 << 25)
 291
 292 struct legacy_surf_level {
 293     uint64_t                    offset;
 294     uint64_t                    slice_size;
 295     uint64_t                    dcc_offset;
 296     uint64_t                    dcc_fast_clear_size;
 297     uint16_t                    nblk_x;
 298     uint16_t                    nblk_y;
 299     enum radeon_surf_mode       mode;
 300 };
 301
 302 struct legacy_surf_layout {
 303     unsigned                    bankw:4;  /* max 8 */
 304     unsigned                    bankh:4;  /* max 8 */
 305     unsigned                    mtilea:4; /* max 8 */
 306     unsigned                    tile_split:13;         /* max 4K */
 307     unsigned                    stencil_tile_split:13; /* max 4K */
 308     unsigned                    pipe_config:5;      /* max 17 */
 309     unsigned                    num_banks:5;        /* max 16 */
 310     unsigned                    macro_tile_index:4; /* max 15 */
 311
 312     /* Whether the depth miptree or stencil miptree as used by the DB are
 313      * adjusted from their TC compatible form to ensure depth/stencil
 314      * compatibility. If either is true, the corresponding plane cannot be
 315      * sampled from.
 316      */
 317     unsigned                    depth_adjusted:1;
 318     unsigned                    stencil_adjusted:1;
 319
 320     struct legacy_surf_level    level[RADEON_SURF_MAX_LEVELS];
 321     struct legacy_surf_level    stencil_level[RADEON_SURF_MAX_LEVELS];
 322     uint8_t                     tiling_index[RADEON_SURF_MAX_LEVELS];
 323     uint8_t                     stencil_tiling_index[RADEON_SURF_MAX_LEVELS];
 324 };
 325
 326 struct gfx9_surf_flags {
 327     uint16_t                    swizzle_mode; /* tile mode */
 328     uint16_t                    epitch; /* (pitch - 1) or (height - 1) */
 329 };
 330
 331 struct gfx9_surf_meta_flags {
 332     unsigned                    rb_aligned:1;   /* optimal for RBs */
 333     unsigned                    pipe_aligned:1; /* optimal for TC */
 334 };
 335
 336 struct gfx9_surf_layout {
 337     struct gfx9_surf_flags      surf;    /* color or depth surface */
 338     struct gfx9_surf_flags      fmask;   /* not added to surf_size */
 339     struct gfx9_surf_flags      stencil; /* added to surf_size, use stencil_offset */
 340
 341     struct gfx9_surf_meta_flags dcc;   /* metadata of color */
 342     struct gfx9_surf_meta_flags htile; /* metadata of depth and stencil */
 343     struct gfx9_surf_meta_flags cmask; /* metadata of fmask */
 344
 345     /* The size of the 2D plane containing all mipmap levels. */
 346     uint64_t                    surf_slice_size;
 347     uint16_t                    surf_pitch; /* in blocks */
 348     /* Y mipmap level offset in blocks. Only valid for LINEAR. */
 349     uint16_t                    surf_ymip_offset[RADEON_SURF_MAX_LEVELS];
 350
 351     uint16_t                    dcc_pitch_max;  /* (mip chain pitch - 1) */
 352
 353     uint64_t                    stencil_offset; /* separate stencil */
 354     uint64_t                    fmask_size;
 355     uint64_t                    cmask_size;
 356
 357     uint32_t                    fmask_alignment;
 358     uint32_t                    cmask_alignment;
 359 };
 360
 361 struct radeon_surf {
 362     /* Format properties. */
 363     unsigned                    blk_w:4;
 364     unsigned                    blk_h:4;
 365     unsigned                    bpe:5;
 366     /* Number of mipmap levels where DCC is enabled starting from level 0.
 367      * Non-zero levels may be disabled due to alignment constraints, but not
 368      * the first level.
 369      */
 370     unsigned                    num_dcc_levels:4;
 371     unsigned                    is_linear:1;
 372     /* Displayable, thin, depth, rotated. AKA D,S,Z,R swizzle modes. */
 373     unsigned                    micro_tile_mode:3;
 374     uint32_t                    flags;
 375
 376     /* These are return values. Some of them can be set by the caller, but
 377      * they will be treated as hints (e.g. bankw, bankh) and might be
 378      * changed by the calculator.
 379      */
 380     uint64_t                    surf_size;
 381     uint64_t                    dcc_size;
 382     uint64_t                    htile_size;
 383
 384     uint32_t                    surf_alignment;
 385     uint32_t                    dcc_alignment;
 386     uint32_t                    htile_alignment;
 387
 388     union {
 389         /* R600-VI return values.
 390          *
 391          * Some of them can be set by the caller if certain parameters are
 392          * desirable. The allocator will try to obey them.
 393          */
 394         struct legacy_surf_layout legacy;
 395
 396         /* GFX9+ return values. */
 397         struct gfx9_surf_layout gfx9;
 398     } u;
 399 };
 400
 401 struct radeon_bo_list_item {
 402     uint64_t bo_size;
 403     uint64_t vm_address;
 404     uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
 405 };
 406
 407 struct radeon_winsys {
 408     /**
 409      * The screen object this winsys was created for
 410      */
 411     struct pipe_screen *screen;
 412
 413     /**
 414      * Decrement the winsys reference count.
 415      *
 416      * \param ws  The winsys this function is called for.
 417      * \return    True if the winsys and screen should be destroyed.
 418      */
 419     bool (*unref)(struct radeon_winsys *ws);
 420
 421     /**
 422      * Destroy this winsys.
 423      *
 424      * \param ws        The winsys this function is called from.
 425      */
 426     void (*destroy)(struct radeon_winsys *ws);
 427
 428     /**
 429      * Query an info structure from winsys.
 430      *
 431      * \param ws        The winsys this function is called from.
 432      * \param info      Return structure
 433      */
 434     void (*query_info)(struct radeon_winsys *ws,
 435                        struct radeon_info *info);
 436
 437     /**************************************************************************
 438      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 439      *
 440      * Remember that gallium gets to choose the interface it needs, and the
 441      * window systems must then implement that interface (rather than the
 442      * other way around...).
 443      *************************************************************************/
 444
 445     /**
 446      * Create a buffer object.
 447      *
 448      * \param ws        The winsys this function is called from.
 449      * \param size      The size to allocate.
 450      * \param alignment An alignment of the buffer in memory.
 451      * \param use_reusable_pool Whether the cache buffer manager should be used.
 452      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 453      * \return          The created buffer object.
 454      */
 455     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 456                                        uint64_t size,
 457                                        unsigned alignment,
 458                                        enum radeon_bo_domain domain,
 459                                        enum radeon_bo_flag flags);
 460
 461     /**
 462      * Map the entire data store of a buffer object into the client's address
 463      * space.
 464      *
 465      * \param buf       A winsys buffer object to map.
 466      * \param cs        A command stream to flush if the buffer is referenced by it.
 467      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 468      * \return          The pointer at the beginning of the buffer.
 469      */
 470     void *(*buffer_map)(struct pb_buffer *buf,
 471                         struct radeon_winsys_cs *cs,
 472                         enum pipe_transfer_usage usage);
 473
 474     /**
 475      * Unmap a buffer object from the client's address space.
 476      *
 477      * \param buf       A winsys buffer object to unmap.
 478      */
 479     void (*buffer_unmap)(struct pb_buffer *buf);
 480
 481     /**
 482      * Wait for the buffer and return true if the buffer is not used
 483      * by the device.
 484      *
 485      * The timeout of 0 will only return the status.
 486      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
 487      * is idle.
 488      */
 489     bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
 490                         enum radeon_bo_usage usage);
 491
 492     /**
 493      * Return buffer metadata.
 494      * (tiling info for display code, DRI sharing, and other data)
 495      *
 496      * \param buf       A winsys buffer object to get the flags from.
 497      * \param md        Metadata
 498      */
 499     void (*buffer_get_metadata)(struct pb_buffer *buf,
 500                                 struct radeon_bo_metadata *md);
 501
 502     /**
 503      * Set buffer metadata.
 504      * (tiling info for display code, DRI sharing, and other data)
 505      *
 506      * \param buf       A winsys buffer object to set the flags for.
 507      * \param md        Metadata
 508      */
 509     void (*buffer_set_metadata)(struct pb_buffer *buf,
 510                                 struct radeon_bo_metadata *md);
 511
 512     /**
 513      * Get a winsys buffer from a winsys handle. The internal structure
 514      * of the handle is platform-specific and only a winsys should access it.
 515      *
 516      * \param ws        The winsys this function is called from.
 517      * \param whandle   A winsys handle pointer as was received from a state
 518      *                  tracker.
 519      * \param stride    The returned buffer stride in bytes.
 520      */
 521     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 522                                             struct winsys_handle *whandle,
 523                                             unsigned *stride, unsigned *offset);
 524
 525     /**
 526      * Get a winsys buffer from a user pointer. The resulting buffer can't
 527      * be exported. Both pointer and size must be page aligned.
 528      *
 529      * \param ws        The winsys this function is called from.
 530      * \param pointer   User pointer to turn into a buffer object.
 531      * \param Size      Size in bytes for the new buffer.
 532      */
 533     struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
 534                                          void *pointer, uint64_t size);
 535
 536     /**
 537      * Whether the buffer was created from a user pointer.
 538      *
 539      * \param buf       A winsys buffer object
 540      * \return          whether \p buf was created via buffer_from_ptr
 541      */
 542     bool (*buffer_is_user_ptr)(struct pb_buffer *buf);
 543
 544     /**
 545      * Get a winsys handle from a winsys buffer. The internal structure
 546      * of the handle is platform-specific and only a winsys should access it.
 547      *
 548      * \param buf       A winsys buffer object to get the handle from.
 549      * \param whandle   A winsys handle pointer.
 550      * \param stride    A stride of the buffer in bytes, for texturing.
 551      * \return          true on success.
 552      */
 553     bool (*buffer_get_handle)(struct pb_buffer *buf,
 554                               unsigned stride, unsigned offset,
 555                               unsigned slice_size,
 556                               struct winsys_handle *whandle);
 557
 558     /**
 559      * Return the virtual address of a buffer.
 560      *
 561      * When virtual memory is not in use, this is the offset relative to the
 562      * relocation base (non-zero for sub-allocated buffers).
 563      *
 564      * \param buf       A winsys buffer object
 565      * \return          virtual address
 566      */
 567     uint64_t (*buffer_get_virtual_address)(struct pb_buffer *buf);
 568
 569     /**
 570      * Return the offset of this buffer relative to the relocation base.
 571      * This is only non-zero for sub-allocated buffers.
 572      *
 573      * This is only supported in the radeon winsys, since amdgpu uses virtual
 574      * addresses in submissions even for the video engines.
 575      *
 576      * \param buf      A winsys buffer object
 577      * \return         the offset for relocations
 578      */
 579     unsigned (*buffer_get_reloc_offset)(struct pb_buffer *buf);
 580
 581     /**
 582      * Query the initial placement of the buffer from the kernel driver.
 583      */
 584     enum radeon_bo_domain (*buffer_get_initial_domain)(struct pb_buffer *buf);
 585
 586     /**************************************************************************
 587      * Command submission.
 588      *
 589      * Each pipe context should create its own command stream and submit
 590      * commands independently of other contexts.
 591      *************************************************************************/
 592
 593     /**
 594      * Create a command submission context.
 595      * Various command streams can be submitted to the same context.
 596      */
 597     struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 598
 599     /**
 600      * Destroy a context.
 601      */
 602     void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 603
 604     /**
 605      * Query a GPU reset status.
 606      */
 607     enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
 608
 609     /**
 610      * Create a command stream.
 611      *
 612      * \param ctx       The submission context
 613      * \param ring_type The ring type (GFX, DMA, UVD)
 614      * \param flush     Flush callback function associated with the command stream.
 615      * \param user      User pointer that will be passed to the flush callback.
 616      */
 617     struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys_ctx *ctx,
 618                                           enum ring_type ring_type,
 619                                           void (*flush)(void *ctx, unsigned flags,
 620                                                         struct pipe_fence_handle **fence),
 621                                           void *flush_ctx);
 622
 623     /**
 624      * Add a constant engine IB to a graphics CS. This makes the graphics CS
 625      * from "cs_create" a group of two IBs that share a buffer list and are
 626      * flushed together.
 627      *
 628      * The returned constant CS is only a stream for writing packets to the new
 629      * IB. Calling other winsys functions with it is not allowed, not even
 630      * "cs_destroy".
 631      *
 632      * In order to add buffers and check memory usage, use the graphics CS.
 633      * In order to flush it, use the graphics CS, which will flush both IBs.
 634      * Destroying the graphics CS will destroy both of them.
 635      *
 636      * \param cs  The graphics CS from "cs_create" that will hold the buffer
 637      *            list and will be used for flushing.
 638      */
 639     struct radeon_winsys_cs *(*cs_add_const_ib)(struct radeon_winsys_cs *cs);
 640
 641      /**
 642      * Add a constant engine preamble IB to a graphics CS. This add an extra IB
 643      * in similar manner to cs_add_const_ib. This should always be called after
 644      * cs_add_const_ib.
 645      *
 646      * The returned IB is a constant engine IB that only gets flushed if the
 647      * context changed.
 648      *
 649      * \param cs  The graphics CS from "cs_create" that will hold the buffer
 650      *            list and will be used for flushing.
 651      */
 652     struct radeon_winsys_cs *(*cs_add_const_preamble_ib)(struct radeon_winsys_cs *cs);
 653     /**
 654      * Destroy a command stream.
 655      *
 656      * \param cs        A command stream to destroy.
 657      */
 658     void (*cs_destroy)(struct radeon_winsys_cs *cs);
 659
 660     /**
 661      * Add a buffer. Each buffer used by a CS must be added using this function.
 662      *
 663      * \param cs      Command stream
 664      * \param buf     Buffer
 665      * \param usage   Whether the buffer is used for read and/or write.
 666      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 667      * \param priority  A higher number means a greater chance of being
 668      *                  placed in the requested domain. 15 is the maximum.
 669      * \return Buffer index.
 670      */
 671     unsigned (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 672                              struct pb_buffer *buf,
 673                              enum radeon_bo_usage usage,
 674                              enum radeon_bo_domain domain,
 675                              enum radeon_bo_priority priority);
 676
 677     /**
 678      * Return the index of an already-added buffer.
 679      *
 680      * Not supported on amdgpu. Drivers with GPUVM should not care about
 681      * buffer indices.
 682      *
 683      * \param cs        Command stream
 684      * \param buf       Buffer
 685      * \return          The buffer index, or -1 if the buffer has not been added.
 686      */
 687     int (*cs_lookup_buffer)(struct radeon_winsys_cs *cs,
 688                             struct pb_buffer *buf);
 689
 690     /**
 691      * Return true if there is enough memory in VRAM and GTT for the buffers
 692      * added so far. If the validation fails, all buffers which have
 693      * been added since the last call of cs_validate will be removed and
 694      * the CS will be flushed (provided there are still any buffers).
 695      *
 696      * \param cs        A command stream to validate.
 697      */
 698     bool (*cs_validate)(struct radeon_winsys_cs *cs);
 699
 700     /**
 701      * Check whether the given number of dwords is available in the IB.
 702      * Optionally chain a new chunk of the IB if necessary and supported.
 703      *
 704      * \param cs        A command stream.
 705      * \param dw        Number of CS dwords requested by the caller.
 706      */
 707     bool (*cs_check_space)(struct radeon_winsys_cs *cs, unsigned dw);
 708
 709     /**
 710      * Return the buffer list.
 711      *
 712      * This is the buffer list as passed to the kernel, i.e. it only contains
 713      * the parent buffers of sub-allocated buffers.
 714      *
 715      * \param cs    Command stream
 716      * \param list  Returned buffer list. Set to NULL to query the count only.
 717      * \return      The buffer count.
 718      */
 719     unsigned (*cs_get_buffer_list)(struct radeon_winsys_cs *cs,
 720                                    struct radeon_bo_list_item *list);
 721
 722     /**
 723      * Flush a command stream.
 724      *
 725      * \param cs          A command stream to flush.
 726      * \param flags,      RADEON_FLUSH_ASYNC or 0.
 727      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 728      *                    after the CS and is returned through this parameter.
 729      * \return Negative POSIX error code or 0 for success.
 730      *         Asynchronous submissions never return an error.
 731      */
 732     int (*cs_flush)(struct radeon_winsys_cs *cs,
 733                     unsigned flags,
 734                     struct pipe_fence_handle **fence);
 735
 736     /**
 737      * Create a fence before the CS is flushed.
 738      * The user must flush manually to complete the initializaton of the fence.
 739      * The fence must not be used before the flush.
 740      */
 741     struct pipe_fence_handle *(*cs_get_next_fence)(struct radeon_winsys_cs *cs);
 742
 743     /**
 744      * Return true if a buffer is referenced by a command stream.
 745      *
 746      * \param cs        A command stream.
 747      * \param buf       A winsys buffer.
 748      */
 749     bool (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
 750                                     struct pb_buffer *buf,
 751                                     enum radeon_bo_usage usage);
 752
 753     /**
 754      * Request access to a feature for a command stream.
 755      *
 756      * \param cs        A command stream.
 757      * \param fid       Feature ID, one of RADEON_FID_*
 758      * \param enable    Whether to enable or disable the feature.
 759      */
 760     bool (*cs_request_feature)(struct radeon_winsys_cs *cs,
 761                                enum radeon_feature_id fid,
 762                                bool enable);
 763      /**
 764       * Make sure all asynchronous flush of the cs have completed
 765       *
 766       * \param cs        A command stream.
 767       */
 768     void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
 769
 770     /**
 771      * Wait for the fence and return true if the fence has been signalled.
 772      * The timeout of 0 will only return the status.
 773      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 774      * is signalled.
 775      */
 776     bool (*fence_wait)(struct radeon_winsys *ws,
 777                        struct pipe_fence_handle *fence,
 778                        uint64_t timeout);
 779
 780     /**
 781      * Reference counting for fences.
 782      */
 783     void (*fence_reference)(struct pipe_fence_handle **dst,
 784                             struct pipe_fence_handle *src);
 785
 786     /**
 787      * Initialize surface
 788      *
 789      * \param ws        The winsys this function is called from.
 790      * \param tex       Input texture description
 791      * \param flags     Bitmask of RADEON_SURF_* flags
 792      * \param bpe       Bytes per pixel, it can be different for Z buffers.
 793      * \param mode      Preferred tile mode. (linear, 1D, or 2D)
 794      * \param surf      Output structure
 795      */
 796     int (*surface_init)(struct radeon_winsys *ws,
 797                         const struct pipe_resource *tex,
 798                         unsigned flags, unsigned bpe,
 799                         enum radeon_surf_mode mode,
 800                         struct radeon_surf *surf);
 801
 802     uint64_t (*query_value)(struct radeon_winsys *ws,
 803                             enum radeon_value_id value);
 804
 805     bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 806                            unsigned num_registers, uint32_t *out);
 807 };
 808
 809 static inline bool radeon_emitted(struct radeon_winsys_cs *cs, unsigned num_dw)
 810 {
 811     return cs && (cs->prev_dw + cs->current.cdw > num_dw);
 812 }
 813
 814 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 815 {
 816     cs->current.buf[cs->current.cdw++] = value;
 817 }
 818
 819 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 820                                      const uint32_t *values, unsigned count)
 821 {
 822     memcpy(cs->current.buf + cs->current.cdw, values, count * 4);
 823     cs->current.cdw += count;
 824 }
 825
 826 #endif