src/gallium/drivers/radeon/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #ifndef RADEON_WINSYS_H
  25 #define RADEON_WINSYS_H
  26
  27 /* The public winsys interface header for the radeon driver. */
  28
  29 #include "pipebuffer/pb_buffer.h"
  30
  31 #include "amd/common/amd_family.h"
  32
  33 #define RADEON_FLUSH_ASYNC              (1 << 0)
  34 #define RADEON_FLUSH_END_OF_FRAME       (1 << 1)
  35
  36 /* Tiling flags. */
  37 enum radeon_bo_layout {
  38     RADEON_LAYOUT_LINEAR = 0,
  39     RADEON_LAYOUT_TILED,
  40     RADEON_LAYOUT_SQUARETILED,
  41
  42     RADEON_LAYOUT_UNKNOWN
  43 };
  44
  45 enum radeon_bo_domain { /* bitfield */
  46     RADEON_DOMAIN_GTT  = 2,
  47     RADEON_DOMAIN_VRAM = 4,
  48     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  49 };
  50
  51 enum radeon_bo_flag { /* bitfield */
  52     RADEON_FLAG_GTT_WC =        (1 << 0),
  53     RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  54     RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  55     RADEON_FLAG_HANDLE =        (1 << 3), /* the buffer most not be suballocated */
  56 };
  57
  58 enum radeon_bo_usage { /* bitfield */
  59     RADEON_USAGE_READ = 2,
  60     RADEON_USAGE_WRITE = 4,
  61     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE,
  62
  63     /* The winsys ensures that the CS submission will be scheduled after
  64      * previously flushed CSs referencing this BO in a conflicting way.
  65      */
  66     RADEON_USAGE_SYNCHRONIZED = 8
  67 };
  68
  69 enum ring_type {
  70     RING_GFX = 0,
  71     RING_COMPUTE,
  72     RING_DMA,
  73     RING_UVD,
  74     RING_VCE,
  75     RING_LAST,
  76 };
  77
  78 enum radeon_value_id {
  79     RADEON_REQUESTED_VRAM_MEMORY,
  80     RADEON_REQUESTED_GTT_MEMORY,
  81     RADEON_MAPPED_VRAM,
  82     RADEON_MAPPED_GTT,
  83     RADEON_BUFFER_WAIT_TIME_NS,
  84     RADEON_NUM_MAPPED_BUFFERS,
  85     RADEON_TIMESTAMP,
  86     RADEON_NUM_GFX_IBS,
  87     RADEON_NUM_SDMA_IBS,
  88     RADEON_NUM_BYTES_MOVED,
  89     RADEON_NUM_EVICTIONS,
  90     RADEON_VRAM_USAGE,
  91     RADEON_GTT_USAGE,
  92     RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
  93     RADEON_CURRENT_SCLK,
  94     RADEON_CURRENT_MCLK,
  95     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
  96 };
  97
  98 /* Each group of four has the same priority. */
  99 enum radeon_bo_priority {
 100     RADEON_PRIO_FENCE = 0,
 101     RADEON_PRIO_TRACE,
 102     RADEON_PRIO_SO_FILLED_SIZE,
 103     RADEON_PRIO_QUERY,
 104
 105     RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
 106     RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
 107     RADEON_PRIO_DRAW_INDIRECT,
 108     RADEON_PRIO_INDEX_BUFFER,
 109
 110     RADEON_PRIO_VCE = 8,
 111     RADEON_PRIO_UVD,
 112     RADEON_PRIO_SDMA_BUFFER,
 113     RADEON_PRIO_SDMA_TEXTURE,
 114
 115     RADEON_PRIO_CP_DMA = 12,
 116
 117     RADEON_PRIO_CONST_BUFFER = 16,
 118     RADEON_PRIO_DESCRIPTORS,
 119     RADEON_PRIO_BORDER_COLORS,
 120
 121     RADEON_PRIO_SAMPLER_BUFFER = 20,
 122     RADEON_PRIO_VERTEX_BUFFER,
 123
 124     RADEON_PRIO_SHADER_RW_BUFFER = 24,
 125     RADEON_PRIO_COMPUTE_GLOBAL,
 126
 127     RADEON_PRIO_SAMPLER_TEXTURE = 28,
 128     RADEON_PRIO_SHADER_RW_IMAGE,
 129
 130     RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 32,
 131
 132     RADEON_PRIO_COLOR_BUFFER = 36,
 133
 134     RADEON_PRIO_DEPTH_BUFFER = 40,
 135
 136     RADEON_PRIO_COLOR_BUFFER_MSAA = 44,
 137
 138     RADEON_PRIO_DEPTH_BUFFER_MSAA = 48,
 139
 140     RADEON_PRIO_CMASK = 52,
 141     RADEON_PRIO_DCC,
 142     RADEON_PRIO_HTILE,
 143     RADEON_PRIO_SHADER_BINARY, /* the hw can't hide instruction cache misses */
 144
 145     RADEON_PRIO_SHADER_RINGS = 56,
 146
 147     RADEON_PRIO_SCRATCH_BUFFER = 60,
 148     /* 63 is the maximum value */
 149 };
 150
 151 struct winsys_handle;
 152 struct radeon_winsys_ctx;
 153
 154 struct radeon_winsys_cs_chunk {
 155     unsigned cdw;  /* Number of used dwords. */
 156     unsigned max_dw; /* Maximum number of dwords. */
 157     uint32_t *buf; /* The base pointer of the chunk. */
 158 };
 159
 160 struct radeon_winsys_cs {
 161     struct radeon_winsys_cs_chunk current;
 162     struct radeon_winsys_cs_chunk *prev;
 163     unsigned                      num_prev; /* Number of previous chunks. */
 164     unsigned                      max_prev; /* Space in array pointed to by prev. */
 165     unsigned                      prev_dw; /* Total number of dwords in previous chunks. */
 166
 167     /* Memory usage of the buffer list. These are always 0 for CE and preamble
 168      * IBs. */
 169     uint64_t                      used_vram;
 170     uint64_t                      used_gart;
 171 };
 172
 173 struct radeon_info {
 174     /* PCI info: domain:bus:dev:func */
 175     uint32_t                    pci_domain;
 176     uint32_t                    pci_bus;
 177     uint32_t                    pci_dev;
 178     uint32_t                    pci_func;
 179
 180     /* Device info. */
 181     uint32_t                    pci_id;
 182     enum radeon_family          family;
 183     enum chip_class             chip_class;
 184     uint32_t                    gart_page_size;
 185     uint64_t                    gart_size;
 186     uint64_t                    vram_size;
 187     uint64_t                    vram_vis_size;
 188     uint64_t                    max_alloc_size;
 189     uint32_t                    min_alloc_size;
 190     bool                        has_dedicated_vram;
 191     bool                        has_virtual_memory;
 192     bool                        gfx_ib_pad_with_type2;
 193     bool                        has_sdma;
 194     bool                        has_uvd;
 195     uint32_t                    uvd_fw_version;
 196     uint32_t                    vce_fw_version;
 197     uint32_t                    me_fw_version;
 198     uint32_t                    pfp_fw_version;
 199     uint32_t                    ce_fw_version;
 200     uint32_t                    vce_harvest_config;
 201     uint32_t                    clock_crystal_freq;
 202
 203     /* Kernel info. */
 204     uint32_t                    drm_major; /* version */
 205     uint32_t                    drm_minor;
 206     uint32_t                    drm_patchlevel;
 207     bool                        has_userptr;
 208
 209     /* Shader cores. */
 210     uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
 211     uint32_t                    max_shader_clock;
 212     uint32_t                    num_good_compute_units;
 213     uint32_t                    max_se; /* shader engines */
 214     uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 215
 216     /* Render backends (color + depth blocks). */
 217     uint32_t                    r300_num_gb_pipes;
 218     uint32_t                    r300_num_z_pipes;
 219     uint32_t                    r600_gb_backend_map; /* R600 harvest config */
 220     bool                        r600_gb_backend_map_valid;
 221     uint32_t                    r600_num_banks;
 222     uint32_t                    num_render_backends;
 223     uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
 224     uint32_t                    pipe_interleave_bytes;
 225     uint32_t                    enabled_rb_mask; /* GCN harvest config */
 226
 227     /* Tile modes. */
 228     uint32_t                    si_tile_mode_array[32];
 229     uint32_t                    cik_macrotile_mode_array[16];
 230 };
 231
 232 /* Tiling info for display code, DRI sharing, and other data. */
 233 struct radeon_bo_metadata {
 234     /* Tiling flags describing the texture layout for display code
 235      * and DRI sharing.
 236      */
 237     enum radeon_bo_layout   microtile;
 238     enum radeon_bo_layout   macrotile;
 239     unsigned                pipe_config;
 240     unsigned                bankw;
 241     unsigned                bankh;
 242     unsigned                tile_split;
 243     unsigned                mtilea;
 244     unsigned                num_banks;
 245     unsigned                stride;
 246     bool                    scanout;
 247
 248     /* Additional metadata associated with the buffer, in bytes.
 249      * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 250      * Supported by amdgpu only.
 251      */
 252     uint32_t                size_metadata;
 253     uint32_t                metadata[64];
 254 };
 255
 256 enum radeon_feature_id {
 257     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 258     RADEON_FID_R300_CMASK_ACCESS,
 259 };
 260
 261 #define RADEON_SURF_MAX_LEVELS                  15
 262
 263 enum radeon_surf_mode {
 264     RADEON_SURF_MODE_LINEAR_ALIGNED = 1,
 265     RADEON_SURF_MODE_1D = 2,
 266     RADEON_SURF_MODE_2D = 3,
 267 };
 268
 269 /* These are defined exactly like GB_TILE_MODEn.MICRO_TILE_MODE_NEW. */
 270 enum radeon_micro_mode {
 271     RADEON_MICRO_MODE_DISPLAY = 0,
 272     RADEON_MICRO_MODE_THIN = 1,
 273     RADEON_MICRO_MODE_DEPTH = 2,
 274     RADEON_MICRO_MODE_ROTATED = 3,
 275 };
 276
 277 /* the first 16 bits are reserved for libdrm_radeon, don't use them */
 278 #define RADEON_SURF_SCANOUT                     (1 << 16)
 279 #define RADEON_SURF_ZBUFFER                     (1 << 17)
 280 #define RADEON_SURF_SBUFFER                     (1 << 18)
 281 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
 282 /* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
 283 #define RADEON_SURF_FMASK                       (1 << 21)
 284 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
 285 #define RADEON_SURF_TC_COMPATIBLE_HTILE         (1 << 23)
 286 #define RADEON_SURF_IMPORTED                    (1 << 24)
 287 #define RADEON_SURF_OPTIMIZE_FOR_SPACE          (1 << 25)
 288
 289 struct radeon_surf_level {
 290     uint64_t                    offset;
 291     uint64_t                    slice_size;
 292     uint64_t                    dcc_offset;
 293     uint64_t                    dcc_fast_clear_size;
 294     uint16_t                    nblk_x;
 295     uint16_t                    nblk_y;
 296     enum radeon_surf_mode       mode;
 297 };
 298
 299 struct radeon_surf {
 300     /* Format properties. */
 301     unsigned                    blk_w:4;
 302     unsigned                    blk_h:4;
 303     unsigned                    bpe:5;
 304     /* Number of mipmap levels where DCC is enabled starting from level 0.
 305      * Non-zero levels may be disabled due to alignment constraints, but not
 306      * the first level.
 307      */
 308     unsigned                    num_dcc_levels:4;
 309     unsigned                    is_linear:1;
 310     uint32_t                    flags;
 311
 312     /* These are return values. Some of them can be set by the caller, but
 313      * they will be treated as hints (e.g. bankw, bankh) and might be
 314      * changed by the calculator.
 315      */
 316     uint64_t                    surf_size;
 317     uint64_t                    dcc_size;
 318     uint64_t                    htile_size;
 319
 320     uint32_t                    surf_alignment;
 321     uint32_t                    dcc_alignment;
 322     uint32_t                    htile_alignment;
 323
 324     /* This applies to EG and later. */
 325     unsigned                    bankw:4;  /* max 8 */
 326     unsigned                    bankh:4;  /* max 8 */
 327     unsigned                    mtilea:4; /* max 8 */
 328     unsigned                    tile_split:13;         /* max 4K */
 329     unsigned                    stencil_tile_split:13; /* max 4K */
 330     unsigned                    pipe_config:5;      /* max 17 */
 331     unsigned                    num_banks:5;        /* max 16 */
 332     unsigned                    macro_tile_index:4; /* max 15 */
 333     unsigned                    micro_tile_mode:3; /* displayable, thin, depth, rotated */
 334
 335     /* Whether the depth miptree or stencil miptree as used by the DB are
 336      * adjusted from their TC compatible form to ensure depth/stencil
 337      * compatibility. If either is true, the corresponding plane cannot be
 338      * sampled from.
 339      */
 340     unsigned                    depth_adjusted:1;
 341     unsigned                    stencil_adjusted:1;
 342
 343     struct radeon_surf_level    level[RADEON_SURF_MAX_LEVELS];
 344     struct radeon_surf_level    stencil_level[RADEON_SURF_MAX_LEVELS];
 345     uint8_t                     tiling_index[RADEON_SURF_MAX_LEVELS];
 346     uint8_t                     stencil_tiling_index[RADEON_SURF_MAX_LEVELS];
 347 };
 348
 349 struct radeon_bo_list_item {
 350     uint64_t bo_size;
 351     uint64_t vm_address;
 352     uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
 353 };
 354
 355 struct radeon_winsys {
 356     /**
 357      * The screen object this winsys was created for
 358      */
 359     struct pipe_screen *screen;
 360
 361     /**
 362      * Decrement the winsys reference count.
 363      *
 364      * \param ws  The winsys this function is called for.
 365      * \return    True if the winsys and screen should be destroyed.
 366      */
 367     bool (*unref)(struct radeon_winsys *ws);
 368
 369     /**
 370      * Destroy this winsys.
 371      *
 372      * \param ws        The winsys this function is called from.
 373      */
 374     void (*destroy)(struct radeon_winsys *ws);
 375
 376     /**
 377      * Query an info structure from winsys.
 378      *
 379      * \param ws        The winsys this function is called from.
 380      * \param info      Return structure
 381      */
 382     void (*query_info)(struct radeon_winsys *ws,
 383                        struct radeon_info *info);
 384
 385     /**************************************************************************
 386      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 387      *
 388      * Remember that gallium gets to choose the interface it needs, and the
 389      * window systems must then implement that interface (rather than the
 390      * other way around...).
 391      *************************************************************************/
 392
 393     /**
 394      * Create a buffer object.
 395      *
 396      * \param ws        The winsys this function is called from.
 397      * \param size      The size to allocate.
 398      * \param alignment An alignment of the buffer in memory.
 399      * \param use_reusable_pool Whether the cache buffer manager should be used.
 400      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 401      * \return          The created buffer object.
 402      */
 403     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 404                                        uint64_t size,
 405                                        unsigned alignment,
 406                                        enum radeon_bo_domain domain,
 407                                        enum radeon_bo_flag flags);
 408
 409     /**
 410      * Map the entire data store of a buffer object into the client's address
 411      * space.
 412      *
 413      * \param buf       A winsys buffer object to map.
 414      * \param cs        A command stream to flush if the buffer is referenced by it.
 415      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 416      * \return          The pointer at the beginning of the buffer.
 417      */
 418     void *(*buffer_map)(struct pb_buffer *buf,
 419                         struct radeon_winsys_cs *cs,
 420                         enum pipe_transfer_usage usage);
 421
 422     /**
 423      * Unmap a buffer object from the client's address space.
 424      *
 425      * \param buf       A winsys buffer object to unmap.
 426      */
 427     void (*buffer_unmap)(struct pb_buffer *buf);
 428
 429     /**
 430      * Wait for the buffer and return true if the buffer is not used
 431      * by the device.
 432      *
 433      * The timeout of 0 will only return the status.
 434      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
 435      * is idle.
 436      */
 437     bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
 438                         enum radeon_bo_usage usage);
 439
 440     /**
 441      * Return buffer metadata.
 442      * (tiling info for display code, DRI sharing, and other data)
 443      *
 444      * \param buf       A winsys buffer object to get the flags from.
 445      * \param md        Metadata
 446      */
 447     void (*buffer_get_metadata)(struct pb_buffer *buf,
 448                                 struct radeon_bo_metadata *md);
 449
 450     /**
 451      * Set buffer metadata.
 452      * (tiling info for display code, DRI sharing, and other data)
 453      *
 454      * \param buf       A winsys buffer object to set the flags for.
 455      * \param md        Metadata
 456      */
 457     void (*buffer_set_metadata)(struct pb_buffer *buf,
 458                                 struct radeon_bo_metadata *md);
 459
 460     /**
 461      * Get a winsys buffer from a winsys handle. The internal structure
 462      * of the handle is platform-specific and only a winsys should access it.
 463      *
 464      * \param ws        The winsys this function is called from.
 465      * \param whandle   A winsys handle pointer as was received from a state
 466      *                  tracker.
 467      * \param stride    The returned buffer stride in bytes.
 468      */
 469     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 470                                             struct winsys_handle *whandle,
 471                                             unsigned *stride, unsigned *offset);
 472
 473     /**
 474      * Get a winsys buffer from a user pointer. The resulting buffer can't
 475      * be exported. Both pointer and size must be page aligned.
 476      *
 477      * \param ws        The winsys this function is called from.
 478      * \param pointer   User pointer to turn into a buffer object.
 479      * \param Size      Size in bytes for the new buffer.
 480      */
 481     struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
 482                                          void *pointer, uint64_t size);
 483
 484     /**
 485      * Whether the buffer was created from a user pointer.
 486      *
 487      * \param buf       A winsys buffer object
 488      * \return          whether \p buf was created via buffer_from_ptr
 489      */
 490     bool (*buffer_is_user_ptr)(struct pb_buffer *buf);
 491
 492     /**
 493      * Get a winsys handle from a winsys buffer. The internal structure
 494      * of the handle is platform-specific and only a winsys should access it.
 495      *
 496      * \param buf       A winsys buffer object to get the handle from.
 497      * \param whandle   A winsys handle pointer.
 498      * \param stride    A stride of the buffer in bytes, for texturing.
 499      * \return          true on success.
 500      */
 501     bool (*buffer_get_handle)(struct pb_buffer *buf,
 502                               unsigned stride, unsigned offset,
 503                               unsigned slice_size,
 504                               struct winsys_handle *whandle);
 505
 506     /**
 507      * Return the virtual address of a buffer.
 508      *
 509      * When virtual memory is not in use, this is the offset relative to the
 510      * relocation base (non-zero for sub-allocated buffers).
 511      *
 512      * \param buf       A winsys buffer object
 513      * \return          virtual address
 514      */
 515     uint64_t (*buffer_get_virtual_address)(struct pb_buffer *buf);
 516
 517     /**
 518      * Return the offset of this buffer relative to the relocation base.
 519      * This is only non-zero for sub-allocated buffers.
 520      *
 521      * This is only supported in the radeon winsys, since amdgpu uses virtual
 522      * addresses in submissions even for the video engines.
 523      *
 524      * \param buf      A winsys buffer object
 525      * \return         the offset for relocations
 526      */
 527     unsigned (*buffer_get_reloc_offset)(struct pb_buffer *buf);
 528
 529     /**
 530      * Query the initial placement of the buffer from the kernel driver.
 531      */
 532     enum radeon_bo_domain (*buffer_get_initial_domain)(struct pb_buffer *buf);
 533
 534     /**************************************************************************
 535      * Command submission.
 536      *
 537      * Each pipe context should create its own command stream and submit
 538      * commands independently of other contexts.
 539      *************************************************************************/
 540
 541     /**
 542      * Create a command submission context.
 543      * Various command streams can be submitted to the same context.
 544      */
 545     struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 546
 547     /**
 548      * Destroy a context.
 549      */
 550     void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 551
 552     /**
 553      * Query a GPU reset status.
 554      */
 555     enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
 556
 557     /**
 558      * Create a command stream.
 559      *
 560      * \param ctx       The submission context
 561      * \param ring_type The ring type (GFX, DMA, UVD)
 562      * \param flush     Flush callback function associated with the command stream.
 563      * \param user      User pointer that will be passed to the flush callback.
 564      */
 565     struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys_ctx *ctx,
 566                                           enum ring_type ring_type,
 567                                           void (*flush)(void *ctx, unsigned flags,
 568                                                         struct pipe_fence_handle **fence),
 569                                           void *flush_ctx);
 570
 571     /**
 572      * Add a constant engine IB to a graphics CS. This makes the graphics CS
 573      * from "cs_create" a group of two IBs that share a buffer list and are
 574      * flushed together.
 575      *
 576      * The returned constant CS is only a stream for writing packets to the new
 577      * IB. Calling other winsys functions with it is not allowed, not even
 578      * "cs_destroy".
 579      *
 580      * In order to add buffers and check memory usage, use the graphics CS.
 581      * In order to flush it, use the graphics CS, which will flush both IBs.
 582      * Destroying the graphics CS will destroy both of them.
 583      *
 584      * \param cs  The graphics CS from "cs_create" that will hold the buffer
 585      *            list and will be used for flushing.
 586      */
 587     struct radeon_winsys_cs *(*cs_add_const_ib)(struct radeon_winsys_cs *cs);
 588
 589      /**
 590      * Add a constant engine preamble IB to a graphics CS. This add an extra IB
 591      * in similar manner to cs_add_const_ib. This should always be called after
 592      * cs_add_const_ib.
 593      *
 594      * The returned IB is a constant engine IB that only gets flushed if the
 595      * context changed.
 596      *
 597      * \param cs  The graphics CS from "cs_create" that will hold the buffer
 598      *            list and will be used for flushing.
 599      */
 600     struct radeon_winsys_cs *(*cs_add_const_preamble_ib)(struct radeon_winsys_cs *cs);
 601     /**
 602      * Destroy a command stream.
 603      *
 604      * \param cs        A command stream to destroy.
 605      */
 606     void (*cs_destroy)(struct radeon_winsys_cs *cs);
 607
 608     /**
 609      * Add a buffer. Each buffer used by a CS must be added using this function.
 610      *
 611      * \param cs      Command stream
 612      * \param buf     Buffer
 613      * \param usage   Whether the buffer is used for read and/or write.
 614      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 615      * \param priority  A higher number means a greater chance of being
 616      *                  placed in the requested domain. 15 is the maximum.
 617      * \return Buffer index.
 618      */
 619     unsigned (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 620                              struct pb_buffer *buf,
 621                              enum radeon_bo_usage usage,
 622                              enum radeon_bo_domain domain,
 623                              enum radeon_bo_priority priority);
 624
 625     /**
 626      * Return the index of an already-added buffer.
 627      *
 628      * Not supported on amdgpu. Drivers with GPUVM should not care about
 629      * buffer indices.
 630      *
 631      * \param cs        Command stream
 632      * \param buf       Buffer
 633      * \return          The buffer index, or -1 if the buffer has not been added.
 634      */
 635     int (*cs_lookup_buffer)(struct radeon_winsys_cs *cs,
 636                             struct pb_buffer *buf);
 637
 638     /**
 639      * Return true if there is enough memory in VRAM and GTT for the buffers
 640      * added so far. If the validation fails, all buffers which have
 641      * been added since the last call of cs_validate will be removed and
 642      * the CS will be flushed (provided there are still any buffers).
 643      *
 644      * \param cs        A command stream to validate.
 645      */
 646     bool (*cs_validate)(struct radeon_winsys_cs *cs);
 647
 648     /**
 649      * Check whether the given number of dwords is available in the IB.
 650      * Optionally chain a new chunk of the IB if necessary and supported.
 651      *
 652      * \param cs        A command stream.
 653      * \param dw        Number of CS dwords requested by the caller.
 654      */
 655     bool (*cs_check_space)(struct radeon_winsys_cs *cs, unsigned dw);
 656
 657     /**
 658      * Return the buffer list.
 659      *
 660      * This is the buffer list as passed to the kernel, i.e. it only contains
 661      * the parent buffers of sub-allocated buffers.
 662      *
 663      * \param cs    Command stream
 664      * \param list  Returned buffer list. Set to NULL to query the count only.
 665      * \return      The buffer count.
 666      */
 667     unsigned (*cs_get_buffer_list)(struct radeon_winsys_cs *cs,
 668                                    struct radeon_bo_list_item *list);
 669
 670     /**
 671      * Flush a command stream.
 672      *
 673      * \param cs          A command stream to flush.
 674      * \param flags,      RADEON_FLUSH_ASYNC or 0.
 675      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 676      *                    after the CS and is returned through this parameter.
 677      * \return Negative POSIX error code or 0 for success.
 678      *         Asynchronous submissions never return an error.
 679      */
 680     int (*cs_flush)(struct radeon_winsys_cs *cs,
 681                     unsigned flags,
 682                     struct pipe_fence_handle **fence);
 683
 684     /**
 685      * Create a fence before the CS is flushed.
 686      * The user must flush manually to complete the initializaton of the fence.
 687      * The fence must not be used before the flush.
 688      */
 689     struct pipe_fence_handle *(*cs_get_next_fence)(struct radeon_winsys_cs *cs);
 690
 691     /**
 692      * Return true if a buffer is referenced by a command stream.
 693      *
 694      * \param cs        A command stream.
 695      * \param buf       A winsys buffer.
 696      */
 697     bool (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
 698                                     struct pb_buffer *buf,
 699                                     enum radeon_bo_usage usage);
 700
 701     /**
 702      * Request access to a feature for a command stream.
 703      *
 704      * \param cs        A command stream.
 705      * \param fid       Feature ID, one of RADEON_FID_*
 706      * \param enable    Whether to enable or disable the feature.
 707      */
 708     bool (*cs_request_feature)(struct radeon_winsys_cs *cs,
 709                                enum radeon_feature_id fid,
 710                                bool enable);
 711      /**
 712       * Make sure all asynchronous flush of the cs have completed
 713       *
 714       * \param cs        A command stream.
 715       */
 716     void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
 717
 718     /**
 719      * Wait for the fence and return true if the fence has been signalled.
 720      * The timeout of 0 will only return the status.
 721      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 722      * is signalled.
 723      */
 724     bool (*fence_wait)(struct radeon_winsys *ws,
 725                        struct pipe_fence_handle *fence,
 726                        uint64_t timeout);
 727
 728     /**
 729      * Reference counting for fences.
 730      */
 731     void (*fence_reference)(struct pipe_fence_handle **dst,
 732                             struct pipe_fence_handle *src);
 733
 734     /**
 735      * Initialize surface
 736      *
 737      * \param ws        The winsys this function is called from.
 738      * \param tex       Input texture description
 739      * \param flags     Bitmask of RADEON_SURF_* flags
 740      * \param bpe       Bytes per pixel, it can be different for Z buffers.
 741      * \param mode      Preferred tile mode. (linear, 1D, or 2D)
 742      * \param surf      Output structure
 743      */
 744     int (*surface_init)(struct radeon_winsys *ws,
 745                         const struct pipe_resource *tex,
 746                         unsigned flags, unsigned bpe,
 747                         enum radeon_surf_mode mode,
 748                         struct radeon_surf *surf);
 749
 750     uint64_t (*query_value)(struct radeon_winsys *ws,
 751                             enum radeon_value_id value);
 752
 753     bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 754                            unsigned num_registers, uint32_t *out);
 755 };
 756
 757 static inline bool radeon_emitted(struct radeon_winsys_cs *cs, unsigned num_dw)
 758 {
 759     return cs && (cs->prev_dw + cs->current.cdw > num_dw);
 760 }
 761
 762 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 763 {
 764     cs->current.buf[cs->current.cdw++] = value;
 765 }
 766
 767 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 768                                      const uint32_t *values, unsigned count)
 769 {
 770     memcpy(cs->current.buf + cs->current.cdw, values, count * 4);
 771     cs->current.cdw += count;
 772 }
 773
 774 #endif