src/gallium/drivers/radeon/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #ifndef RADEON_WINSYS_H
  25 #define RADEON_WINSYS_H
  26
  27 /* The public winsys interface header for the radeon driver. */
  28
  29 #include "pipebuffer/pb_buffer.h"
  30
  31 #define RADEON_FLUSH_ASYNC              (1 << 0)
  32 #define RADEON_FLUSH_KEEP_TILING_FLAGS  (1 << 1)
  33 #define RADEON_FLUSH_END_OF_FRAME       (1 << 2)
  34
  35 /* Tiling flags. */
  36 enum radeon_bo_layout {
  37     RADEON_LAYOUT_LINEAR = 0,
  38     RADEON_LAYOUT_TILED,
  39     RADEON_LAYOUT_SQUARETILED,
  40
  41     RADEON_LAYOUT_UNKNOWN
  42 };
  43
  44 enum radeon_bo_domain { /* bitfield */
  45     RADEON_DOMAIN_GTT  = 2,
  46     RADEON_DOMAIN_VRAM = 4,
  47     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  48 };
  49
  50 enum radeon_bo_flag { /* bitfield */
  51     RADEON_FLAG_GTT_WC =        (1 << 0),
  52     RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  53     RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  54 };
  55
  56 enum radeon_bo_usage { /* bitfield */
  57     RADEON_USAGE_READ = 2,
  58     RADEON_USAGE_WRITE = 4,
  59     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
  60 };
  61
  62 enum radeon_family {
  63     CHIP_UNKNOWN = 0,
  64     CHIP_R300, /* R3xx-based cores. */
  65     CHIP_R350,
  66     CHIP_RV350,
  67     CHIP_RV370,
  68     CHIP_RV380,
  69     CHIP_RS400,
  70     CHIP_RC410,
  71     CHIP_RS480,
  72     CHIP_R420,     /* R4xx-based cores. */
  73     CHIP_R423,
  74     CHIP_R430,
  75     CHIP_R480,
  76     CHIP_R481,
  77     CHIP_RV410,
  78     CHIP_RS600,
  79     CHIP_RS690,
  80     CHIP_RS740,
  81     CHIP_RV515,    /* R5xx-based cores. */
  82     CHIP_R520,
  83     CHIP_RV530,
  84     CHIP_R580,
  85     CHIP_RV560,
  86     CHIP_RV570,
  87     CHIP_R600,
  88     CHIP_RV610,
  89     CHIP_RV630,
  90     CHIP_RV670,
  91     CHIP_RV620,
  92     CHIP_RV635,
  93     CHIP_RS780,
  94     CHIP_RS880,
  95     CHIP_RV770,
  96     CHIP_RV730,
  97     CHIP_RV710,
  98     CHIP_RV740,
  99     CHIP_CEDAR,
 100     CHIP_REDWOOD,
 101     CHIP_JUNIPER,
 102     CHIP_CYPRESS,
 103     CHIP_HEMLOCK,
 104     CHIP_PALM,
 105     CHIP_SUMO,
 106     CHIP_SUMO2,
 107     CHIP_BARTS,
 108     CHIP_TURKS,
 109     CHIP_CAICOS,
 110     CHIP_CAYMAN,
 111     CHIP_ARUBA,
 112     CHIP_TAHITI,
 113     CHIP_PITCAIRN,
 114     CHIP_VERDE,
 115     CHIP_OLAND,
 116     CHIP_HAINAN,
 117     CHIP_BONAIRE,
 118     CHIP_KAVERI,
 119     CHIP_KABINI,
 120     CHIP_HAWAII,
 121     CHIP_MULLINS,
 122     CHIP_TONGA,
 123     CHIP_ICELAND,
 124     CHIP_CARRIZO,
 125     CHIP_FIJI,
 126     CHIP_STONEY,
 127     CHIP_LAST,
 128 };
 129
 130 enum chip_class {
 131     CLASS_UNKNOWN = 0,
 132     R300,
 133     R400,
 134     R500,
 135     R600,
 136     R700,
 137     EVERGREEN,
 138     CAYMAN,
 139     SI,
 140     CIK,
 141     VI,
 142 };
 143
 144 enum ring_type {
 145     RING_GFX = 0,
 146     RING_COMPUTE,
 147     RING_DMA,
 148     RING_UVD,
 149     RING_VCE,
 150     RING_LAST,
 151 };
 152
 153 enum radeon_value_id {
 154     RADEON_REQUESTED_VRAM_MEMORY,
 155     RADEON_REQUESTED_GTT_MEMORY,
 156     RADEON_BUFFER_WAIT_TIME_NS,
 157     RADEON_TIMESTAMP,
 158     RADEON_NUM_CS_FLUSHES,
 159     RADEON_NUM_BYTES_MOVED,
 160     RADEON_VRAM_USAGE,
 161     RADEON_GTT_USAGE,
 162     RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
 163     RADEON_CURRENT_SCLK,
 164     RADEON_CURRENT_MCLK,
 165     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
 166 };
 167
 168 /* Each group of four has the same priority. */
 169 enum radeon_bo_priority {
 170     RADEON_PRIO_FENCE = 0,
 171     RADEON_PRIO_TRACE,
 172     RADEON_PRIO_SO_FILLED_SIZE,
 173     RADEON_PRIO_QUERY,
 174
 175     RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
 176     RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
 177     RADEON_PRIO_DRAW_INDIRECT,
 178     RADEON_PRIO_INDEX_BUFFER,
 179
 180     RADEON_PRIO_CP_DMA = 8,
 181
 182     RADEON_PRIO_VCE = 12,
 183     RADEON_PRIO_UVD,
 184     RADEON_PRIO_SDMA_BUFFER,
 185     RADEON_PRIO_SDMA_TEXTURE,
 186
 187     RADEON_PRIO_USER_SHADER = 16,
 188     RADEON_PRIO_INTERNAL_SHADER, /* fetch shader, etc. */
 189
 190     /* gap: 20 */
 191
 192     RADEON_PRIO_CONST_BUFFER = 24,
 193     RADEON_PRIO_DESCRIPTORS,
 194     RADEON_PRIO_BORDER_COLORS,
 195
 196     RADEON_PRIO_SAMPLER_BUFFER = 28,
 197     RADEON_PRIO_VERTEX_BUFFER,
 198
 199     RADEON_PRIO_SHADER_RW_BUFFER = 32,
 200     RADEON_PRIO_RINGS_STREAMOUT,
 201     RADEON_PRIO_SCRATCH_BUFFER,
 202     RADEON_PRIO_COMPUTE_GLOBAL,
 203
 204     RADEON_PRIO_SAMPLER_TEXTURE = 36,
 205     RADEON_PRIO_SHADER_RW_IMAGE,
 206
 207     RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 40,
 208
 209     RADEON_PRIO_COLOR_BUFFER = 44,
 210
 211     RADEON_PRIO_DEPTH_BUFFER = 48,
 212
 213     RADEON_PRIO_COLOR_BUFFER_MSAA = 52,
 214
 215     RADEON_PRIO_DEPTH_BUFFER_MSAA = 56,
 216
 217     RADEON_PRIO_CMASK = 60,
 218     RADEON_PRIO_DCC,
 219     RADEON_PRIO_HTILE,
 220     /* 63 is the maximum value */
 221 };
 222
 223 struct winsys_handle;
 224 struct radeon_winsys_ctx;
 225
 226 struct radeon_winsys_cs {
 227     unsigned                    cdw;  /* Number of used dwords. */
 228     unsigned                    max_dw; /* Maximum number of dwords. */
 229     uint32_t                    *buf; /* The command buffer. */
 230     enum ring_type              ring_type;
 231 };
 232
 233 struct radeon_info {
 234     /* Device info. */
 235     uint32_t                    pci_id;
 236     enum radeon_family          family;
 237     enum chip_class             chip_class;
 238     uint64_t                    gart_size;
 239     uint64_t                    vram_size;
 240     boolean                     has_virtual_memory;
 241     bool                        gfx_ib_pad_with_type2;
 242     boolean                     has_sdma;
 243     boolean                     has_uvd;
 244     uint32_t                    vce_fw_version;
 245     uint32_t                    vce_harvest_config;
 246     uint32_t                    clock_crystal_freq;
 247
 248     /* Kernel info. */
 249     uint32_t                    drm_major; /* version */
 250     uint32_t                    drm_minor;
 251     uint32_t                    drm_patchlevel;
 252     boolean                     has_userptr;
 253
 254     /* Shader cores. */
 255     uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
 256     uint32_t                    max_shader_clock;
 257     uint32_t                    num_good_compute_units;
 258     uint32_t                    max_se; /* shader engines */
 259     uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 260
 261     /* Render backends (color + depth blocks). */
 262     uint32_t                    r300_num_gb_pipes;
 263     uint32_t                    r300_num_z_pipes;
 264     uint32_t                    r600_gb_backend_map; /* R600 harvest config */
 265     boolean                     r600_gb_backend_map_valid;
 266     uint32_t                    r600_num_banks;
 267     uint32_t                    num_render_backends;
 268     uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
 269     uint32_t                    pipe_interleave_bytes;
 270     uint32_t                    enabled_rb_mask; /* GCN harvest config */
 271
 272     /* Tile modes. */
 273     boolean                     si_tile_mode_array_valid;
 274     uint32_t                    si_tile_mode_array[32];
 275     boolean                     cik_macrotile_mode_array_valid;
 276     uint32_t                    cik_macrotile_mode_array[16];
 277 };
 278
 279 enum radeon_feature_id {
 280     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 281     RADEON_FID_R300_CMASK_ACCESS,
 282 };
 283
 284 #define RADEON_SURF_MAX_LEVEL                   32
 285
 286 #define RADEON_SURF_TYPE_MASK                   0xFF
 287 #define RADEON_SURF_TYPE_SHIFT                  0
 288 #define     RADEON_SURF_TYPE_1D                     0
 289 #define     RADEON_SURF_TYPE_2D                     1
 290 #define     RADEON_SURF_TYPE_3D                     2
 291 #define     RADEON_SURF_TYPE_CUBEMAP                3
 292 #define     RADEON_SURF_TYPE_1D_ARRAY               4
 293 #define     RADEON_SURF_TYPE_2D_ARRAY               5
 294 #define RADEON_SURF_MODE_MASK                   0xFF
 295 #define RADEON_SURF_MODE_SHIFT                  8
 296 #define     RADEON_SURF_MODE_LINEAR                 0
 297 #define     RADEON_SURF_MODE_LINEAR_ALIGNED         1
 298 #define     RADEON_SURF_MODE_1D                     2
 299 #define     RADEON_SURF_MODE_2D                     3
 300 #define RADEON_SURF_SCANOUT                     (1 << 16)
 301 #define RADEON_SURF_ZBUFFER                     (1 << 17)
 302 #define RADEON_SURF_SBUFFER                     (1 << 18)
 303 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
 304 #define RADEON_SURF_HAS_SBUFFER_MIPTREE         (1 << 19)
 305 #define RADEON_SURF_HAS_TILE_MODE_INDEX         (1 << 20)
 306 #define RADEON_SURF_FMASK                       (1 << 21)
 307
 308 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
 309 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
 310 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
 311
 312 struct radeon_surf_level {
 313     uint64_t                    offset;
 314     uint64_t                    slice_size;
 315     uint32_t                    npix_x;
 316     uint32_t                    npix_y;
 317     uint32_t                    npix_z;
 318     uint32_t                    nblk_x;
 319     uint32_t                    nblk_y;
 320     uint32_t                    nblk_z;
 321     uint32_t                    pitch_bytes;
 322     uint32_t                    mode;
 323     uint64_t                    dcc_offset;
 324 };
 325
 326 struct radeon_surf {
 327     /* These are inputs to the calculator. */
 328     uint32_t                    npix_x;
 329     uint32_t                    npix_y;
 330     uint32_t                    npix_z;
 331     uint32_t                    blk_w;
 332     uint32_t                    blk_h;
 333     uint32_t                    blk_d;
 334     uint32_t                    array_size;
 335     uint32_t                    last_level;
 336     uint32_t                    bpe;
 337     uint32_t                    nsamples;
 338     uint32_t                    flags;
 339
 340     /* These are return values. Some of them can be set by the caller, but
 341      * they will be treated as hints (e.g. bankw, bankh) and might be
 342      * changed by the calculator.
 343      */
 344     uint64_t                    bo_size;
 345     uint64_t                    bo_alignment;
 346     /* This applies to EG and later. */
 347     uint32_t                    bankw;
 348     uint32_t                    bankh;
 349     uint32_t                    mtilea;
 350     uint32_t                    tile_split;
 351     uint32_t                    stencil_tile_split;
 352     uint64_t                    stencil_offset;
 353     struct radeon_surf_level    level[RADEON_SURF_MAX_LEVEL];
 354     struct radeon_surf_level    stencil_level[RADEON_SURF_MAX_LEVEL];
 355     uint32_t                    tiling_index[RADEON_SURF_MAX_LEVEL];
 356     uint32_t                    stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
 357     uint32_t                    pipe_config;
 358     uint32_t                    num_banks;
 359
 360     uint64_t                    dcc_size;
 361     uint64_t                    dcc_alignment;
 362 };
 363
 364 struct radeon_bo_list_item {
 365     struct pb_buffer *buf;
 366     uint64_t vm_address;
 367     uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
 368 };
 369
 370 struct radeon_winsys {
 371     /**
 372      * The screen object this winsys was created for
 373      */
 374     struct pipe_screen *screen;
 375
 376     /**
 377      * Decrement the winsys reference count.
 378      *
 379      * \param ws  The winsys this function is called for.
 380      * \return    True if the winsys and screen should be destroyed.
 381      */
 382     bool (*unref)(struct radeon_winsys *ws);
 383
 384     /**
 385      * Destroy this winsys.
 386      *
 387      * \param ws        The winsys this function is called from.
 388      */
 389     void (*destroy)(struct radeon_winsys *ws);
 390
 391     /**
 392      * Query an info structure from winsys.
 393      *
 394      * \param ws        The winsys this function is called from.
 395      * \param info      Return structure
 396      */
 397     void (*query_info)(struct radeon_winsys *ws,
 398                        struct radeon_info *info);
 399
 400     /**************************************************************************
 401      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 402      *
 403      * Remember that gallium gets to choose the interface it needs, and the
 404      * window systems must then implement that interface (rather than the
 405      * other way around...).
 406      *************************************************************************/
 407
 408     /**
 409      * Create a buffer object.
 410      *
 411      * \param ws        The winsys this function is called from.
 412      * \param size      The size to allocate.
 413      * \param alignment An alignment of the buffer in memory.
 414      * \param use_reusable_pool Whether the cache buffer manager should be used.
 415      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 416      * \return          The created buffer object.
 417      */
 418     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 419                                        unsigned size,
 420                                        unsigned alignment,
 421                                        boolean use_reusable_pool,
 422                                        enum radeon_bo_domain domain,
 423                                        enum radeon_bo_flag flags);
 424
 425     /**
 426      * Map the entire data store of a buffer object into the client's address
 427      * space.
 428      *
 429      * \param buf       A winsys buffer object to map.
 430      * \param cs        A command stream to flush if the buffer is referenced by it.
 431      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 432      * \return          The pointer at the beginning of the buffer.
 433      */
 434     void *(*buffer_map)(struct pb_buffer *buf,
 435                         struct radeon_winsys_cs *cs,
 436                         enum pipe_transfer_usage usage);
 437
 438     /**
 439      * Unmap a buffer object from the client's address space.
 440      *
 441      * \param buf       A winsys buffer object to unmap.
 442      */
 443     void (*buffer_unmap)(struct pb_buffer *buf);
 444
 445     /**
 446      * Wait for the buffer and return true if the buffer is not used
 447      * by the device.
 448      *
 449      * The timeout of 0 will only return the status.
 450      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
 451      * is idle.
 452      */
 453     bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
 454                         enum radeon_bo_usage usage);
 455
 456     /**
 457      * Return tiling flags describing a memory layout of a buffer object.
 458      *
 459      * \param buf       A winsys buffer object to get the flags from.
 460      * \param macrotile A pointer to the return value of the microtile flag.
 461      * \param microtile A pointer to the return value of the macrotile flag.
 462      *
 463      * \note microtile and macrotile are not bitmasks!
 464      */
 465     void (*buffer_get_tiling)(struct pb_buffer *buf,
 466                               enum radeon_bo_layout *microtile,
 467                               enum radeon_bo_layout *macrotile,
 468                               unsigned *bankw, unsigned *bankh,
 469                               unsigned *tile_split,
 470                               unsigned *stencil_tile_split,
 471                               unsigned *mtilea,
 472                               bool *scanout);
 473
 474     /**
 475      * Set tiling flags describing a memory layout of a buffer object.
 476      *
 477      * \param buf       A winsys buffer object to set the flags for.
 478      * \param cs        A command stream to flush if the buffer is referenced by it.
 479      * \param macrotile A macrotile flag.
 480      * \param microtile A microtile flag.
 481      * \param stride    A stride of the buffer in bytes, for texturing.
 482      *
 483      * \note microtile and macrotile are not bitmasks!
 484      */
 485     void (*buffer_set_tiling)(struct pb_buffer *buf,
 486                               struct radeon_winsys_cs *rcs,
 487                               enum radeon_bo_layout microtile,
 488                               enum radeon_bo_layout macrotile,
 489                               unsigned pipe_config,
 490                               unsigned bankw, unsigned bankh,
 491                               unsigned tile_split,
 492                               unsigned stencil_tile_split,
 493                               unsigned mtilea, unsigned num_banks,
 494                               unsigned stride,
 495                               bool scanout);
 496
 497     /**
 498      * Get a winsys buffer from a winsys handle. The internal structure
 499      * of the handle is platform-specific and only a winsys should access it.
 500      *
 501      * \param ws        The winsys this function is called from.
 502      * \param whandle   A winsys handle pointer as was received from a state
 503      *                  tracker.
 504      * \param stride    The returned buffer stride in bytes.
 505      */
 506     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 507                                             struct winsys_handle *whandle,
 508                                             unsigned *stride);
 509
 510     /**
 511      * Get a winsys buffer from a user pointer. The resulting buffer can't
 512      * be exported. Both pointer and size must be page aligned.
 513      *
 514      * \param ws        The winsys this function is called from.
 515      * \param pointer   User pointer to turn into a buffer object.
 516      * \param Size      Size in bytes for the new buffer.
 517      */
 518     struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
 519                                          void *pointer, unsigned size);
 520
 521     /**
 522      * Whether the buffer was created from a user pointer.
 523      *
 524      * \param buf       A winsys buffer object
 525      * \return          whether \p buf was created via buffer_from_ptr
 526      */
 527     bool (*buffer_is_user_ptr)(struct pb_buffer *buf);
 528
 529     /**
 530      * Get a winsys handle from a winsys buffer. The internal structure
 531      * of the handle is platform-specific and only a winsys should access it.
 532      *
 533      * \param buf       A winsys buffer object to get the handle from.
 534      * \param whandle   A winsys handle pointer.
 535      * \param stride    A stride of the buffer in bytes, for texturing.
 536      * \return          TRUE on success.
 537      */
 538     boolean (*buffer_get_handle)(struct pb_buffer *buf,
 539                                  unsigned stride,
 540                                  struct winsys_handle *whandle);
 541
 542     /**
 543      * Return the virtual address of a buffer.
 544      *
 545      * \param buf       A winsys buffer object
 546      * \return          virtual address
 547      */
 548     uint64_t (*buffer_get_virtual_address)(struct pb_buffer *buf);
 549
 550     /**
 551      * Query the initial placement of the buffer from the kernel driver.
 552      */
 553     enum radeon_bo_domain (*buffer_get_initial_domain)(struct pb_buffer *buf);
 554
 555     /**************************************************************************
 556      * Command submission.
 557      *
 558      * Each pipe context should create its own command stream and submit
 559      * commands independently of other contexts.
 560      *************************************************************************/
 561
 562     /**
 563      * Create a command submission context.
 564      * Various command streams can be submitted to the same context.
 565      */
 566     struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 567
 568     /**
 569      * Destroy a context.
 570      */
 571     void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 572
 573     /**
 574      * Query a GPU reset status.
 575      */
 576     enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
 577
 578     /**
 579      * Create a command stream.
 580      *
 581      * \param ctx       The submission context
 582      * \param ring_type The ring type (GFX, DMA, UVD)
 583      * \param flush     Flush callback function associated with the command stream.
 584      * \param user      User pointer that will be passed to the flush callback.
 585      * \param trace_buf Trace buffer when tracing is enabled
 586      */
 587     struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys_ctx *ctx,
 588                                           enum ring_type ring_type,
 589                                           void (*flush)(void *ctx, unsigned flags,
 590                                                         struct pipe_fence_handle **fence),
 591                                           void *flush_ctx,
 592                                           struct pb_buffer *trace_buf);
 593
 594     /**
 595      * Destroy a command stream.
 596      *
 597      * \param cs        A command stream to destroy.
 598      */
 599     void (*cs_destroy)(struct radeon_winsys_cs *cs);
 600
 601     /**
 602      * Add a buffer. Each buffer used by a CS must be added using this function.
 603      *
 604      * \param cs      Command stream
 605      * \param buf     Buffer
 606      * \param usage   Whether the buffer is used for read and/or write.
 607      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 608      * \param priority  A higher number means a greater chance of being
 609      *                  placed in the requested domain. 15 is the maximum.
 610      * \return Buffer index.
 611      */
 612     unsigned (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 613                              struct pb_buffer *buf,
 614                              enum radeon_bo_usage usage,
 615                              enum radeon_bo_domain domain,
 616                              enum radeon_bo_priority priority);
 617
 618     /**
 619      * Return the index of an already-added buffer.
 620      *
 621      * \param cs        Command stream
 622      * \param buf       Buffer
 623      * \return          The buffer index, or -1 if the buffer has not been added.
 624      */
 625     int (*cs_lookup_buffer)(struct radeon_winsys_cs *cs,
 626                             struct pb_buffer *buf);
 627
 628     /**
 629      * Return TRUE if there is enough memory in VRAM and GTT for the buffers
 630      * added so far. If the validation fails, all buffers which have
 631      * been added since the last call of cs_validate will be removed and
 632      * the CS will be flushed (provided there are still any buffers).
 633      *
 634      * \param cs        A command stream to validate.
 635      */
 636     boolean (*cs_validate)(struct radeon_winsys_cs *cs);
 637
 638     /**
 639      * Return TRUE if there is enough memory in VRAM and GTT for the buffers
 640      * added so far.
 641      *
 642      * \param cs        A command stream to validate.
 643      * \param vram      VRAM memory size pending to be use
 644      * \param gtt       GTT memory size pending to be use
 645      */
 646     boolean (*cs_memory_below_limit)(struct radeon_winsys_cs *cs, uint64_t vram, uint64_t gtt);
 647
 648     /**
 649      * Return the buffer list.
 650      *
 651      * \param cs    Command stream
 652      * \param list  Returned buffer list. Set to NULL to query the count only.
 653      * \return      The buffer count.
 654      */
 655     unsigned (*cs_get_buffer_list)(struct radeon_winsys_cs *cs,
 656                                    struct radeon_bo_list_item *list);
 657
 658     /**
 659      * Flush a command stream.
 660      *
 661      * \param cs          A command stream to flush.
 662      * \param flags,      RADEON_FLUSH_ASYNC or 0.
 663      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 664      *                    after the CS and is returned through this parameter.
 665      * \param cs_trace_id A unique identifier of the cs, used for tracing.
 666      */
 667     void (*cs_flush)(struct radeon_winsys_cs *cs,
 668                      unsigned flags,
 669                      struct pipe_fence_handle **fence,
 670                      uint32_t cs_trace_id);
 671
 672     /**
 673      * Return TRUE if a buffer is referenced by a command stream.
 674      *
 675      * \param cs        A command stream.
 676      * \param buf       A winsys buffer.
 677      */
 678     boolean (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
 679                                        struct pb_buffer *buf,
 680                                        enum radeon_bo_usage usage);
 681
 682     /**
 683      * Request access to a feature for a command stream.
 684      *
 685      * \param cs        A command stream.
 686      * \param fid       Feature ID, one of RADEON_FID_*
 687      * \param enable    Whether to enable or disable the feature.
 688      */
 689     boolean (*cs_request_feature)(struct radeon_winsys_cs *cs,
 690                                   enum radeon_feature_id fid,
 691                                   boolean enable);
 692      /**
 693       * Make sure all asynchronous flush of the cs have completed
 694       *
 695       * \param cs        A command stream.
 696       */
 697     void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
 698
 699     /**
 700      * Wait for the fence and return true if the fence has been signalled.
 701      * The timeout of 0 will only return the status.
 702      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 703      * is signalled.
 704      */
 705     bool (*fence_wait)(struct radeon_winsys *ws,
 706                        struct pipe_fence_handle *fence,
 707                        uint64_t timeout);
 708
 709     /**
 710      * Reference counting for fences.
 711      */
 712     void (*fence_reference)(struct pipe_fence_handle **dst,
 713                             struct pipe_fence_handle *src);
 714
 715     /**
 716      * Initialize surface
 717      *
 718      * \param ws        The winsys this function is called from.
 719      * \param surf      Surface structure ptr
 720      */
 721     int (*surface_init)(struct radeon_winsys *ws,
 722                         struct radeon_surf *surf);
 723
 724     /**
 725      * Find best values for a surface
 726      *
 727      * \param ws        The winsys this function is called from.
 728      * \param surf      Surface structure ptr
 729      */
 730     int (*surface_best)(struct radeon_winsys *ws,
 731                         struct radeon_surf *surf);
 732
 733     uint64_t (*query_value)(struct radeon_winsys *ws,
 734                             enum radeon_value_id value);
 735
 736     bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 737                            unsigned num_registers, uint32_t *out);
 738 };
 739
 740
 741 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 742 {
 743     cs->buf[cs->cdw++] = value;
 744 }
 745
 746 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 747                                      const uint32_t *values, unsigned count)
 748 {
 749     memcpy(cs->buf+cs->cdw, values, count * 4);
 750     cs->cdw += count;
 751 }
 752
 753 #endif