src/gallium/drivers/radeon/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #ifndef RADEON_WINSYS_H
  25 #define RADEON_WINSYS_H
  26
  27 /* The public winsys interface header for the radeon driver. */
  28
  29 #include "pipebuffer/pb_buffer.h"
  30
  31 #include "amd/common/amd_family.h"
  32
  33 #define RADEON_FLUSH_ASYNC              (1 << 0)
  34 #define RADEON_FLUSH_END_OF_FRAME       (1 << 1)
  35
  36 /* Tiling flags. */
  37 enum radeon_bo_layout {
  38     RADEON_LAYOUT_LINEAR = 0,
  39     RADEON_LAYOUT_TILED,
  40     RADEON_LAYOUT_SQUARETILED,
  41
  42     RADEON_LAYOUT_UNKNOWN
  43 };
  44
  45 enum radeon_bo_domain { /* bitfield */
  46     RADEON_DOMAIN_GTT  = 2,
  47     RADEON_DOMAIN_VRAM = 4,
  48     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  49 };
  50
  51 enum radeon_bo_flag { /* bitfield */
  52     RADEON_FLAG_GTT_WC =        (1 << 0),
  53     RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  54     RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  55     RADEON_FLAG_HANDLE =        (1 << 3), /* the buffer most not be suballocated */
  56 };
  57
  58 enum radeon_bo_usage { /* bitfield */
  59     RADEON_USAGE_READ = 2,
  60     RADEON_USAGE_WRITE = 4,
  61     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE,
  62
  63     /* The winsys ensures that the CS submission will be scheduled after
  64      * previously flushed CSs referencing this BO in a conflicting way.
  65      */
  66     RADEON_USAGE_SYNCHRONIZED = 8
  67 };
  68
  69 enum ring_type {
  70     RING_GFX = 0,
  71     RING_COMPUTE,
  72     RING_DMA,
  73     RING_UVD,
  74     RING_VCE,
  75     RING_LAST,
  76 };
  77
  78 enum radeon_value_id {
  79     RADEON_REQUESTED_VRAM_MEMORY,
  80     RADEON_REQUESTED_GTT_MEMORY,
  81     RADEON_MAPPED_VRAM,
  82     RADEON_MAPPED_GTT,
  83     RADEON_BUFFER_WAIT_TIME_NS,
  84     RADEON_TIMESTAMP,
  85     RADEON_NUM_CS_FLUSHES,
  86     RADEON_NUM_BYTES_MOVED,
  87     RADEON_NUM_EVICTIONS,
  88     RADEON_VRAM_USAGE,
  89     RADEON_GTT_USAGE,
  90     RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
  91     RADEON_CURRENT_SCLK,
  92     RADEON_CURRENT_MCLK,
  93     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
  94 };
  95
  96 /* Each group of four has the same priority. */
  97 enum radeon_bo_priority {
  98     RADEON_PRIO_FENCE = 0,
  99     RADEON_PRIO_TRACE,
 100     RADEON_PRIO_SO_FILLED_SIZE,
 101     RADEON_PRIO_QUERY,
 102
 103     RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
 104     RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
 105     RADEON_PRIO_DRAW_INDIRECT,
 106     RADEON_PRIO_INDEX_BUFFER,
 107
 108     RADEON_PRIO_VCE = 8,
 109     RADEON_PRIO_UVD,
 110     RADEON_PRIO_SDMA_BUFFER,
 111     RADEON_PRIO_SDMA_TEXTURE,
 112
 113     RADEON_PRIO_CP_DMA = 12,
 114
 115     RADEON_PRIO_CONST_BUFFER = 16,
 116     RADEON_PRIO_DESCRIPTORS,
 117     RADEON_PRIO_BORDER_COLORS,
 118
 119     RADEON_PRIO_SAMPLER_BUFFER = 20,
 120     RADEON_PRIO_VERTEX_BUFFER,
 121
 122     RADEON_PRIO_SHADER_RW_BUFFER = 24,
 123     RADEON_PRIO_COMPUTE_GLOBAL,
 124
 125     RADEON_PRIO_SAMPLER_TEXTURE = 28,
 126     RADEON_PRIO_SHADER_RW_IMAGE,
 127
 128     RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 32,
 129
 130     RADEON_PRIO_COLOR_BUFFER = 36,
 131
 132     RADEON_PRIO_DEPTH_BUFFER = 40,
 133
 134     RADEON_PRIO_COLOR_BUFFER_MSAA = 44,
 135
 136     RADEON_PRIO_DEPTH_BUFFER_MSAA = 48,
 137
 138     RADEON_PRIO_CMASK = 52,
 139     RADEON_PRIO_DCC,
 140     RADEON_PRIO_HTILE,
 141     RADEON_PRIO_SHADER_BINARY, /* the hw can't hide instruction cache misses */
 142
 143     RADEON_PRIO_SHADER_RINGS = 56,
 144
 145     RADEON_PRIO_SCRATCH_BUFFER = 60,
 146     /* 63 is the maximum value */
 147 };
 148
 149 struct winsys_handle;
 150 struct radeon_winsys_ctx;
 151
 152 struct radeon_winsys_cs_chunk {
 153     unsigned cdw;  /* Number of used dwords. */
 154     unsigned max_dw; /* Maximum number of dwords. */
 155     uint32_t *buf; /* The base pointer of the chunk. */
 156 };
 157
 158 struct radeon_winsys_cs {
 159     struct radeon_winsys_cs_chunk current;
 160     struct radeon_winsys_cs_chunk *prev;
 161     unsigned                      num_prev; /* Number of previous chunks. */
 162     unsigned                      max_prev; /* Space in array pointed to by prev. */
 163     unsigned                      prev_dw; /* Total number of dwords in previous chunks. */
 164
 165     /* Memory usage of the buffer list. These are always 0 for CE and preamble
 166      * IBs. */
 167     uint64_t                      used_vram;
 168     uint64_t                      used_gart;
 169 };
 170
 171 struct radeon_info {
 172     /* PCI info: domain:bus:dev:func */
 173     uint32_t                    pci_domain;
 174     uint32_t                    pci_bus;
 175     uint32_t                    pci_dev;
 176     uint32_t                    pci_func;
 177
 178     /* Device info. */
 179     uint32_t                    pci_id;
 180     enum radeon_family          family;
 181     enum chip_class             chip_class;
 182     uint32_t                    gart_page_size;
 183     uint64_t                    gart_size;
 184     uint64_t                    vram_size;
 185     uint64_t                    max_alloc_size;
 186     uint32_t                    min_alloc_size;
 187     bool                        has_dedicated_vram;
 188     bool                        has_virtual_memory;
 189     bool                        gfx_ib_pad_with_type2;
 190     bool                        has_sdma;
 191     bool                        has_uvd;
 192     uint32_t                    uvd_fw_version;
 193     uint32_t                    vce_fw_version;
 194     uint32_t                    me_fw_version;
 195     uint32_t                    pfp_fw_version;
 196     uint32_t                    ce_fw_version;
 197     uint32_t                    vce_harvest_config;
 198     uint32_t                    clock_crystal_freq;
 199
 200     /* Kernel info. */
 201     uint32_t                    drm_major; /* version */
 202     uint32_t                    drm_minor;
 203     uint32_t                    drm_patchlevel;
 204     bool                        has_userptr;
 205
 206     /* Shader cores. */
 207     uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
 208     uint32_t                    max_shader_clock;
 209     uint32_t                    num_good_compute_units;
 210     uint32_t                    max_se; /* shader engines */
 211     uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 212
 213     /* Render backends (color + depth blocks). */
 214     uint32_t                    r300_num_gb_pipes;
 215     uint32_t                    r300_num_z_pipes;
 216     uint32_t                    r600_gb_backend_map; /* R600 harvest config */
 217     bool                        r600_gb_backend_map_valid;
 218     uint32_t                    r600_num_banks;
 219     uint32_t                    num_render_backends;
 220     uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
 221     uint32_t                    pipe_interleave_bytes;
 222     uint32_t                    enabled_rb_mask; /* GCN harvest config */
 223
 224     /* Tile modes. */
 225     uint32_t                    si_tile_mode_array[32];
 226     uint32_t                    cik_macrotile_mode_array[16];
 227 };
 228
 229 /* Tiling info for display code, DRI sharing, and other data. */
 230 struct radeon_bo_metadata {
 231     /* Tiling flags describing the texture layout for display code
 232      * and DRI sharing.
 233      */
 234     enum radeon_bo_layout   microtile;
 235     enum radeon_bo_layout   macrotile;
 236     unsigned                pipe_config;
 237     unsigned                bankw;
 238     unsigned                bankh;
 239     unsigned                tile_split;
 240     unsigned                mtilea;
 241     unsigned                num_banks;
 242     unsigned                stride;
 243     bool                    scanout;
 244
 245     /* Additional metadata associated with the buffer, in bytes.
 246      * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 247      * Supported by amdgpu only.
 248      */
 249     uint32_t                size_metadata;
 250     uint32_t                metadata[64];
 251 };
 252
 253 enum radeon_feature_id {
 254     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 255     RADEON_FID_R300_CMASK_ACCESS,
 256 };
 257
 258 #define RADEON_SURF_MAX_LEVEL                   32
 259
 260 enum radeon_surf_mode {
 261     RADEON_SURF_MODE_LINEAR_ALIGNED = 1,
 262     RADEON_SURF_MODE_1D = 2,
 263     RADEON_SURF_MODE_2D = 3,
 264 };
 265
 266 #define RADEON_SURF_TYPE_MASK                   0xFF
 267 #define RADEON_SURF_TYPE_SHIFT                  0
 268 #define     RADEON_SURF_TYPE_1D                     0
 269 #define     RADEON_SURF_TYPE_2D                     1
 270 #define     RADEON_SURF_TYPE_3D                     2
 271 #define     RADEON_SURF_TYPE_CUBEMAP                3
 272 #define     RADEON_SURF_TYPE_1D_ARRAY               4
 273 #define     RADEON_SURF_TYPE_2D_ARRAY               5
 274 #define RADEON_SURF_MODE_MASK                   0xFF
 275 #define RADEON_SURF_MODE_SHIFT                  8
 276 #define RADEON_SURF_SCANOUT                     (1 << 16)
 277 #define RADEON_SURF_ZBUFFER                     (1 << 17)
 278 #define RADEON_SURF_SBUFFER                     (1 << 18)
 279 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
 280 #define RADEON_SURF_HAS_SBUFFER_MIPTREE         (1 << 19)
 281 #define RADEON_SURF_HAS_TILE_MODE_INDEX         (1 << 20)
 282 #define RADEON_SURF_FMASK                       (1 << 21)
 283 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
 284 #define RADEON_SURF_TC_COMPATIBLE_HTILE         (1 << 23)
 285 #define RADEON_SURF_IMPORTED                    (1 << 24)
 286
 287 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
 288 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
 289 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
 290
 291 struct radeon_surf_level {
 292     uint64_t                    offset;
 293     uint64_t                    slice_size;
 294     uint32_t                    npix_x;
 295     uint32_t                    npix_y;
 296     uint32_t                    npix_z;
 297     uint32_t                    nblk_x;
 298     uint32_t                    nblk_y;
 299     uint32_t                    nblk_z;
 300     uint32_t                    pitch_bytes;
 301     enum radeon_surf_mode       mode;
 302     uint64_t                    dcc_offset;
 303     uint64_t                    dcc_fast_clear_size;
 304     bool                        dcc_enabled;
 305 };
 306
 307 struct radeon_surf {
 308     /* These are inputs to the calculator. */
 309     uint32_t                    npix_x;
 310     uint32_t                    npix_y;
 311     uint32_t                    npix_z;
 312     uint32_t                    blk_w;
 313     uint32_t                    blk_h;
 314     uint32_t                    blk_d;
 315     uint32_t                    array_size;
 316     uint32_t                    last_level;
 317     uint32_t                    bpe;
 318     uint32_t                    nsamples;
 319     uint32_t                    flags;
 320
 321     /* These are return values. Some of them can be set by the caller, but
 322      * they will be treated as hints (e.g. bankw, bankh) and might be
 323      * changed by the calculator.
 324      */
 325     uint64_t                    bo_size;
 326     uint64_t                    bo_alignment;
 327     /* This applies to EG and later. */
 328     uint32_t                    bankw;
 329     uint32_t                    bankh;
 330     uint32_t                    mtilea;
 331     uint32_t                    tile_split;
 332     uint32_t                    stencil_tile_split;
 333     struct radeon_surf_level    level[RADEON_SURF_MAX_LEVEL];
 334     struct radeon_surf_level    stencil_level[RADEON_SURF_MAX_LEVEL];
 335     uint32_t                    tiling_index[RADEON_SURF_MAX_LEVEL];
 336     uint32_t                    stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
 337     uint32_t                    pipe_config;
 338     uint32_t                    num_banks;
 339     uint32_t                    macro_tile_index;
 340     uint32_t                    micro_tile_mode; /* displayable, thin, depth, rotated */
 341
 342     /* Whether the depth miptree or stencil miptree as used by the DB are
 343      * adjusted from their TC compatible form to ensure depth/stencil
 344      * compatibility. If either is true, the corresponding plane cannot be
 345      * sampled from.
 346      */
 347     bool                        depth_adjusted;
 348     bool                        stencil_adjusted;
 349
 350     uint64_t                    dcc_size;
 351     uint64_t                    dcc_alignment;
 352     /* TC-compatible HTILE only. */
 353     uint64_t                    htile_size;
 354     uint64_t                    htile_alignment;
 355 };
 356
 357 struct radeon_bo_list_item {
 358     uint64_t bo_size;
 359     uint64_t vm_address;
 360     uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
 361 };
 362
 363 struct radeon_winsys {
 364     /**
 365      * The screen object this winsys was created for
 366      */
 367     struct pipe_screen *screen;
 368
 369     /**
 370      * Decrement the winsys reference count.
 371      *
 372      * \param ws  The winsys this function is called for.
 373      * \return    True if the winsys and screen should be destroyed.
 374      */
 375     bool (*unref)(struct radeon_winsys *ws);
 376
 377     /**
 378      * Destroy this winsys.
 379      *
 380      * \param ws        The winsys this function is called from.
 381      */
 382     void (*destroy)(struct radeon_winsys *ws);
 383
 384     /**
 385      * Query an info structure from winsys.
 386      *
 387      * \param ws        The winsys this function is called from.
 388      * \param info      Return structure
 389      */
 390     void (*query_info)(struct radeon_winsys *ws,
 391                        struct radeon_info *info);
 392
 393     /**************************************************************************
 394      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 395      *
 396      * Remember that gallium gets to choose the interface it needs, and the
 397      * window systems must then implement that interface (rather than the
 398      * other way around...).
 399      *************************************************************************/
 400
 401     /**
 402      * Create a buffer object.
 403      *
 404      * \param ws        The winsys this function is called from.
 405      * \param size      The size to allocate.
 406      * \param alignment An alignment of the buffer in memory.
 407      * \param use_reusable_pool Whether the cache buffer manager should be used.
 408      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 409      * \return          The created buffer object.
 410      */
 411     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 412                                        uint64_t size,
 413                                        unsigned alignment,
 414                                        enum radeon_bo_domain domain,
 415                                        enum radeon_bo_flag flags);
 416
 417     /**
 418      * Map the entire data store of a buffer object into the client's address
 419      * space.
 420      *
 421      * \param buf       A winsys buffer object to map.
 422      * \param cs        A command stream to flush if the buffer is referenced by it.
 423      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 424      * \return          The pointer at the beginning of the buffer.
 425      */
 426     void *(*buffer_map)(struct pb_buffer *buf,
 427                         struct radeon_winsys_cs *cs,
 428                         enum pipe_transfer_usage usage);
 429
 430     /**
 431      * Unmap a buffer object from the client's address space.
 432      *
 433      * \param buf       A winsys buffer object to unmap.
 434      */
 435     void (*buffer_unmap)(struct pb_buffer *buf);
 436
 437     /**
 438      * Wait for the buffer and return true if the buffer is not used
 439      * by the device.
 440      *
 441      * The timeout of 0 will only return the status.
 442      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
 443      * is idle.
 444      */
 445     bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
 446                         enum radeon_bo_usage usage);
 447
 448     /**
 449      * Return buffer metadata.
 450      * (tiling info for display code, DRI sharing, and other data)
 451      *
 452      * \param buf       A winsys buffer object to get the flags from.
 453      * \param md        Metadata
 454      */
 455     void (*buffer_get_metadata)(struct pb_buffer *buf,
 456                                 struct radeon_bo_metadata *md);
 457
 458     /**
 459      * Set buffer metadata.
 460      * (tiling info for display code, DRI sharing, and other data)
 461      *
 462      * \param buf       A winsys buffer object to set the flags for.
 463      * \param md        Metadata
 464      */
 465     void (*buffer_set_metadata)(struct pb_buffer *buf,
 466                                 struct radeon_bo_metadata *md);
 467
 468     /**
 469      * Get a winsys buffer from a winsys handle. The internal structure
 470      * of the handle is platform-specific and only a winsys should access it.
 471      *
 472      * \param ws        The winsys this function is called from.
 473      * \param whandle   A winsys handle pointer as was received from a state
 474      *                  tracker.
 475      * \param stride    The returned buffer stride in bytes.
 476      */
 477     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 478                                             struct winsys_handle *whandle,
 479                                             unsigned *stride, unsigned *offset);
 480
 481     /**
 482      * Get a winsys buffer from a user pointer. The resulting buffer can't
 483      * be exported. Both pointer and size must be page aligned.
 484      *
 485      * \param ws        The winsys this function is called from.
 486      * \param pointer   User pointer to turn into a buffer object.
 487      * \param Size      Size in bytes for the new buffer.
 488      */
 489     struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
 490                                          void *pointer, uint64_t size);
 491
 492     /**
 493      * Whether the buffer was created from a user pointer.
 494      *
 495      * \param buf       A winsys buffer object
 496      * \return          whether \p buf was created via buffer_from_ptr
 497      */
 498     bool (*buffer_is_user_ptr)(struct pb_buffer *buf);
 499
 500     /**
 501      * Get a winsys handle from a winsys buffer. The internal structure
 502      * of the handle is platform-specific and only a winsys should access it.
 503      *
 504      * \param buf       A winsys buffer object to get the handle from.
 505      * \param whandle   A winsys handle pointer.
 506      * \param stride    A stride of the buffer in bytes, for texturing.
 507      * \return          true on success.
 508      */
 509     bool (*buffer_get_handle)(struct pb_buffer *buf,
 510                               unsigned stride, unsigned offset,
 511                               unsigned slice_size,
 512                               struct winsys_handle *whandle);
 513
 514     /**
 515      * Return the virtual address of a buffer.
 516      *
 517      * When virtual memory is not in use, this is the offset relative to the
 518      * relocation base (non-zero for sub-allocated buffers).
 519      *
 520      * \param buf       A winsys buffer object
 521      * \return          virtual address
 522      */
 523     uint64_t (*buffer_get_virtual_address)(struct pb_buffer *buf);
 524
 525     /**
 526      * Return the offset of this buffer relative to the relocation base.
 527      * This is only non-zero for sub-allocated buffers.
 528      *
 529      * This is only supported in the radeon winsys, since amdgpu uses virtual
 530      * addresses in submissions even for the video engines.
 531      *
 532      * \param buf      A winsys buffer object
 533      * \return         the offset for relocations
 534      */
 535     unsigned (*buffer_get_reloc_offset)(struct pb_buffer *buf);
 536
 537     /**
 538      * Query the initial placement of the buffer from the kernel driver.
 539      */
 540     enum radeon_bo_domain (*buffer_get_initial_domain)(struct pb_buffer *buf);
 541
 542     /**************************************************************************
 543      * Command submission.
 544      *
 545      * Each pipe context should create its own command stream and submit
 546      * commands independently of other contexts.
 547      *************************************************************************/
 548
 549     /**
 550      * Create a command submission context.
 551      * Various command streams can be submitted to the same context.
 552      */
 553     struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 554
 555     /**
 556      * Destroy a context.
 557      */
 558     void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 559
 560     /**
 561      * Query a GPU reset status.
 562      */
 563     enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
 564
 565     /**
 566      * Create a command stream.
 567      *
 568      * \param ctx       The submission context
 569      * \param ring_type The ring type (GFX, DMA, UVD)
 570      * \param flush     Flush callback function associated with the command stream.
 571      * \param user      User pointer that will be passed to the flush callback.
 572      */
 573     struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys_ctx *ctx,
 574                                           enum ring_type ring_type,
 575                                           void (*flush)(void *ctx, unsigned flags,
 576                                                         struct pipe_fence_handle **fence),
 577                                           void *flush_ctx);
 578
 579     /**
 580      * Add a constant engine IB to a graphics CS. This makes the graphics CS
 581      * from "cs_create" a group of two IBs that share a buffer list and are
 582      * flushed together.
 583      *
 584      * The returned constant CS is only a stream for writing packets to the new
 585      * IB. Calling other winsys functions with it is not allowed, not even
 586      * "cs_destroy".
 587      *
 588      * In order to add buffers and check memory usage, use the graphics CS.
 589      * In order to flush it, use the graphics CS, which will flush both IBs.
 590      * Destroying the graphics CS will destroy both of them.
 591      *
 592      * \param cs  The graphics CS from "cs_create" that will hold the buffer
 593      *            list and will be used for flushing.
 594      */
 595     struct radeon_winsys_cs *(*cs_add_const_ib)(struct radeon_winsys_cs *cs);
 596
 597      /**
 598      * Add a constant engine preamble IB to a graphics CS. This add an extra IB
 599      * in similar manner to cs_add_const_ib. This should always be called after
 600      * cs_add_const_ib.
 601      *
 602      * The returned IB is a constant engine IB that only gets flushed if the
 603      * context changed.
 604      *
 605      * \param cs  The graphics CS from "cs_create" that will hold the buffer
 606      *            list and will be used for flushing.
 607      */
 608     struct radeon_winsys_cs *(*cs_add_const_preamble_ib)(struct radeon_winsys_cs *cs);
 609     /**
 610      * Destroy a command stream.
 611      *
 612      * \param cs        A command stream to destroy.
 613      */
 614     void (*cs_destroy)(struct radeon_winsys_cs *cs);
 615
 616     /**
 617      * Add a buffer. Each buffer used by a CS must be added using this function.
 618      *
 619      * \param cs      Command stream
 620      * \param buf     Buffer
 621      * \param usage   Whether the buffer is used for read and/or write.
 622      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 623      * \param priority  A higher number means a greater chance of being
 624      *                  placed in the requested domain. 15 is the maximum.
 625      * \return Buffer index.
 626      */
 627     unsigned (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 628                              struct pb_buffer *buf,
 629                              enum radeon_bo_usage usage,
 630                              enum radeon_bo_domain domain,
 631                              enum radeon_bo_priority priority);
 632
 633     /**
 634      * Return the index of an already-added buffer.
 635      *
 636      * Not supported on amdgpu. Drivers with GPUVM should not care about
 637      * buffer indices.
 638      *
 639      * \param cs        Command stream
 640      * \param buf       Buffer
 641      * \return          The buffer index, or -1 if the buffer has not been added.
 642      */
 643     int (*cs_lookup_buffer)(struct radeon_winsys_cs *cs,
 644                             struct pb_buffer *buf);
 645
 646     /**
 647      * Return true if there is enough memory in VRAM and GTT for the buffers
 648      * added so far. If the validation fails, all buffers which have
 649      * been added since the last call of cs_validate will be removed and
 650      * the CS will be flushed (provided there are still any buffers).
 651      *
 652      * \param cs        A command stream to validate.
 653      */
 654     bool (*cs_validate)(struct radeon_winsys_cs *cs);
 655
 656     /**
 657      * Check whether the given number of dwords is available in the IB.
 658      * Optionally chain a new chunk of the IB if necessary and supported.
 659      *
 660      * \param cs        A command stream.
 661      * \param dw        Number of CS dwords requested by the caller.
 662      */
 663     bool (*cs_check_space)(struct radeon_winsys_cs *cs, unsigned dw);
 664
 665     /**
 666      * Return the buffer list.
 667      *
 668      * This is the buffer list as passed to the kernel, i.e. it only contains
 669      * the parent buffers of sub-allocated buffers.
 670      *
 671      * \param cs    Command stream
 672      * \param list  Returned buffer list. Set to NULL to query the count only.
 673      * \return      The buffer count.
 674      */
 675     unsigned (*cs_get_buffer_list)(struct radeon_winsys_cs *cs,
 676                                    struct radeon_bo_list_item *list);
 677
 678     /**
 679      * Flush a command stream.
 680      *
 681      * \param cs          A command stream to flush.
 682      * \param flags,      RADEON_FLUSH_ASYNC or 0.
 683      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 684      *                    after the CS and is returned through this parameter.
 685      * \return Negative POSIX error code or 0 for success.
 686      *         Asynchronous submissions never return an error.
 687      */
 688     int (*cs_flush)(struct radeon_winsys_cs *cs,
 689                     unsigned flags,
 690                     struct pipe_fence_handle **fence);
 691
 692     /**
 693      * Create a fence before the CS is flushed.
 694      * The user must flush manually to complete the initializaton of the fence.
 695      * The fence must not be used before the flush.
 696      */
 697     struct pipe_fence_handle *(*cs_get_next_fence)(struct radeon_winsys_cs *cs);
 698
 699     /**
 700      * Return true if a buffer is referenced by a command stream.
 701      *
 702      * \param cs        A command stream.
 703      * \param buf       A winsys buffer.
 704      */
 705     bool (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
 706                                     struct pb_buffer *buf,
 707                                     enum radeon_bo_usage usage);
 708
 709     /**
 710      * Request access to a feature for a command stream.
 711      *
 712      * \param cs        A command stream.
 713      * \param fid       Feature ID, one of RADEON_FID_*
 714      * \param enable    Whether to enable or disable the feature.
 715      */
 716     bool (*cs_request_feature)(struct radeon_winsys_cs *cs,
 717                                enum radeon_feature_id fid,
 718                                bool enable);
 719      /**
 720       * Make sure all asynchronous flush of the cs have completed
 721       *
 722       * \param cs        A command stream.
 723       */
 724     void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
 725
 726     /**
 727      * Wait for the fence and return true if the fence has been signalled.
 728      * The timeout of 0 will only return the status.
 729      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 730      * is signalled.
 731      */
 732     bool (*fence_wait)(struct radeon_winsys *ws,
 733                        struct pipe_fence_handle *fence,
 734                        uint64_t timeout);
 735
 736     /**
 737      * Reference counting for fences.
 738      */
 739     void (*fence_reference)(struct pipe_fence_handle **dst,
 740                             struct pipe_fence_handle *src);
 741
 742     /**
 743      * Initialize surface
 744      *
 745      * \param ws        The winsys this function is called from.
 746      * \param surf      Surface structure ptr
 747      */
 748     int (*surface_init)(struct radeon_winsys *ws,
 749                         struct radeon_surf *surf);
 750
 751     uint64_t (*query_value)(struct radeon_winsys *ws,
 752                             enum radeon_value_id value);
 753
 754     bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 755                            unsigned num_registers, uint32_t *out);
 756 };
 757
 758 static inline bool radeon_emitted(struct radeon_winsys_cs *cs, unsigned num_dw)
 759 {
 760     return cs && (cs->prev_dw + cs->current.cdw > num_dw);
 761 }
 762
 763 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 764 {
 765     cs->current.buf[cs->current.cdw++] = value;
 766 }
 767
 768 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 769                                      const uint32_t *values, unsigned count)
 770 {
 771     memcpy(cs->current.buf + cs->current.cdw, values, count * 4);
 772     cs->current.cdw += count;
 773 }
 774
 775 #endif