src/gallium/drivers/radeon/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #ifndef RADEON_WINSYS_H
  25 #define RADEON_WINSYS_H
  26
  27 /* The public winsys interface header for the radeon driver. */
  28
  29 #include "pipebuffer/pb_buffer.h"
  30
  31 #include "amd/common/amd_family.h"
  32
  33 #define RADEON_FLUSH_ASYNC              (1 << 0)
  34 #define RADEON_FLUSH_END_OF_FRAME       (1 << 1)
  35
  36 /* Tiling flags. */
  37 enum radeon_bo_layout {
  38     RADEON_LAYOUT_LINEAR = 0,
  39     RADEON_LAYOUT_TILED,
  40     RADEON_LAYOUT_SQUARETILED,
  41
  42     RADEON_LAYOUT_UNKNOWN
  43 };
  44
  45 enum radeon_bo_domain { /* bitfield */
  46     RADEON_DOMAIN_GTT  = 2,
  47     RADEON_DOMAIN_VRAM = 4,
  48     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  49 };
  50
  51 enum radeon_bo_flag { /* bitfield */
  52     RADEON_FLAG_GTT_WC =        (1 << 0),
  53     RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  54     RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  55     RADEON_FLAG_HANDLE =        (1 << 3), /* the buffer most not be suballocated */
  56 };
  57
  58 enum radeon_bo_usage { /* bitfield */
  59     RADEON_USAGE_READ = 2,
  60     RADEON_USAGE_WRITE = 4,
  61     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE,
  62
  63     /* The winsys ensures that the CS submission will be scheduled after
  64      * previously flushed CSs referencing this BO in a conflicting way.
  65      */
  66     RADEON_USAGE_SYNCHRONIZED = 8
  67 };
  68
  69 enum ring_type {
  70     RING_GFX = 0,
  71     RING_COMPUTE,
  72     RING_DMA,
  73     RING_UVD,
  74     RING_VCE,
  75     RING_LAST,
  76 };
  77
  78 enum radeon_value_id {
  79     RADEON_REQUESTED_VRAM_MEMORY,
  80     RADEON_REQUESTED_GTT_MEMORY,
  81     RADEON_MAPPED_VRAM,
  82     RADEON_MAPPED_GTT,
  83     RADEON_BUFFER_WAIT_TIME_NS,
  84     RADEON_NUM_MAPPED_BUFFERS,
  85     RADEON_TIMESTAMP,
  86     RADEON_NUM_GFX_IBS,
  87     RADEON_NUM_SDMA_IBS,
  88     RADEON_NUM_BYTES_MOVED,
  89     RADEON_NUM_EVICTIONS,
  90     RADEON_VRAM_USAGE,
  91     RADEON_VRAM_VIS_USAGE,
  92     RADEON_GTT_USAGE,
  93     RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
  94     RADEON_CURRENT_SCLK,
  95     RADEON_CURRENT_MCLK,
  96     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
  97     RADEON_CS_THREAD_TIME,
  98 };
  99
 100 /* Each group of four has the same priority. */
 101 enum radeon_bo_priority {
 102     RADEON_PRIO_FENCE = 0,
 103     RADEON_PRIO_TRACE,
 104     RADEON_PRIO_SO_FILLED_SIZE,
 105     RADEON_PRIO_QUERY,
 106
 107     RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
 108     RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
 109     RADEON_PRIO_DRAW_INDIRECT,
 110     RADEON_PRIO_INDEX_BUFFER,
 111
 112     RADEON_PRIO_VCE = 8,
 113     RADEON_PRIO_UVD,
 114     RADEON_PRIO_SDMA_BUFFER,
 115     RADEON_PRIO_SDMA_TEXTURE,
 116
 117     RADEON_PRIO_CP_DMA = 12,
 118
 119     RADEON_PRIO_CONST_BUFFER = 16,
 120     RADEON_PRIO_DESCRIPTORS,
 121     RADEON_PRIO_BORDER_COLORS,
 122
 123     RADEON_PRIO_SAMPLER_BUFFER = 20,
 124     RADEON_PRIO_VERTEX_BUFFER,
 125
 126     RADEON_PRIO_SHADER_RW_BUFFER = 24,
 127     RADEON_PRIO_COMPUTE_GLOBAL,
 128
 129     RADEON_PRIO_SAMPLER_TEXTURE = 28,
 130     RADEON_PRIO_SHADER_RW_IMAGE,
 131
 132     RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 32,
 133
 134     RADEON_PRIO_COLOR_BUFFER = 36,
 135
 136     RADEON_PRIO_DEPTH_BUFFER = 40,
 137
 138     RADEON_PRIO_COLOR_BUFFER_MSAA = 44,
 139
 140     RADEON_PRIO_DEPTH_BUFFER_MSAA = 48,
 141
 142     RADEON_PRIO_CMASK = 52,
 143     RADEON_PRIO_DCC,
 144     RADEON_PRIO_HTILE,
 145     RADEON_PRIO_SHADER_BINARY, /* the hw can't hide instruction cache misses */
 146
 147     RADEON_PRIO_SHADER_RINGS = 56,
 148
 149     RADEON_PRIO_SCRATCH_BUFFER = 60,
 150     /* 63 is the maximum value */
 151 };
 152
 153 struct winsys_handle;
 154 struct radeon_winsys_ctx;
 155
 156 struct radeon_winsys_cs_chunk {
 157     unsigned cdw;  /* Number of used dwords. */
 158     unsigned max_dw; /* Maximum number of dwords. */
 159     uint32_t *buf; /* The base pointer of the chunk. */
 160 };
 161
 162 struct radeon_winsys_cs {
 163     struct radeon_winsys_cs_chunk current;
 164     struct radeon_winsys_cs_chunk *prev;
 165     unsigned                      num_prev; /* Number of previous chunks. */
 166     unsigned                      max_prev; /* Space in array pointed to by prev. */
 167     unsigned                      prev_dw; /* Total number of dwords in previous chunks. */
 168
 169     /* Memory usage of the buffer list. These are always 0 for CE and preamble
 170      * IBs. */
 171     uint64_t                      used_vram;
 172     uint64_t                      used_gart;
 173 };
 174
 175 struct radeon_info {
 176     /* PCI info: domain:bus:dev:func */
 177     uint32_t                    pci_domain;
 178     uint32_t                    pci_bus;
 179     uint32_t                    pci_dev;
 180     uint32_t                    pci_func;
 181
 182     /* Device info. */
 183     uint32_t                    pci_id;
 184     enum radeon_family          family;
 185     enum chip_class             chip_class;
 186     uint32_t                    gart_page_size;
 187     uint64_t                    gart_size;
 188     uint64_t                    vram_size;
 189     uint64_t                    vram_vis_size;
 190     uint64_t                    max_alloc_size;
 191     uint32_t                    min_alloc_size;
 192     bool                        has_dedicated_vram;
 193     bool                        has_virtual_memory;
 194     bool                        gfx_ib_pad_with_type2;
 195     bool                        has_sdma;
 196     bool                        has_uvd;
 197     uint32_t                    uvd_fw_version;
 198     uint32_t                    vce_fw_version;
 199     uint32_t                    me_fw_version;
 200     uint32_t                    pfp_fw_version;
 201     uint32_t                    ce_fw_version;
 202     uint32_t                    vce_harvest_config;
 203     uint32_t                    clock_crystal_freq;
 204
 205     /* Kernel info. */
 206     uint32_t                    drm_major; /* version */
 207     uint32_t                    drm_minor;
 208     uint32_t                    drm_patchlevel;
 209     bool                        has_userptr;
 210
 211     /* Shader cores. */
 212     uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
 213     uint32_t                    max_shader_clock;
 214     uint32_t                    num_good_compute_units;
 215     uint32_t                    max_se; /* shader engines */
 216     uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 217
 218     /* Render backends (color + depth blocks). */
 219     uint32_t                    r300_num_gb_pipes;
 220     uint32_t                    r300_num_z_pipes;
 221     uint32_t                    r600_gb_backend_map; /* R600 harvest config */
 222     bool                        r600_gb_backend_map_valid;
 223     uint32_t                    r600_num_banks;
 224     uint32_t                    num_render_backends;
 225     uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
 226     uint32_t                    pipe_interleave_bytes;
 227     uint32_t                    enabled_rb_mask; /* GCN harvest config */
 228
 229     /* Tile modes. */
 230     uint32_t                    si_tile_mode_array[32];
 231     uint32_t                    cik_macrotile_mode_array[16];
 232 };
 233
 234 /* Tiling info for display code, DRI sharing, and other data. */
 235 struct radeon_bo_metadata {
 236     /* Tiling flags describing the texture layout for display code
 237      * and DRI sharing.
 238      */
 239     enum radeon_bo_layout   microtile;
 240     enum radeon_bo_layout   macrotile;
 241     unsigned                pipe_config;
 242     unsigned                bankw;
 243     unsigned                bankh;
 244     unsigned                tile_split;
 245     unsigned                mtilea;
 246     unsigned                num_banks;
 247     unsigned                stride;
 248     bool                    scanout;
 249
 250     /* Additional metadata associated with the buffer, in bytes.
 251      * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 252      * Supported by amdgpu only.
 253      */
 254     uint32_t                size_metadata;
 255     uint32_t                metadata[64];
 256 };
 257
 258 enum radeon_feature_id {
 259     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 260     RADEON_FID_R300_CMASK_ACCESS,
 261 };
 262
 263 #define RADEON_SURF_MAX_LEVELS                  15
 264
 265 enum radeon_surf_mode {
 266     RADEON_SURF_MODE_LINEAR_ALIGNED = 1,
 267     RADEON_SURF_MODE_1D = 2,
 268     RADEON_SURF_MODE_2D = 3,
 269 };
 270
 271 /* These are defined exactly like GB_TILE_MODEn.MICRO_TILE_MODE_NEW. */
 272 enum radeon_micro_mode {
 273     RADEON_MICRO_MODE_DISPLAY = 0,
 274     RADEON_MICRO_MODE_THIN = 1,
 275     RADEON_MICRO_MODE_DEPTH = 2,
 276     RADEON_MICRO_MODE_ROTATED = 3,
 277 };
 278
 279 /* the first 16 bits are reserved for libdrm_radeon, don't use them */
 280 #define RADEON_SURF_SCANOUT                     (1 << 16)
 281 #define RADEON_SURF_ZBUFFER                     (1 << 17)
 282 #define RADEON_SURF_SBUFFER                     (1 << 18)
 283 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
 284 /* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
 285 #define RADEON_SURF_FMASK                       (1 << 21)
 286 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
 287 #define RADEON_SURF_TC_COMPATIBLE_HTILE         (1 << 23)
 288 #define RADEON_SURF_IMPORTED                    (1 << 24)
 289 #define RADEON_SURF_OPTIMIZE_FOR_SPACE          (1 << 25)
 290
 291 struct radeon_surf_level {
 292     uint64_t                    offset;
 293     uint64_t                    slice_size;
 294     uint64_t                    dcc_offset;
 295     uint64_t                    dcc_fast_clear_size;
 296     uint16_t                    nblk_x;
 297     uint16_t                    nblk_y;
 298     enum radeon_surf_mode       mode;
 299 };
 300
 301 struct radeon_surf {
 302     /* Format properties. */
 303     unsigned                    blk_w:4;
 304     unsigned                    blk_h:4;
 305     unsigned                    bpe:5;
 306     /* Number of mipmap levels where DCC is enabled starting from level 0.
 307      * Non-zero levels may be disabled due to alignment constraints, but not
 308      * the first level.
 309      */
 310     unsigned                    num_dcc_levels:4;
 311     unsigned                    is_linear:1;
 312     uint32_t                    flags;
 313
 314     /* These are return values. Some of them can be set by the caller, but
 315      * they will be treated as hints (e.g. bankw, bankh) and might be
 316      * changed by the calculator.
 317      */
 318     uint64_t                    surf_size;
 319     uint64_t                    dcc_size;
 320     uint64_t                    htile_size;
 321
 322     uint32_t                    surf_alignment;
 323     uint32_t                    dcc_alignment;
 324     uint32_t                    htile_alignment;
 325
 326     /* This applies to EG and later. */
 327     unsigned                    bankw:4;  /* max 8 */
 328     unsigned                    bankh:4;  /* max 8 */
 329     unsigned                    mtilea:4; /* max 8 */
 330     unsigned                    tile_split:13;         /* max 4K */
 331     unsigned                    stencil_tile_split:13; /* max 4K */
 332     unsigned                    pipe_config:5;      /* max 17 */
 333     unsigned                    num_banks:5;        /* max 16 */
 334     unsigned                    macro_tile_index:4; /* max 15 */
 335     unsigned                    micro_tile_mode:3; /* displayable, thin, depth, rotated */
 336
 337     /* Whether the depth miptree or stencil miptree as used by the DB are
 338      * adjusted from their TC compatible form to ensure depth/stencil
 339      * compatibility. If either is true, the corresponding plane cannot be
 340      * sampled from.
 341      */
 342     unsigned                    depth_adjusted:1;
 343     unsigned                    stencil_adjusted:1;
 344
 345     struct radeon_surf_level    level[RADEON_SURF_MAX_LEVELS];
 346     struct radeon_surf_level    stencil_level[RADEON_SURF_MAX_LEVELS];
 347     uint8_t                     tiling_index[RADEON_SURF_MAX_LEVELS];
 348     uint8_t                     stencil_tiling_index[RADEON_SURF_MAX_LEVELS];
 349 };
 350
 351 struct radeon_bo_list_item {
 352     uint64_t bo_size;
 353     uint64_t vm_address;
 354     uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
 355 };
 356
 357 struct radeon_winsys {
 358     /**
 359      * The screen object this winsys was created for
 360      */
 361     struct pipe_screen *screen;
 362
 363     /**
 364      * Decrement the winsys reference count.
 365      *
 366      * \param ws  The winsys this function is called for.
 367      * \return    True if the winsys and screen should be destroyed.
 368      */
 369     bool (*unref)(struct radeon_winsys *ws);
 370
 371     /**
 372      * Destroy this winsys.
 373      *
 374      * \param ws        The winsys this function is called from.
 375      */
 376     void (*destroy)(struct radeon_winsys *ws);
 377
 378     /**
 379      * Query an info structure from winsys.
 380      *
 381      * \param ws        The winsys this function is called from.
 382      * \param info      Return structure
 383      */
 384     void (*query_info)(struct radeon_winsys *ws,
 385                        struct radeon_info *info);
 386
 387     /**************************************************************************
 388      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 389      *
 390      * Remember that gallium gets to choose the interface it needs, and the
 391      * window systems must then implement that interface (rather than the
 392      * other way around...).
 393      *************************************************************************/
 394
 395     /**
 396      * Create a buffer object.
 397      *
 398      * \param ws        The winsys this function is called from.
 399      * \param size      The size to allocate.
 400      * \param alignment An alignment of the buffer in memory.
 401      * \param use_reusable_pool Whether the cache buffer manager should be used.
 402      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 403      * \return          The created buffer object.
 404      */
 405     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 406                                        uint64_t size,
 407                                        unsigned alignment,
 408                                        enum radeon_bo_domain domain,
 409                                        enum radeon_bo_flag flags);
 410
 411     /**
 412      * Map the entire data store of a buffer object into the client's address
 413      * space.
 414      *
 415      * \param buf       A winsys buffer object to map.
 416      * \param cs        A command stream to flush if the buffer is referenced by it.
 417      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 418      * \return          The pointer at the beginning of the buffer.
 419      */
 420     void *(*buffer_map)(struct pb_buffer *buf,
 421                         struct radeon_winsys_cs *cs,
 422                         enum pipe_transfer_usage usage);
 423
 424     /**
 425      * Unmap a buffer object from the client's address space.
 426      *
 427      * \param buf       A winsys buffer object to unmap.
 428      */
 429     void (*buffer_unmap)(struct pb_buffer *buf);
 430
 431     /**
 432      * Wait for the buffer and return true if the buffer is not used
 433      * by the device.
 434      *
 435      * The timeout of 0 will only return the status.
 436      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
 437      * is idle.
 438      */
 439     bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
 440                         enum radeon_bo_usage usage);
 441
 442     /**
 443      * Return buffer metadata.
 444      * (tiling info for display code, DRI sharing, and other data)
 445      *
 446      * \param buf       A winsys buffer object to get the flags from.
 447      * \param md        Metadata
 448      */
 449     void (*buffer_get_metadata)(struct pb_buffer *buf,
 450                                 struct radeon_bo_metadata *md);
 451
 452     /**
 453      * Set buffer metadata.
 454      * (tiling info for display code, DRI sharing, and other data)
 455      *
 456      * \param buf       A winsys buffer object to set the flags for.
 457      * \param md        Metadata
 458      */
 459     void (*buffer_set_metadata)(struct pb_buffer *buf,
 460                                 struct radeon_bo_metadata *md);
 461
 462     /**
 463      * Get a winsys buffer from a winsys handle. The internal structure
 464      * of the handle is platform-specific and only a winsys should access it.
 465      *
 466      * \param ws        The winsys this function is called from.
 467      * \param whandle   A winsys handle pointer as was received from a state
 468      *                  tracker.
 469      * \param stride    The returned buffer stride in bytes.
 470      */
 471     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 472                                             struct winsys_handle *whandle,
 473                                             unsigned *stride, unsigned *offset);
 474
 475     /**
 476      * Get a winsys buffer from a user pointer. The resulting buffer can't
 477      * be exported. Both pointer and size must be page aligned.
 478      *
 479      * \param ws        The winsys this function is called from.
 480      * \param pointer   User pointer to turn into a buffer object.
 481      * \param Size      Size in bytes for the new buffer.
 482      */
 483     struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
 484                                          void *pointer, uint64_t size);
 485
 486     /**
 487      * Whether the buffer was created from a user pointer.
 488      *
 489      * \param buf       A winsys buffer object
 490      * \return          whether \p buf was created via buffer_from_ptr
 491      */
 492     bool (*buffer_is_user_ptr)(struct pb_buffer *buf);
 493
 494     /**
 495      * Get a winsys handle from a winsys buffer. The internal structure
 496      * of the handle is platform-specific and only a winsys should access it.
 497      *
 498      * \param buf       A winsys buffer object to get the handle from.
 499      * \param whandle   A winsys handle pointer.
 500      * \param stride    A stride of the buffer in bytes, for texturing.
 501      * \return          true on success.
 502      */
 503     bool (*buffer_get_handle)(struct pb_buffer *buf,
 504                               unsigned stride, unsigned offset,
 505                               unsigned slice_size,
 506                               struct winsys_handle *whandle);
 507
 508     /**
 509      * Return the virtual address of a buffer.
 510      *
 511      * When virtual memory is not in use, this is the offset relative to the
 512      * relocation base (non-zero for sub-allocated buffers).
 513      *
 514      * \param buf       A winsys buffer object
 515      * \return          virtual address
 516      */
 517     uint64_t (*buffer_get_virtual_address)(struct pb_buffer *buf);
 518
 519     /**
 520      * Return the offset of this buffer relative to the relocation base.
 521      * This is only non-zero for sub-allocated buffers.
 522      *
 523      * This is only supported in the radeon winsys, since amdgpu uses virtual
 524      * addresses in submissions even for the video engines.
 525      *
 526      * \param buf      A winsys buffer object
 527      * \return         the offset for relocations
 528      */
 529     unsigned (*buffer_get_reloc_offset)(struct pb_buffer *buf);
 530
 531     /**
 532      * Query the initial placement of the buffer from the kernel driver.
 533      */
 534     enum radeon_bo_domain (*buffer_get_initial_domain)(struct pb_buffer *buf);
 535
 536     /**************************************************************************
 537      * Command submission.
 538      *
 539      * Each pipe context should create its own command stream and submit
 540      * commands independently of other contexts.
 541      *************************************************************************/
 542
 543     /**
 544      * Create a command submission context.
 545      * Various command streams can be submitted to the same context.
 546      */
 547     struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 548
 549     /**
 550      * Destroy a context.
 551      */
 552     void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 553
 554     /**
 555      * Query a GPU reset status.
 556      */
 557     enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
 558
 559     /**
 560      * Create a command stream.
 561      *
 562      * \param ctx       The submission context
 563      * \param ring_type The ring type (GFX, DMA, UVD)
 564      * \param flush     Flush callback function associated with the command stream.
 565      * \param user      User pointer that will be passed to the flush callback.
 566      */
 567     struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys_ctx *ctx,
 568                                           enum ring_type ring_type,
 569                                           void (*flush)(void *ctx, unsigned flags,
 570                                                         struct pipe_fence_handle **fence),
 571                                           void *flush_ctx);
 572
 573     /**
 574      * Add a constant engine IB to a graphics CS. This makes the graphics CS
 575      * from "cs_create" a group of two IBs that share a buffer list and are
 576      * flushed together.
 577      *
 578      * The returned constant CS is only a stream for writing packets to the new
 579      * IB. Calling other winsys functions with it is not allowed, not even
 580      * "cs_destroy".
 581      *
 582      * In order to add buffers and check memory usage, use the graphics CS.
 583      * In order to flush it, use the graphics CS, which will flush both IBs.
 584      * Destroying the graphics CS will destroy both of them.
 585      *
 586      * \param cs  The graphics CS from "cs_create" that will hold the buffer
 587      *            list and will be used for flushing.
 588      */
 589     struct radeon_winsys_cs *(*cs_add_const_ib)(struct radeon_winsys_cs *cs);
 590
 591      /**
 592      * Add a constant engine preamble IB to a graphics CS. This add an extra IB
 593      * in similar manner to cs_add_const_ib. This should always be called after
 594      * cs_add_const_ib.
 595      *
 596      * The returned IB is a constant engine IB that only gets flushed if the
 597      * context changed.
 598      *
 599      * \param cs  The graphics CS from "cs_create" that will hold the buffer
 600      *            list and will be used for flushing.
 601      */
 602     struct radeon_winsys_cs *(*cs_add_const_preamble_ib)(struct radeon_winsys_cs *cs);
 603     /**
 604      * Destroy a command stream.
 605      *
 606      * \param cs        A command stream to destroy.
 607      */
 608     void (*cs_destroy)(struct radeon_winsys_cs *cs);
 609
 610     /**
 611      * Add a buffer. Each buffer used by a CS must be added using this function.
 612      *
 613      * \param cs      Command stream
 614      * \param buf     Buffer
 615      * \param usage   Whether the buffer is used for read and/or write.
 616      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 617      * \param priority  A higher number means a greater chance of being
 618      *                  placed in the requested domain. 15 is the maximum.
 619      * \return Buffer index.
 620      */
 621     unsigned (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 622                              struct pb_buffer *buf,
 623                              enum radeon_bo_usage usage,
 624                              enum radeon_bo_domain domain,
 625                              enum radeon_bo_priority priority);
 626
 627     /**
 628      * Return the index of an already-added buffer.
 629      *
 630      * Not supported on amdgpu. Drivers with GPUVM should not care about
 631      * buffer indices.
 632      *
 633      * \param cs        Command stream
 634      * \param buf       Buffer
 635      * \return          The buffer index, or -1 if the buffer has not been added.
 636      */
 637     int (*cs_lookup_buffer)(struct radeon_winsys_cs *cs,
 638                             struct pb_buffer *buf);
 639
 640     /**
 641      * Return true if there is enough memory in VRAM and GTT for the buffers
 642      * added so far. If the validation fails, all buffers which have
 643      * been added since the last call of cs_validate will be removed and
 644      * the CS will be flushed (provided there are still any buffers).
 645      *
 646      * \param cs        A command stream to validate.
 647      */
 648     bool (*cs_validate)(struct radeon_winsys_cs *cs);
 649
 650     /**
 651      * Check whether the given number of dwords is available in the IB.
 652      * Optionally chain a new chunk of the IB if necessary and supported.
 653      *
 654      * \param cs        A command stream.
 655      * \param dw        Number of CS dwords requested by the caller.
 656      */
 657     bool (*cs_check_space)(struct radeon_winsys_cs *cs, unsigned dw);
 658
 659     /**
 660      * Return the buffer list.
 661      *
 662      * This is the buffer list as passed to the kernel, i.e. it only contains
 663      * the parent buffers of sub-allocated buffers.
 664      *
 665      * \param cs    Command stream
 666      * \param list  Returned buffer list. Set to NULL to query the count only.
 667      * \return      The buffer count.
 668      */
 669     unsigned (*cs_get_buffer_list)(struct radeon_winsys_cs *cs,
 670                                    struct radeon_bo_list_item *list);
 671
 672     /**
 673      * Flush a command stream.
 674      *
 675      * \param cs          A command stream to flush.
 676      * \param flags,      RADEON_FLUSH_ASYNC or 0.
 677      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 678      *                    after the CS and is returned through this parameter.
 679      * \return Negative POSIX error code or 0 for success.
 680      *         Asynchronous submissions never return an error.
 681      */
 682     int (*cs_flush)(struct radeon_winsys_cs *cs,
 683                     unsigned flags,
 684                     struct pipe_fence_handle **fence);
 685
 686     /**
 687      * Create a fence before the CS is flushed.
 688      * The user must flush manually to complete the initializaton of the fence.
 689      * The fence must not be used before the flush.
 690      */
 691     struct pipe_fence_handle *(*cs_get_next_fence)(struct radeon_winsys_cs *cs);
 692
 693     /**
 694      * Return true if a buffer is referenced by a command stream.
 695      *
 696      * \param cs        A command stream.
 697      * \param buf       A winsys buffer.
 698      */
 699     bool (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
 700                                     struct pb_buffer *buf,
 701                                     enum radeon_bo_usage usage);
 702
 703     /**
 704      * Request access to a feature for a command stream.
 705      *
 706      * \param cs        A command stream.
 707      * \param fid       Feature ID, one of RADEON_FID_*
 708      * \param enable    Whether to enable or disable the feature.
 709      */
 710     bool (*cs_request_feature)(struct radeon_winsys_cs *cs,
 711                                enum radeon_feature_id fid,
 712                                bool enable);
 713      /**
 714       * Make sure all asynchronous flush of the cs have completed
 715       *
 716       * \param cs        A command stream.
 717       */
 718     void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
 719
 720     /**
 721      * Wait for the fence and return true if the fence has been signalled.
 722      * The timeout of 0 will only return the status.
 723      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 724      * is signalled.
 725      */
 726     bool (*fence_wait)(struct radeon_winsys *ws,
 727                        struct pipe_fence_handle *fence,
 728                        uint64_t timeout);
 729
 730     /**
 731      * Reference counting for fences.
 732      */
 733     void (*fence_reference)(struct pipe_fence_handle **dst,
 734                             struct pipe_fence_handle *src);
 735
 736     /**
 737      * Initialize surface
 738      *
 739      * \param ws        The winsys this function is called from.
 740      * \param tex       Input texture description
 741      * \param flags     Bitmask of RADEON_SURF_* flags
 742      * \param bpe       Bytes per pixel, it can be different for Z buffers.
 743      * \param mode      Preferred tile mode. (linear, 1D, or 2D)
 744      * \param surf      Output structure
 745      */
 746     int (*surface_init)(struct radeon_winsys *ws,
 747                         const struct pipe_resource *tex,
 748                         unsigned flags, unsigned bpe,
 749                         enum radeon_surf_mode mode,
 750                         struct radeon_surf *surf);
 751
 752     uint64_t (*query_value)(struct radeon_winsys *ws,
 753                             enum radeon_value_id value);
 754
 755     bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 756                            unsigned num_registers, uint32_t *out);
 757 };
 758
 759 static inline bool radeon_emitted(struct radeon_winsys_cs *cs, unsigned num_dw)
 760 {
 761     return cs && (cs->prev_dw + cs->current.cdw > num_dw);
 762 }
 763
 764 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 765 {
 766     cs->current.buf[cs->current.cdw++] = value;
 767 }
 768
 769 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 770                                      const uint32_t *values, unsigned count)
 771 {
 772     memcpy(cs->current.buf + cs->current.cdw, values, count * 4);
 773     cs->current.cdw += count;
 774 }
 775
 776 #endif