src/gallium/drivers/radeon/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #ifndef RADEON_WINSYS_H
  25 #define RADEON_WINSYS_H
  26
  27 /* The public winsys interface header for the radeon driver. */
  28
  29 #include "pipebuffer/pb_buffer.h"
  30
  31 #include "amd/common/amd_family.h"
  32
  33 #define RADEON_FLUSH_ASYNC              (1 << 0)
  34 #define RADEON_FLUSH_END_OF_FRAME       (1 << 1)
  35
  36 /* Tiling flags. */
  37 enum radeon_bo_layout {
  38     RADEON_LAYOUT_LINEAR = 0,
  39     RADEON_LAYOUT_TILED,
  40     RADEON_LAYOUT_SQUARETILED,
  41
  42     RADEON_LAYOUT_UNKNOWN
  43 };
  44
  45 enum radeon_bo_domain { /* bitfield */
  46     RADEON_DOMAIN_GTT  = 2,
  47     RADEON_DOMAIN_VRAM = 4,
  48     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  49 };
  50
  51 enum radeon_bo_flag { /* bitfield */
  52     RADEON_FLAG_GTT_WC =        (1 << 0),
  53     RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  54     RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  55     RADEON_FLAG_HANDLE =        (1 << 3), /* the buffer most not be suballocated */
  56 };
  57
  58 enum radeon_bo_usage { /* bitfield */
  59     RADEON_USAGE_READ = 2,
  60     RADEON_USAGE_WRITE = 4,
  61     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE,
  62
  63     /* The winsys ensures that the CS submission will be scheduled after
  64      * previously flushed CSs referencing this BO in a conflicting way.
  65      */
  66     RADEON_USAGE_SYNCHRONIZED = 8
  67 };
  68
  69 enum ring_type {
  70     RING_GFX = 0,
  71     RING_COMPUTE,
  72     RING_DMA,
  73     RING_UVD,
  74     RING_VCE,
  75     RING_LAST,
  76 };
  77
  78 enum radeon_value_id {
  79     RADEON_REQUESTED_VRAM_MEMORY,
  80     RADEON_REQUESTED_GTT_MEMORY,
  81     RADEON_MAPPED_VRAM,
  82     RADEON_MAPPED_GTT,
  83     RADEON_BUFFER_WAIT_TIME_NS,
  84     RADEON_TIMESTAMP,
  85     RADEON_NUM_CS_FLUSHES,
  86     RADEON_NUM_BYTES_MOVED,
  87     RADEON_NUM_EVICTIONS,
  88     RADEON_VRAM_USAGE,
  89     RADEON_GTT_USAGE,
  90     RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
  91     RADEON_CURRENT_SCLK,
  92     RADEON_CURRENT_MCLK,
  93     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
  94 };
  95
  96 /* Each group of four has the same priority. */
  97 enum radeon_bo_priority {
  98     RADEON_PRIO_FENCE = 0,
  99     RADEON_PRIO_TRACE,
 100     RADEON_PRIO_SO_FILLED_SIZE,
 101     RADEON_PRIO_QUERY,
 102
 103     RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
 104     RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
 105     RADEON_PRIO_DRAW_INDIRECT,
 106     RADEON_PRIO_INDEX_BUFFER,
 107
 108     RADEON_PRIO_VCE = 8,
 109     RADEON_PRIO_UVD,
 110     RADEON_PRIO_SDMA_BUFFER,
 111     RADEON_PRIO_SDMA_TEXTURE,
 112
 113     RADEON_PRIO_CP_DMA = 12,
 114
 115     RADEON_PRIO_CONST_BUFFER = 16,
 116     RADEON_PRIO_DESCRIPTORS,
 117     RADEON_PRIO_BORDER_COLORS,
 118
 119     RADEON_PRIO_SAMPLER_BUFFER = 20,
 120     RADEON_PRIO_VERTEX_BUFFER,
 121
 122     RADEON_PRIO_SHADER_RW_BUFFER = 24,
 123     RADEON_PRIO_COMPUTE_GLOBAL,
 124
 125     RADEON_PRIO_SAMPLER_TEXTURE = 28,
 126     RADEON_PRIO_SHADER_RW_IMAGE,
 127
 128     RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 32,
 129
 130     RADEON_PRIO_COLOR_BUFFER = 36,
 131
 132     RADEON_PRIO_DEPTH_BUFFER = 40,
 133
 134     RADEON_PRIO_COLOR_BUFFER_MSAA = 44,
 135
 136     RADEON_PRIO_DEPTH_BUFFER_MSAA = 48,
 137
 138     RADEON_PRIO_CMASK = 52,
 139     RADEON_PRIO_DCC,
 140     RADEON_PRIO_HTILE,
 141     RADEON_PRIO_SHADER_BINARY, /* the hw can't hide instruction cache misses */
 142
 143     RADEON_PRIO_SHADER_RINGS = 56,
 144
 145     RADEON_PRIO_SCRATCH_BUFFER = 60,
 146     /* 63 is the maximum value */
 147 };
 148
 149 struct winsys_handle;
 150 struct radeon_winsys_ctx;
 151
 152 struct radeon_winsys_cs_chunk {
 153     unsigned cdw;  /* Number of used dwords. */
 154     unsigned max_dw; /* Maximum number of dwords. */
 155     uint32_t *buf; /* The base pointer of the chunk. */
 156 };
 157
 158 struct radeon_winsys_cs {
 159     struct radeon_winsys_cs_chunk current;
 160     struct radeon_winsys_cs_chunk *prev;
 161     unsigned                      num_prev; /* Number of previous chunks. */
 162     unsigned                      max_prev; /* Space in array pointed to by prev. */
 163     unsigned                      prev_dw; /* Total number of dwords in previous chunks. */
 164
 165     /* Memory usage of the buffer list. These are always 0 for CE and preamble
 166      * IBs. */
 167     uint64_t                      used_vram;
 168     uint64_t                      used_gart;
 169 };
 170
 171 struct radeon_info {
 172     /* PCI info: domain:bus:dev:func */
 173     uint32_t                    pci_domain;
 174     uint32_t                    pci_bus;
 175     uint32_t                    pci_dev;
 176     uint32_t                    pci_func;
 177
 178     /* Device info. */
 179     uint32_t                    pci_id;
 180     enum radeon_family          family;
 181     enum chip_class             chip_class;
 182     uint32_t                    gart_page_size;
 183     uint64_t                    gart_size;
 184     uint64_t                    vram_size;
 185     uint64_t                    max_alloc_size;
 186     uint32_t                    min_alloc_size;
 187     bool                        has_dedicated_vram;
 188     bool                        has_virtual_memory;
 189     bool                        gfx_ib_pad_with_type2;
 190     bool                        has_sdma;
 191     bool                        has_uvd;
 192     uint32_t                    uvd_fw_version;
 193     uint32_t                    vce_fw_version;
 194     uint32_t                    me_fw_version;
 195     uint32_t                    pfp_fw_version;
 196     uint32_t                    ce_fw_version;
 197     uint32_t                    vce_harvest_config;
 198     uint32_t                    clock_crystal_freq;
 199
 200     /* Kernel info. */
 201     uint32_t                    drm_major; /* version */
 202     uint32_t                    drm_minor;
 203     uint32_t                    drm_patchlevel;
 204     bool                        has_userptr;
 205
 206     /* Shader cores. */
 207     uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
 208     uint32_t                    max_shader_clock;
 209     uint32_t                    num_good_compute_units;
 210     uint32_t                    max_se; /* shader engines */
 211     uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 212
 213     /* Render backends (color + depth blocks). */
 214     uint32_t                    r300_num_gb_pipes;
 215     uint32_t                    r300_num_z_pipes;
 216     uint32_t                    r600_gb_backend_map; /* R600 harvest config */
 217     bool                        r600_gb_backend_map_valid;
 218     uint32_t                    r600_num_banks;
 219     uint32_t                    num_render_backends;
 220     uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
 221     uint32_t                    pipe_interleave_bytes;
 222     uint32_t                    enabled_rb_mask; /* GCN harvest config */
 223
 224     /* Tile modes. */
 225     uint32_t                    si_tile_mode_array[32];
 226     uint32_t                    cik_macrotile_mode_array[16];
 227 };
 228
 229 /* Tiling info for display code, DRI sharing, and other data. */
 230 struct radeon_bo_metadata {
 231     /* Tiling flags describing the texture layout for display code
 232      * and DRI sharing.
 233      */
 234     enum radeon_bo_layout   microtile;
 235     enum radeon_bo_layout   macrotile;
 236     unsigned                pipe_config;
 237     unsigned                bankw;
 238     unsigned                bankh;
 239     unsigned                tile_split;
 240     unsigned                mtilea;
 241     unsigned                num_banks;
 242     unsigned                stride;
 243     bool                    scanout;
 244
 245     /* Additional metadata associated with the buffer, in bytes.
 246      * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 247      * Supported by amdgpu only.
 248      */
 249     uint32_t                size_metadata;
 250     uint32_t                metadata[64];
 251 };
 252
 253 enum radeon_feature_id {
 254     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 255     RADEON_FID_R300_CMASK_ACCESS,
 256 };
 257
 258 #define RADEON_SURF_MAX_LEVEL                   32
 259
 260 #define RADEON_SURF_TYPE_MASK                   0xFF
 261 #define RADEON_SURF_TYPE_SHIFT                  0
 262 #define     RADEON_SURF_TYPE_1D                     0
 263 #define     RADEON_SURF_TYPE_2D                     1
 264 #define     RADEON_SURF_TYPE_3D                     2
 265 #define     RADEON_SURF_TYPE_CUBEMAP                3
 266 #define     RADEON_SURF_TYPE_1D_ARRAY               4
 267 #define     RADEON_SURF_TYPE_2D_ARRAY               5
 268 #define RADEON_SURF_MODE_MASK                   0xFF
 269 #define RADEON_SURF_MODE_SHIFT                  8
 270 #define     RADEON_SURF_MODE_LINEAR_ALIGNED         1
 271 #define     RADEON_SURF_MODE_1D                     2
 272 #define     RADEON_SURF_MODE_2D                     3
 273 #define RADEON_SURF_SCANOUT                     (1 << 16)
 274 #define RADEON_SURF_ZBUFFER                     (1 << 17)
 275 #define RADEON_SURF_SBUFFER                     (1 << 18)
 276 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
 277 #define RADEON_SURF_HAS_SBUFFER_MIPTREE         (1 << 19)
 278 #define RADEON_SURF_HAS_TILE_MODE_INDEX         (1 << 20)
 279 #define RADEON_SURF_FMASK                       (1 << 21)
 280 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
 281 #define RADEON_SURF_TC_COMPATIBLE_HTILE         (1 << 23)
 282
 283 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
 284 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
 285 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
 286
 287 struct radeon_surf_level {
 288     uint64_t                    offset;
 289     uint64_t                    slice_size;
 290     uint32_t                    npix_x;
 291     uint32_t                    npix_y;
 292     uint32_t                    npix_z;
 293     uint32_t                    nblk_x;
 294     uint32_t                    nblk_y;
 295     uint32_t                    nblk_z;
 296     uint32_t                    pitch_bytes;
 297     uint32_t                    mode;
 298     uint64_t                    dcc_offset;
 299     uint64_t                    dcc_fast_clear_size;
 300     bool                        dcc_enabled;
 301 };
 302
 303 struct radeon_surf {
 304     /* These are inputs to the calculator. */
 305     uint32_t                    npix_x;
 306     uint32_t                    npix_y;
 307     uint32_t                    npix_z;
 308     uint32_t                    blk_w;
 309     uint32_t                    blk_h;
 310     uint32_t                    blk_d;
 311     uint32_t                    array_size;
 312     uint32_t                    last_level;
 313     uint32_t                    bpe;
 314     uint32_t                    nsamples;
 315     uint32_t                    flags;
 316
 317     /* These are return values. Some of them can be set by the caller, but
 318      * they will be treated as hints (e.g. bankw, bankh) and might be
 319      * changed by the calculator.
 320      */
 321     uint64_t                    bo_size;
 322     uint64_t                    bo_alignment;
 323     /* This applies to EG and later. */
 324     uint32_t                    bankw;
 325     uint32_t                    bankh;
 326     uint32_t                    mtilea;
 327     uint32_t                    tile_split;
 328     uint32_t                    stencil_tile_split;
 329     struct radeon_surf_level    level[RADEON_SURF_MAX_LEVEL];
 330     struct radeon_surf_level    stencil_level[RADEON_SURF_MAX_LEVEL];
 331     uint32_t                    tiling_index[RADEON_SURF_MAX_LEVEL];
 332     uint32_t                    stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
 333     uint32_t                    pipe_config;
 334     uint32_t                    num_banks;
 335     uint32_t                    macro_tile_index;
 336     uint32_t                    micro_tile_mode; /* displayable, thin, depth, rotated */
 337
 338     /* Whether the depth miptree or stencil miptree as used by the DB are
 339      * adjusted from their TC compatible form to ensure depth/stencil
 340      * compatibility. If either is true, the corresponding plane cannot be
 341      * sampled from.
 342      */
 343     bool                        depth_adjusted;
 344     bool                        stencil_adjusted;
 345
 346     uint64_t                    dcc_size;
 347     uint64_t                    dcc_alignment;
 348     /* TC-compatible HTILE only. */
 349     uint64_t                    htile_size;
 350     uint64_t                    htile_alignment;
 351 };
 352
 353 struct radeon_bo_list_item {
 354     uint64_t bo_size;
 355     uint64_t vm_address;
 356     uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
 357 };
 358
 359 struct radeon_winsys {
 360     /**
 361      * The screen object this winsys was created for
 362      */
 363     struct pipe_screen *screen;
 364
 365     /**
 366      * Decrement the winsys reference count.
 367      *
 368      * \param ws  The winsys this function is called for.
 369      * \return    True if the winsys and screen should be destroyed.
 370      */
 371     bool (*unref)(struct radeon_winsys *ws);
 372
 373     /**
 374      * Destroy this winsys.
 375      *
 376      * \param ws        The winsys this function is called from.
 377      */
 378     void (*destroy)(struct radeon_winsys *ws);
 379
 380     /**
 381      * Query an info structure from winsys.
 382      *
 383      * \param ws        The winsys this function is called from.
 384      * \param info      Return structure
 385      */
 386     void (*query_info)(struct radeon_winsys *ws,
 387                        struct radeon_info *info);
 388
 389     /**************************************************************************
 390      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 391      *
 392      * Remember that gallium gets to choose the interface it needs, and the
 393      * window systems must then implement that interface (rather than the
 394      * other way around...).
 395      *************************************************************************/
 396
 397     /**
 398      * Create a buffer object.
 399      *
 400      * \param ws        The winsys this function is called from.
 401      * \param size      The size to allocate.
 402      * \param alignment An alignment of the buffer in memory.
 403      * \param use_reusable_pool Whether the cache buffer manager should be used.
 404      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 405      * \return          The created buffer object.
 406      */
 407     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 408                                        uint64_t size,
 409                                        unsigned alignment,
 410                                        enum radeon_bo_domain domain,
 411                                        enum radeon_bo_flag flags);
 412
 413     /**
 414      * Map the entire data store of a buffer object into the client's address
 415      * space.
 416      *
 417      * \param buf       A winsys buffer object to map.
 418      * \param cs        A command stream to flush if the buffer is referenced by it.
 419      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 420      * \return          The pointer at the beginning of the buffer.
 421      */
 422     void *(*buffer_map)(struct pb_buffer *buf,
 423                         struct radeon_winsys_cs *cs,
 424                         enum pipe_transfer_usage usage);
 425
 426     /**
 427      * Unmap a buffer object from the client's address space.
 428      *
 429      * \param buf       A winsys buffer object to unmap.
 430      */
 431     void (*buffer_unmap)(struct pb_buffer *buf);
 432
 433     /**
 434      * Wait for the buffer and return true if the buffer is not used
 435      * by the device.
 436      *
 437      * The timeout of 0 will only return the status.
 438      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
 439      * is idle.
 440      */
 441     bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
 442                         enum radeon_bo_usage usage);
 443
 444     /**
 445      * Return buffer metadata.
 446      * (tiling info for display code, DRI sharing, and other data)
 447      *
 448      * \param buf       A winsys buffer object to get the flags from.
 449      * \param md        Metadata
 450      */
 451     void (*buffer_get_metadata)(struct pb_buffer *buf,
 452                                 struct radeon_bo_metadata *md);
 453
 454     /**
 455      * Set buffer metadata.
 456      * (tiling info for display code, DRI sharing, and other data)
 457      *
 458      * \param buf       A winsys buffer object to set the flags for.
 459      * \param md        Metadata
 460      */
 461     void (*buffer_set_metadata)(struct pb_buffer *buf,
 462                                 struct radeon_bo_metadata *md);
 463
 464     /**
 465      * Get a winsys buffer from a winsys handle. The internal structure
 466      * of the handle is platform-specific and only a winsys should access it.
 467      *
 468      * \param ws        The winsys this function is called from.
 469      * \param whandle   A winsys handle pointer as was received from a state
 470      *                  tracker.
 471      * \param stride    The returned buffer stride in bytes.
 472      */
 473     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 474                                             struct winsys_handle *whandle,
 475                                             unsigned *stride, unsigned *offset);
 476
 477     /**
 478      * Get a winsys buffer from a user pointer. The resulting buffer can't
 479      * be exported. Both pointer and size must be page aligned.
 480      *
 481      * \param ws        The winsys this function is called from.
 482      * \param pointer   User pointer to turn into a buffer object.
 483      * \param Size      Size in bytes for the new buffer.
 484      */
 485     struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
 486                                          void *pointer, uint64_t size);
 487
 488     /**
 489      * Whether the buffer was created from a user pointer.
 490      *
 491      * \param buf       A winsys buffer object
 492      * \return          whether \p buf was created via buffer_from_ptr
 493      */
 494     bool (*buffer_is_user_ptr)(struct pb_buffer *buf);
 495
 496     /**
 497      * Get a winsys handle from a winsys buffer. The internal structure
 498      * of the handle is platform-specific and only a winsys should access it.
 499      *
 500      * \param buf       A winsys buffer object to get the handle from.
 501      * \param whandle   A winsys handle pointer.
 502      * \param stride    A stride of the buffer in bytes, for texturing.
 503      * \return          true on success.
 504      */
 505     bool (*buffer_get_handle)(struct pb_buffer *buf,
 506                               unsigned stride, unsigned offset,
 507                               unsigned slice_size,
 508                               struct winsys_handle *whandle);
 509
 510     /**
 511      * Return the virtual address of a buffer.
 512      *
 513      * When virtual memory is not in use, this is the offset relative to the
 514      * relocation base (non-zero for sub-allocated buffers).
 515      *
 516      * \param buf       A winsys buffer object
 517      * \return          virtual address
 518      */
 519     uint64_t (*buffer_get_virtual_address)(struct pb_buffer *buf);
 520
 521     /**
 522      * Return the offset of this buffer relative to the relocation base.
 523      * This is only non-zero for sub-allocated buffers.
 524      *
 525      * This is only supported in the radeon winsys, since amdgpu uses virtual
 526      * addresses in submissions even for the video engines.
 527      *
 528      * \param buf      A winsys buffer object
 529      * \return         the offset for relocations
 530      */
 531     unsigned (*buffer_get_reloc_offset)(struct pb_buffer *buf);
 532
 533     /**
 534      * Query the initial placement of the buffer from the kernel driver.
 535      */
 536     enum radeon_bo_domain (*buffer_get_initial_domain)(struct pb_buffer *buf);
 537
 538     /**************************************************************************
 539      * Command submission.
 540      *
 541      * Each pipe context should create its own command stream and submit
 542      * commands independently of other contexts.
 543      *************************************************************************/
 544
 545     /**
 546      * Create a command submission context.
 547      * Various command streams can be submitted to the same context.
 548      */
 549     struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 550
 551     /**
 552      * Destroy a context.
 553      */
 554     void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 555
 556     /**
 557      * Query a GPU reset status.
 558      */
 559     enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
 560
 561     /**
 562      * Create a command stream.
 563      *
 564      * \param ctx       The submission context
 565      * \param ring_type The ring type (GFX, DMA, UVD)
 566      * \param flush     Flush callback function associated with the command stream.
 567      * \param user      User pointer that will be passed to the flush callback.
 568      */
 569     struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys_ctx *ctx,
 570                                           enum ring_type ring_type,
 571                                           void (*flush)(void *ctx, unsigned flags,
 572                                                         struct pipe_fence_handle **fence),
 573                                           void *flush_ctx);
 574
 575     /**
 576      * Add a constant engine IB to a graphics CS. This makes the graphics CS
 577      * from "cs_create" a group of two IBs that share a buffer list and are
 578      * flushed together.
 579      *
 580      * The returned constant CS is only a stream for writing packets to the new
 581      * IB. Calling other winsys functions with it is not allowed, not even
 582      * "cs_destroy".
 583      *
 584      * In order to add buffers and check memory usage, use the graphics CS.
 585      * In order to flush it, use the graphics CS, which will flush both IBs.
 586      * Destroying the graphics CS will destroy both of them.
 587      *
 588      * \param cs  The graphics CS from "cs_create" that will hold the buffer
 589      *            list and will be used for flushing.
 590      */
 591     struct radeon_winsys_cs *(*cs_add_const_ib)(struct radeon_winsys_cs *cs);
 592
 593      /**
 594      * Add a constant engine preamble IB to a graphics CS. This add an extra IB
 595      * in similar manner to cs_add_const_ib. This should always be called after
 596      * cs_add_const_ib.
 597      *
 598      * The returned IB is a constant engine IB that only gets flushed if the
 599      * context changed.
 600      *
 601      * \param cs  The graphics CS from "cs_create" that will hold the buffer
 602      *            list and will be used for flushing.
 603      */
 604     struct radeon_winsys_cs *(*cs_add_const_preamble_ib)(struct radeon_winsys_cs *cs);
 605     /**
 606      * Destroy a command stream.
 607      *
 608      * \param cs        A command stream to destroy.
 609      */
 610     void (*cs_destroy)(struct radeon_winsys_cs *cs);
 611
 612     /**
 613      * Add a buffer. Each buffer used by a CS must be added using this function.
 614      *
 615      * \param cs      Command stream
 616      * \param buf     Buffer
 617      * \param usage   Whether the buffer is used for read and/or write.
 618      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 619      * \param priority  A higher number means a greater chance of being
 620      *                  placed in the requested domain. 15 is the maximum.
 621      * \return Buffer index.
 622      */
 623     unsigned (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 624                              struct pb_buffer *buf,
 625                              enum radeon_bo_usage usage,
 626                              enum radeon_bo_domain domain,
 627                              enum radeon_bo_priority priority);
 628
 629     /**
 630      * Return the index of an already-added buffer.
 631      *
 632      * Not supported on amdgpu. Drivers with GPUVM should not care about
 633      * buffer indices.
 634      *
 635      * \param cs        Command stream
 636      * \param buf       Buffer
 637      * \return          The buffer index, or -1 if the buffer has not been added.
 638      */
 639     int (*cs_lookup_buffer)(struct radeon_winsys_cs *cs,
 640                             struct pb_buffer *buf);
 641
 642     /**
 643      * Return true if there is enough memory in VRAM and GTT for the buffers
 644      * added so far. If the validation fails, all buffers which have
 645      * been added since the last call of cs_validate will be removed and
 646      * the CS will be flushed (provided there are still any buffers).
 647      *
 648      * \param cs        A command stream to validate.
 649      */
 650     bool (*cs_validate)(struct radeon_winsys_cs *cs);
 651
 652     /**
 653      * Check whether the given number of dwords is available in the IB.
 654      * Optionally chain a new chunk of the IB if necessary and supported.
 655      *
 656      * \param cs        A command stream.
 657      * \param dw        Number of CS dwords requested by the caller.
 658      */
 659     bool (*cs_check_space)(struct radeon_winsys_cs *cs, unsigned dw);
 660
 661     /**
 662      * Return the buffer list.
 663      *
 664      * This is the buffer list as passed to the kernel, i.e. it only contains
 665      * the parent buffers of sub-allocated buffers.
 666      *
 667      * \param cs    Command stream
 668      * \param list  Returned buffer list. Set to NULL to query the count only.
 669      * \return      The buffer count.
 670      */
 671     unsigned (*cs_get_buffer_list)(struct radeon_winsys_cs *cs,
 672                                    struct radeon_bo_list_item *list);
 673
 674     /**
 675      * Flush a command stream.
 676      *
 677      * \param cs          A command stream to flush.
 678      * \param flags,      RADEON_FLUSH_ASYNC or 0.
 679      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 680      *                    after the CS and is returned through this parameter.
 681      * \return Negative POSIX error code or 0 for success.
 682      *         Asynchronous submissions never return an error.
 683      */
 684     int (*cs_flush)(struct radeon_winsys_cs *cs,
 685                     unsigned flags,
 686                     struct pipe_fence_handle **fence);
 687
 688     /**
 689      * Create a fence before the CS is flushed.
 690      * The user must flush manually to complete the initializaton of the fence.
 691      * The fence must not be used before the flush.
 692      */
 693     struct pipe_fence_handle *(*cs_get_next_fence)(struct radeon_winsys_cs *cs);
 694
 695     /**
 696      * Return true if a buffer is referenced by a command stream.
 697      *
 698      * \param cs        A command stream.
 699      * \param buf       A winsys buffer.
 700      */
 701     bool (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
 702                                     struct pb_buffer *buf,
 703                                     enum radeon_bo_usage usage);
 704
 705     /**
 706      * Request access to a feature for a command stream.
 707      *
 708      * \param cs        A command stream.
 709      * \param fid       Feature ID, one of RADEON_FID_*
 710      * \param enable    Whether to enable or disable the feature.
 711      */
 712     bool (*cs_request_feature)(struct radeon_winsys_cs *cs,
 713                                enum radeon_feature_id fid,
 714                                bool enable);
 715      /**
 716       * Make sure all asynchronous flush of the cs have completed
 717       *
 718       * \param cs        A command stream.
 719       */
 720     void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
 721
 722     /**
 723      * Wait for the fence and return true if the fence has been signalled.
 724      * The timeout of 0 will only return the status.
 725      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 726      * is signalled.
 727      */
 728     bool (*fence_wait)(struct radeon_winsys *ws,
 729                        struct pipe_fence_handle *fence,
 730                        uint64_t timeout);
 731
 732     /**
 733      * Reference counting for fences.
 734      */
 735     void (*fence_reference)(struct pipe_fence_handle **dst,
 736                             struct pipe_fence_handle *src);
 737
 738     /**
 739      * Initialize surface
 740      *
 741      * \param ws        The winsys this function is called from.
 742      * \param surf      Surface structure ptr
 743      */
 744     int (*surface_init)(struct radeon_winsys *ws,
 745                         struct radeon_surf *surf);
 746
 747     /**
 748      * Find best values for a surface
 749      *
 750      * \param ws        The winsys this function is called from.
 751      * \param surf      Surface structure ptr
 752      */
 753     int (*surface_best)(struct radeon_winsys *ws,
 754                         struct radeon_surf *surf);
 755
 756     uint64_t (*query_value)(struct radeon_winsys *ws,
 757                             enum radeon_value_id value);
 758
 759     bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 760                            unsigned num_registers, uint32_t *out);
 761 };
 762
 763 static inline bool radeon_emitted(struct radeon_winsys_cs *cs, unsigned num_dw)
 764 {
 765     return cs && (cs->prev_dw + cs->current.cdw > num_dw);
 766 }
 767
 768 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 769 {
 770     cs->current.buf[cs->current.cdw++] = value;
 771 }
 772
 773 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 774                                      const uint32_t *values, unsigned count)
 775 {
 776     memcpy(cs->current.buf + cs->current.cdw, values, count * 4);
 777     cs->current.cdw += count;
 778 }
 779
 780 #endif