src/gallium/drivers/radeon/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #ifndef RADEON_WINSYS_H
  25 #define RADEON_WINSYS_H
  26
  27 /* The public winsys interface header for the radeon driver. */
  28
  29 #include "pipebuffer/pb_buffer.h"
  30
  31 #include "amd/common/amd_family.h"
  32
  33 #define RADEON_FLUSH_ASYNC              (1 << 0)
  34 #define RADEON_FLUSH_END_OF_FRAME       (1 << 1)
  35
  36 /* Tiling flags. */
  37 enum radeon_bo_layout {
  38     RADEON_LAYOUT_LINEAR = 0,
  39     RADEON_LAYOUT_TILED,
  40     RADEON_LAYOUT_SQUARETILED,
  41
  42     RADEON_LAYOUT_UNKNOWN
  43 };
  44
  45 enum radeon_bo_domain { /* bitfield */
  46     RADEON_DOMAIN_GTT  = 2,
  47     RADEON_DOMAIN_VRAM = 4,
  48     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  49 };
  50
  51 enum radeon_bo_flag { /* bitfield */
  52     RADEON_FLAG_GTT_WC =        (1 << 0),
  53     RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  54     RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  55     RADEON_FLAG_HANDLE =        (1 << 3), /* the buffer most not be suballocated */
  56 };
  57
  58 enum radeon_bo_usage { /* bitfield */
  59     RADEON_USAGE_READ = 2,
  60     RADEON_USAGE_WRITE = 4,
  61     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE,
  62
  63     /* The winsys ensures that the CS submission will be scheduled after
  64      * previously flushed CSs referencing this BO in a conflicting way.
  65      */
  66     RADEON_USAGE_SYNCHRONIZED = 8
  67 };
  68
  69 enum ring_type {
  70     RING_GFX = 0,
  71     RING_COMPUTE,
  72     RING_DMA,
  73     RING_UVD,
  74     RING_VCE,
  75     RING_LAST,
  76 };
  77
  78 enum radeon_value_id {
  79     RADEON_REQUESTED_VRAM_MEMORY,
  80     RADEON_REQUESTED_GTT_MEMORY,
  81     RADEON_MAPPED_VRAM,
  82     RADEON_MAPPED_GTT,
  83     RADEON_BUFFER_WAIT_TIME_NS,
  84     RADEON_TIMESTAMP,
  85     RADEON_NUM_CS_FLUSHES,
  86     RADEON_NUM_BYTES_MOVED,
  87     RADEON_NUM_EVICTIONS,
  88     RADEON_VRAM_USAGE,
  89     RADEON_GTT_USAGE,
  90     RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
  91     RADEON_CURRENT_SCLK,
  92     RADEON_CURRENT_MCLK,
  93     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
  94 };
  95
  96 /* Each group of four has the same priority. */
  97 enum radeon_bo_priority {
  98     RADEON_PRIO_FENCE = 0,
  99     RADEON_PRIO_TRACE,
 100     RADEON_PRIO_SO_FILLED_SIZE,
 101     RADEON_PRIO_QUERY,
 102
 103     RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
 104     RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
 105     RADEON_PRIO_DRAW_INDIRECT,
 106     RADEON_PRIO_INDEX_BUFFER,
 107
 108     RADEON_PRIO_VCE = 8,
 109     RADEON_PRIO_UVD,
 110     RADEON_PRIO_SDMA_BUFFER,
 111     RADEON_PRIO_SDMA_TEXTURE,
 112
 113     RADEON_PRIO_CP_DMA = 12,
 114
 115     RADEON_PRIO_CONST_BUFFER = 16,
 116     RADEON_PRIO_DESCRIPTORS,
 117     RADEON_PRIO_BORDER_COLORS,
 118
 119     RADEON_PRIO_SAMPLER_BUFFER = 20,
 120     RADEON_PRIO_VERTEX_BUFFER,
 121
 122     RADEON_PRIO_SHADER_RW_BUFFER = 24,
 123     RADEON_PRIO_COMPUTE_GLOBAL,
 124
 125     RADEON_PRIO_SAMPLER_TEXTURE = 28,
 126     RADEON_PRIO_SHADER_RW_IMAGE,
 127
 128     RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 32,
 129
 130     RADEON_PRIO_COLOR_BUFFER = 36,
 131
 132     RADEON_PRIO_DEPTH_BUFFER = 40,
 133
 134     RADEON_PRIO_COLOR_BUFFER_MSAA = 44,
 135
 136     RADEON_PRIO_DEPTH_BUFFER_MSAA = 48,
 137
 138     RADEON_PRIO_CMASK = 52,
 139     RADEON_PRIO_DCC,
 140     RADEON_PRIO_HTILE,
 141     RADEON_PRIO_SHADER_BINARY, /* the hw can't hide instruction cache misses */
 142
 143     RADEON_PRIO_SHADER_RINGS = 56,
 144
 145     RADEON_PRIO_SCRATCH_BUFFER = 60,
 146     /* 63 is the maximum value */
 147 };
 148
 149 struct winsys_handle;
 150 struct radeon_winsys_ctx;
 151
 152 struct radeon_winsys_cs_chunk {
 153     unsigned cdw;  /* Number of used dwords. */
 154     unsigned max_dw; /* Maximum number of dwords. */
 155     uint32_t *buf; /* The base pointer of the chunk. */
 156 };
 157
 158 struct radeon_winsys_cs {
 159     struct radeon_winsys_cs_chunk current;
 160     struct radeon_winsys_cs_chunk *prev;
 161     unsigned                      num_prev; /* Number of previous chunks. */
 162     unsigned                      max_prev; /* Space in array pointed to by prev. */
 163     unsigned                      prev_dw; /* Total number of dwords in previous chunks. */
 164
 165     /* Memory usage of the buffer list. These are always 0 for CE and preamble
 166      * IBs. */
 167     uint64_t                      used_vram;
 168     uint64_t                      used_gart;
 169 };
 170
 171 struct radeon_info {
 172     /* PCI info: domain:bus:dev:func */
 173     uint32_t                    pci_domain;
 174     uint32_t                    pci_bus;
 175     uint32_t                    pci_dev;
 176     uint32_t                    pci_func;
 177
 178     /* Device info. */
 179     uint32_t                    pci_id;
 180     enum radeon_family          family;
 181     enum chip_class             chip_class;
 182     uint32_t                    gart_page_size;
 183     uint64_t                    gart_size;
 184     uint64_t                    vram_size;
 185     uint64_t                    max_alloc_size;
 186     uint32_t                    min_alloc_size;
 187     bool                        has_dedicated_vram;
 188     bool                        has_virtual_memory;
 189     bool                        gfx_ib_pad_with_type2;
 190     bool                        has_sdma;
 191     bool                        has_uvd;
 192     uint32_t                    uvd_fw_version;
 193     uint32_t                    vce_fw_version;
 194     uint32_t                    me_fw_version;
 195     uint32_t                    pfp_fw_version;
 196     uint32_t                    ce_fw_version;
 197     uint32_t                    vce_harvest_config;
 198     uint32_t                    clock_crystal_freq;
 199
 200     /* Kernel info. */
 201     uint32_t                    drm_major; /* version */
 202     uint32_t                    drm_minor;
 203     uint32_t                    drm_patchlevel;
 204     bool                        has_userptr;
 205
 206     /* Shader cores. */
 207     uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
 208     uint32_t                    max_shader_clock;
 209     uint32_t                    num_good_compute_units;
 210     uint32_t                    max_se; /* shader engines */
 211     uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 212
 213     /* Render backends (color + depth blocks). */
 214     uint32_t                    r300_num_gb_pipes;
 215     uint32_t                    r300_num_z_pipes;
 216     uint32_t                    r600_gb_backend_map; /* R600 harvest config */
 217     bool                        r600_gb_backend_map_valid;
 218     uint32_t                    r600_num_banks;
 219     uint32_t                    num_render_backends;
 220     uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
 221     uint32_t                    pipe_interleave_bytes;
 222     uint32_t                    enabled_rb_mask; /* GCN harvest config */
 223
 224     /* Tile modes. */
 225     uint32_t                    si_tile_mode_array[32];
 226     uint32_t                    cik_macrotile_mode_array[16];
 227 };
 228
 229 /* Tiling info for display code, DRI sharing, and other data. */
 230 struct radeon_bo_metadata {
 231     /* Tiling flags describing the texture layout for display code
 232      * and DRI sharing.
 233      */
 234     enum radeon_bo_layout   microtile;
 235     enum radeon_bo_layout   macrotile;
 236     unsigned                pipe_config;
 237     unsigned                bankw;
 238     unsigned                bankh;
 239     unsigned                tile_split;
 240     unsigned                mtilea;
 241     unsigned                num_banks;
 242     unsigned                stride;
 243     bool                    scanout;
 244
 245     /* Additional metadata associated with the buffer, in bytes.
 246      * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 247      * Supported by amdgpu only.
 248      */
 249     uint32_t                size_metadata;
 250     uint32_t                metadata[64];
 251 };
 252
 253 enum radeon_feature_id {
 254     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 255     RADEON_FID_R300_CMASK_ACCESS,
 256 };
 257
 258 #define RADEON_SURF_MAX_LEVELS                  15
 259
 260 enum radeon_surf_mode {
 261     RADEON_SURF_MODE_LINEAR_ALIGNED = 1,
 262     RADEON_SURF_MODE_1D = 2,
 263     RADEON_SURF_MODE_2D = 3,
 264 };
 265
 266 /* the first 16 bits are reserved for libdrm_radeon, don't use them */
 267 #define RADEON_SURF_SCANOUT                     (1 << 16)
 268 #define RADEON_SURF_ZBUFFER                     (1 << 17)
 269 #define RADEON_SURF_SBUFFER                     (1 << 18)
 270 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
 271 #define RADEON_SURF_HAS_SBUFFER_MIPTREE         (1 << 19)
 272 #define RADEON_SURF_HAS_TILE_MODE_INDEX         (1 << 20)
 273 #define RADEON_SURF_FMASK                       (1 << 21)
 274 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
 275 #define RADEON_SURF_TC_COMPATIBLE_HTILE         (1 << 23)
 276 #define RADEON_SURF_IMPORTED                    (1 << 24)
 277
 278 struct radeon_surf_level {
 279     uint64_t                    offset;
 280     uint64_t                    slice_size;
 281     uint64_t                    dcc_offset;
 282     uint64_t                    dcc_fast_clear_size;
 283     uint16_t                    npix_x;
 284     uint16_t                    npix_y;
 285     uint16_t                    npix_z;
 286     uint16_t                    nblk_x;
 287     uint16_t                    nblk_y;
 288     uint16_t                    nblk_z;
 289     uint32_t                    pitch_bytes;
 290     enum radeon_surf_mode       mode;
 291     bool                        dcc_enabled;
 292 };
 293
 294 struct radeon_surf {
 295     /* Format properties. */
 296     unsigned                    blk_w:4;
 297     unsigned                    blk_h:4;
 298     unsigned                    bpe:5;
 299     uint32_t                    flags;
 300
 301     /* These are return values. Some of them can be set by the caller, but
 302      * they will be treated as hints (e.g. bankw, bankh) and might be
 303      * changed by the calculator.
 304      */
 305     uint64_t                    bo_size;
 306     uint32_t                    bo_alignment;
 307
 308     /* This applies to EG and later. */
 309     unsigned                    bankw:4;  /* max 8 */
 310     unsigned                    bankh:4;  /* max 8 */
 311     unsigned                    mtilea:4; /* max 8 */
 312     unsigned                    tile_split:13;         /* max 4K */
 313     unsigned                    stencil_tile_split:13; /* max 4K */
 314     unsigned                    pipe_config:5;      /* max 17 */
 315     unsigned                    num_banks:5;        /* max 16 */
 316     unsigned                    macro_tile_index:4; /* max 15 */
 317     unsigned                    micro_tile_mode:3; /* displayable, thin, depth, rotated */
 318
 319     /* Whether the depth miptree or stencil miptree as used by the DB are
 320      * adjusted from their TC compatible form to ensure depth/stencil
 321      * compatibility. If either is true, the corresponding plane cannot be
 322      * sampled from.
 323      */
 324     unsigned                    depth_adjusted:1;
 325     unsigned                    stencil_adjusted:1;
 326
 327     struct radeon_surf_level    level[RADEON_SURF_MAX_LEVELS];
 328     struct radeon_surf_level    stencil_level[RADEON_SURF_MAX_LEVELS];
 329     uint8_t                     tiling_index[RADEON_SURF_MAX_LEVELS];
 330     uint8_t                     stencil_tiling_index[RADEON_SURF_MAX_LEVELS];
 331
 332     uint64_t                    dcc_size;
 333     uint32_t                    dcc_alignment;
 334     /* TC-compatible HTILE only. */
 335     uint64_t                    htile_size;
 336     uint32_t                    htile_alignment;
 337 };
 338
 339 struct radeon_bo_list_item {
 340     uint64_t bo_size;
 341     uint64_t vm_address;
 342     uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
 343 };
 344
 345 struct radeon_winsys {
 346     /**
 347      * The screen object this winsys was created for
 348      */
 349     struct pipe_screen *screen;
 350
 351     /**
 352      * Decrement the winsys reference count.
 353      *
 354      * \param ws  The winsys this function is called for.
 355      * \return    True if the winsys and screen should be destroyed.
 356      */
 357     bool (*unref)(struct radeon_winsys *ws);
 358
 359     /**
 360      * Destroy this winsys.
 361      *
 362      * \param ws        The winsys this function is called from.
 363      */
 364     void (*destroy)(struct radeon_winsys *ws);
 365
 366     /**
 367      * Query an info structure from winsys.
 368      *
 369      * \param ws        The winsys this function is called from.
 370      * \param info      Return structure
 371      */
 372     void (*query_info)(struct radeon_winsys *ws,
 373                        struct radeon_info *info);
 374
 375     /**************************************************************************
 376      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 377      *
 378      * Remember that gallium gets to choose the interface it needs, and the
 379      * window systems must then implement that interface (rather than the
 380      * other way around...).
 381      *************************************************************************/
 382
 383     /**
 384      * Create a buffer object.
 385      *
 386      * \param ws        The winsys this function is called from.
 387      * \param size      The size to allocate.
 388      * \param alignment An alignment of the buffer in memory.
 389      * \param use_reusable_pool Whether the cache buffer manager should be used.
 390      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 391      * \return          The created buffer object.
 392      */
 393     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 394                                        uint64_t size,
 395                                        unsigned alignment,
 396                                        enum radeon_bo_domain domain,
 397                                        enum radeon_bo_flag flags);
 398
 399     /**
 400      * Map the entire data store of a buffer object into the client's address
 401      * space.
 402      *
 403      * \param buf       A winsys buffer object to map.
 404      * \param cs        A command stream to flush if the buffer is referenced by it.
 405      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 406      * \return          The pointer at the beginning of the buffer.
 407      */
 408     void *(*buffer_map)(struct pb_buffer *buf,
 409                         struct radeon_winsys_cs *cs,
 410                         enum pipe_transfer_usage usage);
 411
 412     /**
 413      * Unmap a buffer object from the client's address space.
 414      *
 415      * \param buf       A winsys buffer object to unmap.
 416      */
 417     void (*buffer_unmap)(struct pb_buffer *buf);
 418
 419     /**
 420      * Wait for the buffer and return true if the buffer is not used
 421      * by the device.
 422      *
 423      * The timeout of 0 will only return the status.
 424      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
 425      * is idle.
 426      */
 427     bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
 428                         enum radeon_bo_usage usage);
 429
 430     /**
 431      * Return buffer metadata.
 432      * (tiling info for display code, DRI sharing, and other data)
 433      *
 434      * \param buf       A winsys buffer object to get the flags from.
 435      * \param md        Metadata
 436      */
 437     void (*buffer_get_metadata)(struct pb_buffer *buf,
 438                                 struct radeon_bo_metadata *md);
 439
 440     /**
 441      * Set buffer metadata.
 442      * (tiling info for display code, DRI sharing, and other data)
 443      *
 444      * \param buf       A winsys buffer object to set the flags for.
 445      * \param md        Metadata
 446      */
 447     void (*buffer_set_metadata)(struct pb_buffer *buf,
 448                                 struct radeon_bo_metadata *md);
 449
 450     /**
 451      * Get a winsys buffer from a winsys handle. The internal structure
 452      * of the handle is platform-specific and only a winsys should access it.
 453      *
 454      * \param ws        The winsys this function is called from.
 455      * \param whandle   A winsys handle pointer as was received from a state
 456      *                  tracker.
 457      * \param stride    The returned buffer stride in bytes.
 458      */
 459     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 460                                             struct winsys_handle *whandle,
 461                                             unsigned *stride, unsigned *offset);
 462
 463     /**
 464      * Get a winsys buffer from a user pointer. The resulting buffer can't
 465      * be exported. Both pointer and size must be page aligned.
 466      *
 467      * \param ws        The winsys this function is called from.
 468      * \param pointer   User pointer to turn into a buffer object.
 469      * \param Size      Size in bytes for the new buffer.
 470      */
 471     struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
 472                                          void *pointer, uint64_t size);
 473
 474     /**
 475      * Whether the buffer was created from a user pointer.
 476      *
 477      * \param buf       A winsys buffer object
 478      * \return          whether \p buf was created via buffer_from_ptr
 479      */
 480     bool (*buffer_is_user_ptr)(struct pb_buffer *buf);
 481
 482     /**
 483      * Get a winsys handle from a winsys buffer. The internal structure
 484      * of the handle is platform-specific and only a winsys should access it.
 485      *
 486      * \param buf       A winsys buffer object to get the handle from.
 487      * \param whandle   A winsys handle pointer.
 488      * \param stride    A stride of the buffer in bytes, for texturing.
 489      * \return          true on success.
 490      */
 491     bool (*buffer_get_handle)(struct pb_buffer *buf,
 492                               unsigned stride, unsigned offset,
 493                               unsigned slice_size,
 494                               struct winsys_handle *whandle);
 495
 496     /**
 497      * Return the virtual address of a buffer.
 498      *
 499      * When virtual memory is not in use, this is the offset relative to the
 500      * relocation base (non-zero for sub-allocated buffers).
 501      *
 502      * \param buf       A winsys buffer object
 503      * \return          virtual address
 504      */
 505     uint64_t (*buffer_get_virtual_address)(struct pb_buffer *buf);
 506
 507     /**
 508      * Return the offset of this buffer relative to the relocation base.
 509      * This is only non-zero for sub-allocated buffers.
 510      *
 511      * This is only supported in the radeon winsys, since amdgpu uses virtual
 512      * addresses in submissions even for the video engines.
 513      *
 514      * \param buf      A winsys buffer object
 515      * \return         the offset for relocations
 516      */
 517     unsigned (*buffer_get_reloc_offset)(struct pb_buffer *buf);
 518
 519     /**
 520      * Query the initial placement of the buffer from the kernel driver.
 521      */
 522     enum radeon_bo_domain (*buffer_get_initial_domain)(struct pb_buffer *buf);
 523
 524     /**************************************************************************
 525      * Command submission.
 526      *
 527      * Each pipe context should create its own command stream and submit
 528      * commands independently of other contexts.
 529      *************************************************************************/
 530
 531     /**
 532      * Create a command submission context.
 533      * Various command streams can be submitted to the same context.
 534      */
 535     struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 536
 537     /**
 538      * Destroy a context.
 539      */
 540     void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 541
 542     /**
 543      * Query a GPU reset status.
 544      */
 545     enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
 546
 547     /**
 548      * Create a command stream.
 549      *
 550      * \param ctx       The submission context
 551      * \param ring_type The ring type (GFX, DMA, UVD)
 552      * \param flush     Flush callback function associated with the command stream.
 553      * \param user      User pointer that will be passed to the flush callback.
 554      */
 555     struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys_ctx *ctx,
 556                                           enum ring_type ring_type,
 557                                           void (*flush)(void *ctx, unsigned flags,
 558                                                         struct pipe_fence_handle **fence),
 559                                           void *flush_ctx);
 560
 561     /**
 562      * Add a constant engine IB to a graphics CS. This makes the graphics CS
 563      * from "cs_create" a group of two IBs that share a buffer list and are
 564      * flushed together.
 565      *
 566      * The returned constant CS is only a stream for writing packets to the new
 567      * IB. Calling other winsys functions with it is not allowed, not even
 568      * "cs_destroy".
 569      *
 570      * In order to add buffers and check memory usage, use the graphics CS.
 571      * In order to flush it, use the graphics CS, which will flush both IBs.
 572      * Destroying the graphics CS will destroy both of them.
 573      *
 574      * \param cs  The graphics CS from "cs_create" that will hold the buffer
 575      *            list and will be used for flushing.
 576      */
 577     struct radeon_winsys_cs *(*cs_add_const_ib)(struct radeon_winsys_cs *cs);
 578
 579      /**
 580      * Add a constant engine preamble IB to a graphics CS. This add an extra IB
 581      * in similar manner to cs_add_const_ib. This should always be called after
 582      * cs_add_const_ib.
 583      *
 584      * The returned IB is a constant engine IB that only gets flushed if the
 585      * context changed.
 586      *
 587      * \param cs  The graphics CS from "cs_create" that will hold the buffer
 588      *            list and will be used for flushing.
 589      */
 590     struct radeon_winsys_cs *(*cs_add_const_preamble_ib)(struct radeon_winsys_cs *cs);
 591     /**
 592      * Destroy a command stream.
 593      *
 594      * \param cs        A command stream to destroy.
 595      */
 596     void (*cs_destroy)(struct radeon_winsys_cs *cs);
 597
 598     /**
 599      * Add a buffer. Each buffer used by a CS must be added using this function.
 600      *
 601      * \param cs      Command stream
 602      * \param buf     Buffer
 603      * \param usage   Whether the buffer is used for read and/or write.
 604      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 605      * \param priority  A higher number means a greater chance of being
 606      *                  placed in the requested domain. 15 is the maximum.
 607      * \return Buffer index.
 608      */
 609     unsigned (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 610                              struct pb_buffer *buf,
 611                              enum radeon_bo_usage usage,
 612                              enum radeon_bo_domain domain,
 613                              enum radeon_bo_priority priority);
 614
 615     /**
 616      * Return the index of an already-added buffer.
 617      *
 618      * Not supported on amdgpu. Drivers with GPUVM should not care about
 619      * buffer indices.
 620      *
 621      * \param cs        Command stream
 622      * \param buf       Buffer
 623      * \return          The buffer index, or -1 if the buffer has not been added.
 624      */
 625     int (*cs_lookup_buffer)(struct radeon_winsys_cs *cs,
 626                             struct pb_buffer *buf);
 627
 628     /**
 629      * Return true if there is enough memory in VRAM and GTT for the buffers
 630      * added so far. If the validation fails, all buffers which have
 631      * been added since the last call of cs_validate will be removed and
 632      * the CS will be flushed (provided there are still any buffers).
 633      *
 634      * \param cs        A command stream to validate.
 635      */
 636     bool (*cs_validate)(struct radeon_winsys_cs *cs);
 637
 638     /**
 639      * Check whether the given number of dwords is available in the IB.
 640      * Optionally chain a new chunk of the IB if necessary and supported.
 641      *
 642      * \param cs        A command stream.
 643      * \param dw        Number of CS dwords requested by the caller.
 644      */
 645     bool (*cs_check_space)(struct radeon_winsys_cs *cs, unsigned dw);
 646
 647     /**
 648      * Return the buffer list.
 649      *
 650      * This is the buffer list as passed to the kernel, i.e. it only contains
 651      * the parent buffers of sub-allocated buffers.
 652      *
 653      * \param cs    Command stream
 654      * \param list  Returned buffer list. Set to NULL to query the count only.
 655      * \return      The buffer count.
 656      */
 657     unsigned (*cs_get_buffer_list)(struct radeon_winsys_cs *cs,
 658                                    struct radeon_bo_list_item *list);
 659
 660     /**
 661      * Flush a command stream.
 662      *
 663      * \param cs          A command stream to flush.
 664      * \param flags,      RADEON_FLUSH_ASYNC or 0.
 665      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 666      *                    after the CS and is returned through this parameter.
 667      * \return Negative POSIX error code or 0 for success.
 668      *         Asynchronous submissions never return an error.
 669      */
 670     int (*cs_flush)(struct radeon_winsys_cs *cs,
 671                     unsigned flags,
 672                     struct pipe_fence_handle **fence);
 673
 674     /**
 675      * Create a fence before the CS is flushed.
 676      * The user must flush manually to complete the initializaton of the fence.
 677      * The fence must not be used before the flush.
 678      */
 679     struct pipe_fence_handle *(*cs_get_next_fence)(struct radeon_winsys_cs *cs);
 680
 681     /**
 682      * Return true if a buffer is referenced by a command stream.
 683      *
 684      * \param cs        A command stream.
 685      * \param buf       A winsys buffer.
 686      */
 687     bool (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
 688                                     struct pb_buffer *buf,
 689                                     enum radeon_bo_usage usage);
 690
 691     /**
 692      * Request access to a feature for a command stream.
 693      *
 694      * \param cs        A command stream.
 695      * \param fid       Feature ID, one of RADEON_FID_*
 696      * \param enable    Whether to enable or disable the feature.
 697      */
 698     bool (*cs_request_feature)(struct radeon_winsys_cs *cs,
 699                                enum radeon_feature_id fid,
 700                                bool enable);
 701      /**
 702       * Make sure all asynchronous flush of the cs have completed
 703       *
 704       * \param cs        A command stream.
 705       */
 706     void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
 707
 708     /**
 709      * Wait for the fence and return true if the fence has been signalled.
 710      * The timeout of 0 will only return the status.
 711      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 712      * is signalled.
 713      */
 714     bool (*fence_wait)(struct radeon_winsys *ws,
 715                        struct pipe_fence_handle *fence,
 716                        uint64_t timeout);
 717
 718     /**
 719      * Reference counting for fences.
 720      */
 721     void (*fence_reference)(struct pipe_fence_handle **dst,
 722                             struct pipe_fence_handle *src);
 723
 724     /**
 725      * Initialize surface
 726      *
 727      * \param ws        The winsys this function is called from.
 728      * \param tex       Input texture description
 729      * \param flags     Bitmask of RADEON_SURF_* flags
 730      * \param bpe       Bytes per pixel, it can be different for Z buffers.
 731      * \param mode      Preferred tile mode. (linear, 1D, or 2D)
 732      * \param surf      Output structure
 733      */
 734     int (*surface_init)(struct radeon_winsys *ws,
 735                         const struct pipe_resource *tex,
 736                         unsigned flags, unsigned bpe,
 737                         enum radeon_surf_mode mode,
 738                         struct radeon_surf *surf);
 739
 740     uint64_t (*query_value)(struct radeon_winsys *ws,
 741                             enum radeon_value_id value);
 742
 743     bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 744                            unsigned num_registers, uint32_t *out);
 745 };
 746
 747 static inline bool radeon_emitted(struct radeon_winsys_cs *cs, unsigned num_dw)
 748 {
 749     return cs && (cs->prev_dw + cs->current.cdw > num_dw);
 750 }
 751
 752 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 753 {
 754     cs->current.buf[cs->current.cdw++] = value;
 755 }
 756
 757 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 758                                      const uint32_t *values, unsigned count)
 759 {
 760     memcpy(cs->current.buf + cs->current.cdw, values, count * 4);
 761     cs->current.cdw += count;
 762 }
 763
 764 #endif