2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 #ifndef RADEON_WINSYS_H
25 #define RADEON_WINSYS_H
27 /* The public winsys interface header for the radeon driver. */
29 #include "pipebuffer/pb_buffer.h"
31 #define RADEON_FLUSH_ASYNC (1 << 0)
32 #define RADEON_FLUSH_END_OF_FRAME (1 << 1)
35 enum radeon_bo_layout
{
36 RADEON_LAYOUT_LINEAR
= 0,
38 RADEON_LAYOUT_SQUARETILED
,
43 enum radeon_bo_domain
{ /* bitfield */
44 RADEON_DOMAIN_GTT
= 2,
45 RADEON_DOMAIN_VRAM
= 4,
46 RADEON_DOMAIN_VRAM_GTT
= RADEON_DOMAIN_VRAM
| RADEON_DOMAIN_GTT
49 enum radeon_bo_flag
{ /* bitfield */
50 RADEON_FLAG_GTT_WC
= (1 << 0),
51 RADEON_FLAG_CPU_ACCESS
= (1 << 1),
52 RADEON_FLAG_NO_CPU_ACCESS
= (1 << 2),
55 enum radeon_bo_usage
{ /* bitfield */
56 RADEON_USAGE_READ
= 2,
57 RADEON_USAGE_WRITE
= 4,
58 RADEON_USAGE_READWRITE
= RADEON_USAGE_READ
| RADEON_USAGE_WRITE
63 CHIP_R300
, /* R3xx-based cores. */
71 CHIP_R420
, /* R4xx-based cores. */
80 CHIP_RV515
, /* R5xx-based cores. */
154 enum radeon_value_id
{
155 RADEON_REQUESTED_VRAM_MEMORY
,
156 RADEON_REQUESTED_GTT_MEMORY
,
157 RADEON_BUFFER_WAIT_TIME_NS
,
159 RADEON_NUM_CS_FLUSHES
,
160 RADEON_NUM_BYTES_MOVED
,
163 RADEON_GPU_TEMPERATURE
, /* DRM 2.42.0 */
166 RADEON_GPU_RESET_COUNTER
, /* DRM 2.43.0 */
169 /* Each group of four has the same priority. */
170 enum radeon_bo_priority
{
171 RADEON_PRIO_FENCE
= 0,
173 RADEON_PRIO_SO_FILLED_SIZE
,
176 RADEON_PRIO_IB1
= 4, /* main IB submitted to the kernel */
177 RADEON_PRIO_IB2
, /* IB executed with INDIRECT_BUFFER */
178 RADEON_PRIO_DRAW_INDIRECT
,
179 RADEON_PRIO_INDEX_BUFFER
,
181 RADEON_PRIO_CP_DMA
= 8,
183 RADEON_PRIO_VCE
= 12,
185 RADEON_PRIO_SDMA_BUFFER
,
186 RADEON_PRIO_SDMA_TEXTURE
,
188 RADEON_PRIO_USER_SHADER
= 16,
189 RADEON_PRIO_INTERNAL_SHADER
, /* fetch shader, etc. */
193 RADEON_PRIO_CONST_BUFFER
= 24,
194 RADEON_PRIO_DESCRIPTORS
,
195 RADEON_PRIO_BORDER_COLORS
,
197 RADEON_PRIO_SAMPLER_BUFFER
= 28,
198 RADEON_PRIO_VERTEX_BUFFER
,
200 RADEON_PRIO_SHADER_RW_BUFFER
= 32,
201 RADEON_PRIO_RINGS_STREAMOUT
,
202 RADEON_PRIO_SCRATCH_BUFFER
,
203 RADEON_PRIO_COMPUTE_GLOBAL
,
205 RADEON_PRIO_SAMPLER_TEXTURE
= 36,
206 RADEON_PRIO_SHADER_RW_IMAGE
,
208 RADEON_PRIO_SAMPLER_TEXTURE_MSAA
= 40,
210 RADEON_PRIO_COLOR_BUFFER
= 44,
212 RADEON_PRIO_DEPTH_BUFFER
= 48,
214 RADEON_PRIO_COLOR_BUFFER_MSAA
= 52,
216 RADEON_PRIO_DEPTH_BUFFER_MSAA
= 56,
218 RADEON_PRIO_CMASK
= 60,
221 /* 63 is the maximum value */
224 struct winsys_handle
;
225 struct radeon_winsys_ctx
;
227 struct radeon_winsys_cs_chunk
{
228 unsigned cdw
; /* Number of used dwords. */
229 unsigned max_dw
; /* Maximum number of dwords. */
230 uint32_t *buf
; /* The base pointer of the chunk. */
233 struct radeon_winsys_cs
{
234 struct radeon_winsys_cs_chunk current
;
235 struct radeon_winsys_cs_chunk
*prev
;
236 unsigned num_prev
; /* Number of previous chunks. */
237 unsigned max_prev
; /* Space in array pointed to by prev. */
238 unsigned prev_dw
; /* Total number of dwords in previous chunks. */
240 /* Memory usage of the buffer list. These are always 0 for CE and preamble
247 /* PCI info: domain:bus:dev:func */
255 enum radeon_family family
;
256 enum chip_class chip_class
;
257 uint32_t gart_page_size
;
260 uint64_t max_alloc_size
;
261 bool has_dedicated_vram
;
262 bool has_virtual_memory
;
263 bool gfx_ib_pad_with_type2
;
266 uint32_t uvd_fw_version
;
267 uint32_t vce_fw_version
;
268 uint32_t me_fw_version
;
269 uint32_t pfp_fw_version
;
270 uint32_t ce_fw_version
;
271 uint32_t vce_harvest_config
;
272 uint32_t clock_crystal_freq
;
275 uint32_t drm_major
; /* version */
277 uint32_t drm_patchlevel
;
281 uint32_t r600_max_quad_pipes
; /* wave size / 16 */
282 uint32_t max_shader_clock
;
283 uint32_t num_good_compute_units
;
284 uint32_t max_se
; /* shader engines */
285 uint32_t max_sh_per_se
; /* shader arrays per shader engine */
287 /* Render backends (color + depth blocks). */
288 uint32_t r300_num_gb_pipes
;
289 uint32_t r300_num_z_pipes
;
290 uint32_t r600_gb_backend_map
; /* R600 harvest config */
291 bool r600_gb_backend_map_valid
;
292 uint32_t r600_num_banks
;
293 uint32_t num_render_backends
;
294 uint32_t num_tile_pipes
; /* pipe count from PIPE_CONFIG */
295 uint32_t pipe_interleave_bytes
;
296 uint32_t enabled_rb_mask
; /* GCN harvest config */
299 uint32_t si_tile_mode_array
[32];
300 uint32_t cik_macrotile_mode_array
[16];
303 /* Tiling info for display code, DRI sharing, and other data. */
304 struct radeon_bo_metadata
{
305 /* Tiling flags describing the texture layout for display code
308 enum radeon_bo_layout microtile
;
309 enum radeon_bo_layout macrotile
;
310 unsigned pipe_config
;
319 /* Additional metadata associated with the buffer, in bytes.
320 * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
321 * Supported by amdgpu only.
323 uint32_t size_metadata
;
324 uint32_t metadata
[64];
327 enum radeon_feature_id
{
328 RADEON_FID_R300_HYPERZ_ACCESS
, /* ZMask + HiZ */
329 RADEON_FID_R300_CMASK_ACCESS
,
332 #define RADEON_SURF_MAX_LEVEL 32
334 #define RADEON_SURF_TYPE_MASK 0xFF
335 #define RADEON_SURF_TYPE_SHIFT 0
336 #define RADEON_SURF_TYPE_1D 0
337 #define RADEON_SURF_TYPE_2D 1
338 #define RADEON_SURF_TYPE_3D 2
339 #define RADEON_SURF_TYPE_CUBEMAP 3
340 #define RADEON_SURF_TYPE_1D_ARRAY 4
341 #define RADEON_SURF_TYPE_2D_ARRAY 5
342 #define RADEON_SURF_MODE_MASK 0xFF
343 #define RADEON_SURF_MODE_SHIFT 8
344 #define RADEON_SURF_MODE_LINEAR_ALIGNED 1
345 #define RADEON_SURF_MODE_1D 2
346 #define RADEON_SURF_MODE_2D 3
347 #define RADEON_SURF_SCANOUT (1 << 16)
348 #define RADEON_SURF_ZBUFFER (1 << 17)
349 #define RADEON_SURF_SBUFFER (1 << 18)
350 #define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
351 #define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19)
352 #define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20)
353 #define RADEON_SURF_FMASK (1 << 21)
354 #define RADEON_SURF_DISABLE_DCC (1 << 22)
356 #define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
357 #define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
358 #define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
360 struct radeon_surf_level
{
369 uint32_t pitch_bytes
;
372 uint64_t dcc_fast_clear_size
;
377 /* These are inputs to the calculator. */
390 /* These are return values. Some of them can be set by the caller, but
391 * they will be treated as hints (e.g. bankw, bankh) and might be
392 * changed by the calculator.
395 uint64_t bo_alignment
;
396 /* This applies to EG and later. */
401 uint32_t stencil_tile_split
;
402 struct radeon_surf_level level
[RADEON_SURF_MAX_LEVEL
];
403 struct radeon_surf_level stencil_level
[RADEON_SURF_MAX_LEVEL
];
404 uint32_t tiling_index
[RADEON_SURF_MAX_LEVEL
];
405 uint32_t stencil_tiling_index
[RADEON_SURF_MAX_LEVEL
];
406 uint32_t pipe_config
;
408 uint32_t macro_tile_index
;
409 uint32_t micro_tile_mode
; /* displayable, thin, depth, rotated */
411 /* Whether the depth miptree or stencil miptree as used by the DB are
412 * adjusted from their TC compatible form to ensure depth/stencil
413 * compatibility. If either is true, the corresponding plane cannot be
417 bool stencil_adjusted
;
420 uint64_t dcc_alignment
;
423 struct radeon_bo_list_item
{
426 uint64_t priority_usage
; /* mask of (1 << RADEON_PRIO_*) */
429 struct radeon_winsys
{
431 * The screen object this winsys was created for
433 struct pipe_screen
*screen
;
436 * Decrement the winsys reference count.
438 * \param ws The winsys this function is called for.
439 * \return True if the winsys and screen should be destroyed.
441 bool (*unref
)(struct radeon_winsys
*ws
);
444 * Destroy this winsys.
446 * \param ws The winsys this function is called from.
448 void (*destroy
)(struct radeon_winsys
*ws
);
451 * Query an info structure from winsys.
453 * \param ws The winsys this function is called from.
454 * \param info Return structure
456 void (*query_info
)(struct radeon_winsys
*ws
,
457 struct radeon_info
*info
);
459 /**************************************************************************
460 * Buffer management. Buffer attributes are mostly fixed over its lifetime.
462 * Remember that gallium gets to choose the interface it needs, and the
463 * window systems must then implement that interface (rather than the
464 * other way around...).
465 *************************************************************************/
468 * Create a buffer object.
470 * \param ws The winsys this function is called from.
471 * \param size The size to allocate.
472 * \param alignment An alignment of the buffer in memory.
473 * \param use_reusable_pool Whether the cache buffer manager should be used.
474 * \param domain A bitmask of the RADEON_DOMAIN_* flags.
475 * \return The created buffer object.
477 struct pb_buffer
*(*buffer_create
)(struct radeon_winsys
*ws
,
480 enum radeon_bo_domain domain
,
481 enum radeon_bo_flag flags
);
484 * Map the entire data store of a buffer object into the client's address
487 * \param buf A winsys buffer object to map.
488 * \param cs A command stream to flush if the buffer is referenced by it.
489 * \param usage A bitmask of the PIPE_TRANSFER_* flags.
490 * \return The pointer at the beginning of the buffer.
492 void *(*buffer_map
)(struct pb_buffer
*buf
,
493 struct radeon_winsys_cs
*cs
,
494 enum pipe_transfer_usage usage
);
497 * Unmap a buffer object from the client's address space.
499 * \param buf A winsys buffer object to unmap.
501 void (*buffer_unmap
)(struct pb_buffer
*buf
);
504 * Wait for the buffer and return true if the buffer is not used
507 * The timeout of 0 will only return the status.
508 * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
511 bool (*buffer_wait
)(struct pb_buffer
*buf
, uint64_t timeout
,
512 enum radeon_bo_usage usage
);
515 * Return buffer metadata.
516 * (tiling info for display code, DRI sharing, and other data)
518 * \param buf A winsys buffer object to get the flags from.
521 void (*buffer_get_metadata
)(struct pb_buffer
*buf
,
522 struct radeon_bo_metadata
*md
);
525 * Set buffer metadata.
526 * (tiling info for display code, DRI sharing, and other data)
528 * \param buf A winsys buffer object to set the flags for.
531 void (*buffer_set_metadata
)(struct pb_buffer
*buf
,
532 struct radeon_bo_metadata
*md
);
535 * Get a winsys buffer from a winsys handle. The internal structure
536 * of the handle is platform-specific and only a winsys should access it.
538 * \param ws The winsys this function is called from.
539 * \param whandle A winsys handle pointer as was received from a state
541 * \param stride The returned buffer stride in bytes.
543 struct pb_buffer
*(*buffer_from_handle
)(struct radeon_winsys
*ws
,
544 struct winsys_handle
*whandle
,
545 unsigned *stride
, unsigned *offset
);
548 * Get a winsys buffer from a user pointer. The resulting buffer can't
549 * be exported. Both pointer and size must be page aligned.
551 * \param ws The winsys this function is called from.
552 * \param pointer User pointer to turn into a buffer object.
553 * \param Size Size in bytes for the new buffer.
555 struct pb_buffer
*(*buffer_from_ptr
)(struct radeon_winsys
*ws
,
556 void *pointer
, uint64_t size
);
559 * Whether the buffer was created from a user pointer.
561 * \param buf A winsys buffer object
562 * \return whether \p buf was created via buffer_from_ptr
564 bool (*buffer_is_user_ptr
)(struct pb_buffer
*buf
);
567 * Get a winsys handle from a winsys buffer. The internal structure
568 * of the handle is platform-specific and only a winsys should access it.
570 * \param buf A winsys buffer object to get the handle from.
571 * \param whandle A winsys handle pointer.
572 * \param stride A stride of the buffer in bytes, for texturing.
573 * \return true on success.
575 bool (*buffer_get_handle
)(struct pb_buffer
*buf
,
576 unsigned stride
, unsigned offset
,
578 struct winsys_handle
*whandle
);
581 * Return the virtual address of a buffer.
583 * \param buf A winsys buffer object
584 * \return virtual address
586 uint64_t (*buffer_get_virtual_address
)(struct pb_buffer
*buf
);
589 * Query the initial placement of the buffer from the kernel driver.
591 enum radeon_bo_domain (*buffer_get_initial_domain
)(struct pb_buffer
*buf
);
593 /**************************************************************************
594 * Command submission.
596 * Each pipe context should create its own command stream and submit
597 * commands independently of other contexts.
598 *************************************************************************/
601 * Create a command submission context.
602 * Various command streams can be submitted to the same context.
604 struct radeon_winsys_ctx
*(*ctx_create
)(struct radeon_winsys
*ws
);
609 void (*ctx_destroy
)(struct radeon_winsys_ctx
*ctx
);
612 * Query a GPU reset status.
614 enum pipe_reset_status (*ctx_query_reset_status
)(struct radeon_winsys_ctx
*ctx
);
617 * Create a command stream.
619 * \param ctx The submission context
620 * \param ring_type The ring type (GFX, DMA, UVD)
621 * \param flush Flush callback function associated with the command stream.
622 * \param user User pointer that will be passed to the flush callback.
624 struct radeon_winsys_cs
*(*cs_create
)(struct radeon_winsys_ctx
*ctx
,
625 enum ring_type ring_type
,
626 void (*flush
)(void *ctx
, unsigned flags
,
627 struct pipe_fence_handle
**fence
),
631 * Add a constant engine IB to a graphics CS. This makes the graphics CS
632 * from "cs_create" a group of two IBs that share a buffer list and are
635 * The returned constant CS is only a stream for writing packets to the new
636 * IB. Calling other winsys functions with it is not allowed, not even
639 * In order to add buffers and check memory usage, use the graphics CS.
640 * In order to flush it, use the graphics CS, which will flush both IBs.
641 * Destroying the graphics CS will destroy both of them.
643 * \param cs The graphics CS from "cs_create" that will hold the buffer
644 * list and will be used for flushing.
646 struct radeon_winsys_cs
*(*cs_add_const_ib
)(struct radeon_winsys_cs
*cs
);
649 * Add a constant engine preamble IB to a graphics CS. This add an extra IB
650 * in similar manner to cs_add_const_ib. This should always be called after
653 * The returned IB is a constant engine IB that only gets flushed if the
656 * \param cs The graphics CS from "cs_create" that will hold the buffer
657 * list and will be used for flushing.
659 struct radeon_winsys_cs
*(*cs_add_const_preamble_ib
)(struct radeon_winsys_cs
*cs
);
661 * Destroy a command stream.
663 * \param cs A command stream to destroy.
665 void (*cs_destroy
)(struct radeon_winsys_cs
*cs
);
668 * Add a buffer. Each buffer used by a CS must be added using this function.
670 * \param cs Command stream
672 * \param usage Whether the buffer is used for read and/or write.
673 * \param domain Bitmask of the RADEON_DOMAIN_* flags.
674 * \param priority A higher number means a greater chance of being
675 * placed in the requested domain. 15 is the maximum.
676 * \return Buffer index.
678 unsigned (*cs_add_buffer
)(struct radeon_winsys_cs
*cs
,
679 struct pb_buffer
*buf
,
680 enum radeon_bo_usage usage
,
681 enum radeon_bo_domain domain
,
682 enum radeon_bo_priority priority
);
685 * Return the index of an already-added buffer.
687 * \param cs Command stream
689 * \return The buffer index, or -1 if the buffer has not been added.
691 int (*cs_lookup_buffer
)(struct radeon_winsys_cs
*cs
,
692 struct pb_buffer
*buf
);
695 * Return true if there is enough memory in VRAM and GTT for the buffers
696 * added so far. If the validation fails, all buffers which have
697 * been added since the last call of cs_validate will be removed and
698 * the CS will be flushed (provided there are still any buffers).
700 * \param cs A command stream to validate.
702 bool (*cs_validate
)(struct radeon_winsys_cs
*cs
);
705 * Check whether the given number of dwords is available in the IB.
706 * Optionally chain a new chunk of the IB if necessary and supported.
708 * \param cs A command stream.
709 * \param dw Number of CS dwords requested by the caller.
711 bool (*cs_check_space
)(struct radeon_winsys_cs
*cs
, unsigned dw
);
714 * Return the buffer list.
716 * \param cs Command stream
717 * \param list Returned buffer list. Set to NULL to query the count only.
718 * \return The buffer count.
720 unsigned (*cs_get_buffer_list
)(struct radeon_winsys_cs
*cs
,
721 struct radeon_bo_list_item
*list
);
724 * Flush a command stream.
726 * \param cs A command stream to flush.
727 * \param flags, RADEON_FLUSH_ASYNC or 0.
728 * \param fence Pointer to a fence. If non-NULL, a fence is inserted
729 * after the CS and is returned through this parameter.
730 * \return Negative POSIX error code or 0 for success.
731 * Asynchronous submissions never return an error.
733 int (*cs_flush
)(struct radeon_winsys_cs
*cs
,
735 struct pipe_fence_handle
**fence
);
738 * Create a fence before the CS is flushed.
739 * The user must flush manually to complete the initializaton of the fence.
740 * The fence must not be used before the flush.
742 struct pipe_fence_handle
*(*cs_get_next_fence
)(struct radeon_winsys_cs
*cs
);
745 * Return true if a buffer is referenced by a command stream.
747 * \param cs A command stream.
748 * \param buf A winsys buffer.
750 bool (*cs_is_buffer_referenced
)(struct radeon_winsys_cs
*cs
,
751 struct pb_buffer
*buf
,
752 enum radeon_bo_usage usage
);
755 * Request access to a feature for a command stream.
757 * \param cs A command stream.
758 * \param fid Feature ID, one of RADEON_FID_*
759 * \param enable Whether to enable or disable the feature.
761 bool (*cs_request_feature
)(struct radeon_winsys_cs
*cs
,
762 enum radeon_feature_id fid
,
765 * Make sure all asynchronous flush of the cs have completed
767 * \param cs A command stream.
769 void (*cs_sync_flush
)(struct radeon_winsys_cs
*cs
);
772 * Wait for the fence and return true if the fence has been signalled.
773 * The timeout of 0 will only return the status.
774 * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
777 bool (*fence_wait
)(struct radeon_winsys
*ws
,
778 struct pipe_fence_handle
*fence
,
782 * Reference counting for fences.
784 void (*fence_reference
)(struct pipe_fence_handle
**dst
,
785 struct pipe_fence_handle
*src
);
790 * \param ws The winsys this function is called from.
791 * \param surf Surface structure ptr
793 int (*surface_init
)(struct radeon_winsys
*ws
,
794 struct radeon_surf
*surf
);
797 * Find best values for a surface
799 * \param ws The winsys this function is called from.
800 * \param surf Surface structure ptr
802 int (*surface_best
)(struct radeon_winsys
*ws
,
803 struct radeon_surf
*surf
);
805 uint64_t (*query_value
)(struct radeon_winsys
*ws
,
806 enum radeon_value_id value
);
808 bool (*read_registers
)(struct radeon_winsys
*ws
, unsigned reg_offset
,
809 unsigned num_registers
, uint32_t *out
);
812 static inline bool radeon_emitted(struct radeon_winsys_cs
*cs
, unsigned num_dw
)
814 return cs
&& (cs
->prev_dw
+ cs
->current
.cdw
> num_dw
);
817 static inline void radeon_emit(struct radeon_winsys_cs
*cs
, uint32_t value
)
819 cs
->current
.buf
[cs
->current
.cdw
++] = value
;
822 static inline void radeon_emit_array(struct radeon_winsys_cs
*cs
,
823 const uint32_t *values
, unsigned count
)
825 memcpy(cs
->current
.buf
+ cs
->current
.cdw
, values
, count
* 4);
826 cs
->current
.cdw
+= count
;