src/gallium/drivers/radeon/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #ifndef RADEON_WINSYS_H
  25 #define RADEON_WINSYS_H
  26
  27 /* The public winsys interface header for the radeon driver. */
  28
  29 #include "pipebuffer/pb_buffer.h"
  30
  31 #include "amd/common/ac_gpu_info.h"
  32 #include "amd/common/ac_surface.h"
  33
  34 #define RADEON_FLUSH_ASYNC              (1 << 0)
  35 #define RADEON_FLUSH_END_OF_FRAME       (1 << 1)
  36
  37 /* Tiling flags. */
  38 enum radeon_bo_layout {
  39     RADEON_LAYOUT_LINEAR = 0,
  40     RADEON_LAYOUT_TILED,
  41     RADEON_LAYOUT_SQUARETILED,
  42
  43     RADEON_LAYOUT_UNKNOWN
  44 };
  45
  46 enum radeon_bo_domain { /* bitfield */
  47     RADEON_DOMAIN_GTT  = 2,
  48     RADEON_DOMAIN_VRAM = 4,
  49     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  50 };
  51
  52 enum radeon_bo_flag { /* bitfield */
  53     RADEON_FLAG_GTT_WC =        (1 << 0),
  54     RADEON_FLAG_NO_CPU_ACCESS = (1 << 1),
  55     RADEON_FLAG_NO_SUBALLOC =   (1 << 2),
  56     RADEON_FLAG_SPARSE =        (1 << 3),
  57     RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 4),
  58 };
  59
  60 enum radeon_bo_usage { /* bitfield */
  61     RADEON_USAGE_READ = 2,
  62     RADEON_USAGE_WRITE = 4,
  63     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE,
  64
  65     /* The winsys ensures that the CS submission will be scheduled after
  66      * previously flushed CSs referencing this BO in a conflicting way.
  67      */
  68     RADEON_USAGE_SYNCHRONIZED = 8
  69 };
  70
  71 #define RADEON_SPARSE_PAGE_SIZE (64 * 1024)
  72
  73 enum ring_type {
  74     RING_GFX = 0,
  75     RING_COMPUTE,
  76     RING_DMA,
  77     RING_UVD,
  78     RING_VCE,
  79     RING_UVD_ENC,
  80     RING_VCN_DEC,
  81     RING_LAST,
  82 };
  83
  84 enum radeon_value_id {
  85     RADEON_REQUESTED_VRAM_MEMORY,
  86     RADEON_REQUESTED_GTT_MEMORY,
  87     RADEON_MAPPED_VRAM,
  88     RADEON_MAPPED_GTT,
  89     RADEON_BUFFER_WAIT_TIME_NS,
  90     RADEON_NUM_MAPPED_BUFFERS,
  91     RADEON_TIMESTAMP,
  92     RADEON_NUM_GFX_IBS,
  93     RADEON_NUM_SDMA_IBS,
  94     RADEON_GFX_BO_LIST_COUNTER, /* number of BOs submitted in gfx IBs */
  95     RADEON_GFX_IB_SIZE_COUNTER,
  96     RADEON_NUM_BYTES_MOVED,
  97     RADEON_NUM_EVICTIONS,
  98     RADEON_NUM_VRAM_CPU_PAGE_FAULTS,
  99     RADEON_VRAM_USAGE,
 100     RADEON_VRAM_VIS_USAGE,
 101     RADEON_GTT_USAGE,
 102     RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
 103     RADEON_CURRENT_SCLK,
 104     RADEON_CURRENT_MCLK,
 105     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
 106     RADEON_CS_THREAD_TIME,
 107 };
 108
 109 /* Each group of four has the same priority. */
 110 enum radeon_bo_priority {
 111     RADEON_PRIO_FENCE = 0,
 112     RADEON_PRIO_TRACE,
 113     RADEON_PRIO_SO_FILLED_SIZE,
 114     RADEON_PRIO_QUERY,
 115
 116     RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
 117     RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
 118     RADEON_PRIO_DRAW_INDIRECT,
 119     RADEON_PRIO_INDEX_BUFFER,
 120
 121     RADEON_PRIO_VCE = 8,
 122     RADEON_PRIO_UVD,
 123     RADEON_PRIO_SDMA_BUFFER,
 124     RADEON_PRIO_SDMA_TEXTURE,
 125
 126     RADEON_PRIO_CP_DMA = 12,
 127
 128     RADEON_PRIO_CONST_BUFFER = 16,
 129     RADEON_PRIO_DESCRIPTORS,
 130     RADEON_PRIO_BORDER_COLORS,
 131
 132     RADEON_PRIO_SAMPLER_BUFFER = 20,
 133     RADEON_PRIO_VERTEX_BUFFER,
 134
 135     RADEON_PRIO_SHADER_RW_BUFFER = 24,
 136     RADEON_PRIO_COMPUTE_GLOBAL,
 137
 138     RADEON_PRIO_SAMPLER_TEXTURE = 28,
 139     RADEON_PRIO_SHADER_RW_IMAGE,
 140
 141     RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 32,
 142
 143     RADEON_PRIO_COLOR_BUFFER = 36,
 144
 145     RADEON_PRIO_DEPTH_BUFFER = 40,
 146
 147     RADEON_PRIO_COLOR_BUFFER_MSAA = 44,
 148
 149     RADEON_PRIO_DEPTH_BUFFER_MSAA = 48,
 150
 151     RADEON_PRIO_CMASK = 52,
 152     RADEON_PRIO_DCC,
 153     RADEON_PRIO_HTILE,
 154     RADEON_PRIO_SHADER_BINARY, /* the hw can't hide instruction cache misses */
 155
 156     RADEON_PRIO_SHADER_RINGS = 56,
 157
 158     RADEON_PRIO_SCRATCH_BUFFER = 60,
 159     /* 63 is the maximum value */
 160 };
 161
 162 struct winsys_handle;
 163 struct radeon_winsys_ctx;
 164
 165 struct radeon_winsys_cs_chunk {
 166     unsigned cdw;  /* Number of used dwords. */
 167     unsigned max_dw; /* Maximum number of dwords. */
 168     uint32_t *buf; /* The base pointer of the chunk. */
 169 };
 170
 171 struct radeon_winsys_cs {
 172     struct radeon_winsys_cs_chunk current;
 173     struct radeon_winsys_cs_chunk *prev;
 174     unsigned                      num_prev; /* Number of previous chunks. */
 175     unsigned                      max_prev; /* Space in array pointed to by prev. */
 176     unsigned                      prev_dw; /* Total number of dwords in previous chunks. */
 177
 178     /* Memory usage of the buffer list. These are always 0 for preamble IBs. */
 179     uint64_t                      used_vram;
 180     uint64_t                      used_gart;
 181 };
 182
 183 /* Tiling info for display code, DRI sharing, and other data. */
 184 struct radeon_bo_metadata {
 185     /* Tiling flags describing the texture layout for display code
 186      * and DRI sharing.
 187      */
 188     union {
 189         struct {
 190             enum radeon_bo_layout   microtile;
 191             enum radeon_bo_layout   macrotile;
 192             unsigned                pipe_config;
 193             unsigned                bankw;
 194             unsigned                bankh;
 195             unsigned                tile_split;
 196             unsigned                mtilea;
 197             unsigned                num_banks;
 198             unsigned                stride;
 199             bool                    scanout;
 200         } legacy;
 201
 202         struct {
 203             /* surface flags */
 204             unsigned swizzle_mode:5;
 205         } gfx9;
 206     } u;
 207
 208     /* Additional metadata associated with the buffer, in bytes.
 209      * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 210      * Supported by amdgpu only.
 211      */
 212     uint32_t                size_metadata;
 213     uint32_t                metadata[64];
 214 };
 215
 216 enum radeon_feature_id {
 217     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 218     RADEON_FID_R300_CMASK_ACCESS,
 219 };
 220
 221 struct radeon_bo_list_item {
 222     uint64_t bo_size;
 223     uint64_t vm_address;
 224     uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
 225 };
 226
 227 struct radeon_winsys {
 228     /**
 229      * The screen object this winsys was created for
 230      */
 231     struct pipe_screen *screen;
 232
 233     /**
 234      * Decrement the winsys reference count.
 235      *
 236      * \param ws  The winsys this function is called for.
 237      * \return    True if the winsys and screen should be destroyed.
 238      */
 239     bool (*unref)(struct radeon_winsys *ws);
 240
 241     /**
 242      * Destroy this winsys.
 243      *
 244      * \param ws        The winsys this function is called from.
 245      */
 246     void (*destroy)(struct radeon_winsys *ws);
 247
 248     /**
 249      * Query an info structure from winsys.
 250      *
 251      * \param ws        The winsys this function is called from.
 252      * \param info      Return structure
 253      */
 254     void (*query_info)(struct radeon_winsys *ws,
 255                        struct radeon_info *info);
 256
 257     /**************************************************************************
 258      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 259      *
 260      * Remember that gallium gets to choose the interface it needs, and the
 261      * window systems must then implement that interface (rather than the
 262      * other way around...).
 263      *************************************************************************/
 264
 265     /**
 266      * Create a buffer object.
 267      *
 268      * \param ws        The winsys this function is called from.
 269      * \param size      The size to allocate.
 270      * \param alignment An alignment of the buffer in memory.
 271      * \param use_reusable_pool Whether the cache buffer manager should be used.
 272      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 273      * \return          The created buffer object.
 274      */
 275     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 276                                        uint64_t size,
 277                                        unsigned alignment,
 278                                        enum radeon_bo_domain domain,
 279                                        enum radeon_bo_flag flags);
 280
 281     /**
 282      * Map the entire data store of a buffer object into the client's address
 283      * space.
 284      *
 285      * \param buf       A winsys buffer object to map.
 286      * \param cs        A command stream to flush if the buffer is referenced by it.
 287      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 288      * \return          The pointer at the beginning of the buffer.
 289      */
 290     void *(*buffer_map)(struct pb_buffer *buf,
 291                         struct radeon_winsys_cs *cs,
 292                         enum pipe_transfer_usage usage);
 293
 294     /**
 295      * Unmap a buffer object from the client's address space.
 296      *
 297      * \param buf       A winsys buffer object to unmap.
 298      */
 299     void (*buffer_unmap)(struct pb_buffer *buf);
 300
 301     /**
 302      * Wait for the buffer and return true if the buffer is not used
 303      * by the device.
 304      *
 305      * The timeout of 0 will only return the status.
 306      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
 307      * is idle.
 308      */
 309     bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
 310                         enum radeon_bo_usage usage);
 311
 312     /**
 313      * Return buffer metadata.
 314      * (tiling info for display code, DRI sharing, and other data)
 315      *
 316      * \param buf       A winsys buffer object to get the flags from.
 317      * \param md        Metadata
 318      */
 319     void (*buffer_get_metadata)(struct pb_buffer *buf,
 320                                 struct radeon_bo_metadata *md);
 321
 322     /**
 323      * Set buffer metadata.
 324      * (tiling info for display code, DRI sharing, and other data)
 325      *
 326      * \param buf       A winsys buffer object to set the flags for.
 327      * \param md        Metadata
 328      */
 329     void (*buffer_set_metadata)(struct pb_buffer *buf,
 330                                 struct radeon_bo_metadata *md);
 331
 332     /**
 333      * Get a winsys buffer from a winsys handle. The internal structure
 334      * of the handle is platform-specific and only a winsys should access it.
 335      *
 336      * \param ws        The winsys this function is called from.
 337      * \param whandle   A winsys handle pointer as was received from a state
 338      *                  tracker.
 339      * \param stride    The returned buffer stride in bytes.
 340      */
 341     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 342                                             struct winsys_handle *whandle,
 343                                             unsigned *stride, unsigned *offset);
 344
 345     /**
 346      * Get a winsys buffer from a user pointer. The resulting buffer can't
 347      * be exported. Both pointer and size must be page aligned.
 348      *
 349      * \param ws        The winsys this function is called from.
 350      * \param pointer   User pointer to turn into a buffer object.
 351      * \param Size      Size in bytes for the new buffer.
 352      */
 353     struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
 354                                          void *pointer, uint64_t size);
 355
 356     /**
 357      * Whether the buffer was created from a user pointer.
 358      *
 359      * \param buf       A winsys buffer object
 360      * \return          whether \p buf was created via buffer_from_ptr
 361      */
 362     bool (*buffer_is_user_ptr)(struct pb_buffer *buf);
 363
 364     /** Whether the buffer was suballocated. */
 365     bool (*buffer_is_suballocated)(struct pb_buffer *buf);
 366
 367     /**
 368      * Get a winsys handle from a winsys buffer. The internal structure
 369      * of the handle is platform-specific and only a winsys should access it.
 370      *
 371      * \param buf       A winsys buffer object to get the handle from.
 372      * \param whandle   A winsys handle pointer.
 373      * \param stride    A stride of the buffer in bytes, for texturing.
 374      * \return          true on success.
 375      */
 376     bool (*buffer_get_handle)(struct pb_buffer *buf,
 377                               unsigned stride, unsigned offset,
 378                               unsigned slice_size,
 379                               struct winsys_handle *whandle);
 380
 381     /**
 382      * Change the commitment of a (64KB-page aligned) region of the given
 383      * sparse buffer.
 384      *
 385      * \warning There is no automatic synchronization with command submission.
 386      *
 387      * \note Only implemented by the amdgpu winsys.
 388      *
 389      * \return false on out of memory or other failure, true on success.
 390      */
 391     bool (*buffer_commit)(struct pb_buffer *buf,
 392                           uint64_t offset, uint64_t size,
 393                           bool commit);
 394
 395     /**
 396      * Return the virtual address of a buffer.
 397      *
 398      * When virtual memory is not in use, this is the offset relative to the
 399      * relocation base (non-zero for sub-allocated buffers).
 400      *
 401      * \param buf       A winsys buffer object
 402      * \return          virtual address
 403      */
 404     uint64_t (*buffer_get_virtual_address)(struct pb_buffer *buf);
 405
 406     /**
 407      * Return the offset of this buffer relative to the relocation base.
 408      * This is only non-zero for sub-allocated buffers.
 409      *
 410      * This is only supported in the radeon winsys, since amdgpu uses virtual
 411      * addresses in submissions even for the video engines.
 412      *
 413      * \param buf      A winsys buffer object
 414      * \return         the offset for relocations
 415      */
 416     unsigned (*buffer_get_reloc_offset)(struct pb_buffer *buf);
 417
 418     /**
 419      * Query the initial placement of the buffer from the kernel driver.
 420      */
 421     enum radeon_bo_domain (*buffer_get_initial_domain)(struct pb_buffer *buf);
 422
 423     /**************************************************************************
 424      * Command submission.
 425      *
 426      * Each pipe context should create its own command stream and submit
 427      * commands independently of other contexts.
 428      *************************************************************************/
 429
 430     /**
 431      * Create a command submission context.
 432      * Various command streams can be submitted to the same context.
 433      */
 434     struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 435
 436     /**
 437      * Destroy a context.
 438      */
 439     void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 440
 441     /**
 442      * Query a GPU reset status.
 443      */
 444     enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
 445
 446     /**
 447      * Create a command stream.
 448      *
 449      * \param ctx       The submission context
 450      * \param ring_type The ring type (GFX, DMA, UVD)
 451      * \param flush     Flush callback function associated with the command stream.
 452      * \param user      User pointer that will be passed to the flush callback.
 453      */
 454     struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys_ctx *ctx,
 455                                           enum ring_type ring_type,
 456                                           void (*flush)(void *ctx, unsigned flags,
 457                                                         struct pipe_fence_handle **fence),
 458                                           void *flush_ctx);
 459
 460     /**
 461      * Destroy a command stream.
 462      *
 463      * \param cs        A command stream to destroy.
 464      */
 465     void (*cs_destroy)(struct radeon_winsys_cs *cs);
 466
 467     /**
 468      * Add a buffer. Each buffer used by a CS must be added using this function.
 469      *
 470      * \param cs      Command stream
 471      * \param buf     Buffer
 472      * \param usage   Whether the buffer is used for read and/or write.
 473      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 474      * \param priority  A higher number means a greater chance of being
 475      *                  placed in the requested domain. 15 is the maximum.
 476      * \return Buffer index.
 477      */
 478     unsigned (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 479                              struct pb_buffer *buf,
 480                              enum radeon_bo_usage usage,
 481                              enum radeon_bo_domain domain,
 482                              enum radeon_bo_priority priority);
 483
 484     /**
 485      * Return the index of an already-added buffer.
 486      *
 487      * Not supported on amdgpu. Drivers with GPUVM should not care about
 488      * buffer indices.
 489      *
 490      * \param cs        Command stream
 491      * \param buf       Buffer
 492      * \return          The buffer index, or -1 if the buffer has not been added.
 493      */
 494     int (*cs_lookup_buffer)(struct radeon_winsys_cs *cs,
 495                             struct pb_buffer *buf);
 496
 497     /**
 498      * Return true if there is enough memory in VRAM and GTT for the buffers
 499      * added so far. If the validation fails, all buffers which have
 500      * been added since the last call of cs_validate will be removed and
 501      * the CS will be flushed (provided there are still any buffers).
 502      *
 503      * \param cs        A command stream to validate.
 504      */
 505     bool (*cs_validate)(struct radeon_winsys_cs *cs);
 506
 507     /**
 508      * Check whether the given number of dwords is available in the IB.
 509      * Optionally chain a new chunk of the IB if necessary and supported.
 510      *
 511      * \param cs        A command stream.
 512      * \param dw        Number of CS dwords requested by the caller.
 513      */
 514     bool (*cs_check_space)(struct radeon_winsys_cs *cs, unsigned dw);
 515
 516     /**
 517      * Return the buffer list.
 518      *
 519      * This is the buffer list as passed to the kernel, i.e. it only contains
 520      * the parent buffers of sub-allocated buffers.
 521      *
 522      * \param cs    Command stream
 523      * \param list  Returned buffer list. Set to NULL to query the count only.
 524      * \return      The buffer count.
 525      */
 526     unsigned (*cs_get_buffer_list)(struct radeon_winsys_cs *cs,
 527                                    struct radeon_bo_list_item *list);
 528
 529     /**
 530      * Flush a command stream.
 531      *
 532      * \param cs          A command stream to flush.
 533      * \param flags,      RADEON_FLUSH_ASYNC or 0.
 534      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 535      *                    after the CS and is returned through this parameter.
 536      * \return Negative POSIX error code or 0 for success.
 537      *         Asynchronous submissions never return an error.
 538      */
 539     int (*cs_flush)(struct radeon_winsys_cs *cs,
 540                     unsigned flags,
 541                     struct pipe_fence_handle **fence);
 542
 543     /**
 544      * Create a fence before the CS is flushed.
 545      * The user must flush manually to complete the initializaton of the fence.
 546      *
 547      * The fence must not be used for anything except \ref cs_add_fence_dependency
 548      * before the flush.
 549      */
 550     struct pipe_fence_handle *(*cs_get_next_fence)(struct radeon_winsys_cs *cs);
 551
 552     /**
 553      * Return true if a buffer is referenced by a command stream.
 554      *
 555      * \param cs        A command stream.
 556      * \param buf       A winsys buffer.
 557      */
 558     bool (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
 559                                     struct pb_buffer *buf,
 560                                     enum radeon_bo_usage usage);
 561
 562     /**
 563      * Request access to a feature for a command stream.
 564      *
 565      * \param cs        A command stream.
 566      * \param fid       Feature ID, one of RADEON_FID_*
 567      * \param enable    Whether to enable or disable the feature.
 568      */
 569     bool (*cs_request_feature)(struct radeon_winsys_cs *cs,
 570                                enum radeon_feature_id fid,
 571                                bool enable);
 572      /**
 573       * Make sure all asynchronous flush of the cs have completed
 574       *
 575       * \param cs        A command stream.
 576       */
 577     void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
 578
 579     /**
 580      * Add a fence dependency to the CS, so that the CS will wait for
 581      * the fence before execution.
 582      */
 583     void (*cs_add_fence_dependency)(struct radeon_winsys_cs *cs,
 584                                     struct pipe_fence_handle *fence);
 585
 586     /**
 587      * Wait for the fence and return true if the fence has been signalled.
 588      * The timeout of 0 will only return the status.
 589      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 590      * is signalled.
 591      */
 592     bool (*fence_wait)(struct radeon_winsys *ws,
 593                        struct pipe_fence_handle *fence,
 594                        uint64_t timeout);
 595
 596     /**
 597      * Reference counting for fences.
 598      */
 599     void (*fence_reference)(struct pipe_fence_handle **dst,
 600                             struct pipe_fence_handle *src);
 601
 602     /**
 603      * Create a new fence object corresponding to the given sync_file.
 604      */
 605     struct pipe_fence_handle *(*fence_import_sync_file)(struct radeon_winsys *ws,
 606                                                         int fd);
 607
 608     /**
 609      * Return a sync_file FD corresponding to the given fence object.
 610      */
 611     int (*fence_export_sync_file)(struct radeon_winsys *ws,
 612                                   struct pipe_fence_handle *fence);
 613
 614     /**
 615      * Initialize surface
 616      *
 617      * \param ws        The winsys this function is called from.
 618      * \param tex       Input texture description
 619      * \param flags     Bitmask of RADEON_SURF_* flags
 620      * \param bpe       Bytes per pixel, it can be different for Z buffers.
 621      * \param mode      Preferred tile mode. (linear, 1D, or 2D)
 622      * \param surf      Output structure
 623      */
 624     int (*surface_init)(struct radeon_winsys *ws,
 625                         const struct pipe_resource *tex,
 626                         unsigned flags, unsigned bpe,
 627                         enum radeon_surf_mode mode,
 628                         struct radeon_surf *surf);
 629
 630     uint64_t (*query_value)(struct radeon_winsys *ws,
 631                             enum radeon_value_id value);
 632
 633     bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 634                            unsigned num_registers, uint32_t *out);
 635
 636     const char* (*get_chip_name)(struct radeon_winsys *ws);
 637 };
 638
 639 static inline bool radeon_emitted(struct radeon_winsys_cs *cs, unsigned num_dw)
 640 {
 641     return cs && (cs->prev_dw + cs->current.cdw > num_dw);
 642 }
 643
 644 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 645 {
 646     cs->current.buf[cs->current.cdw++] = value;
 647 }
 648
 649 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 650                                      const uint32_t *values, unsigned count)
 651 {
 652     memcpy(cs->current.buf + cs->current.cdw, values, count * 4);
 653     cs->current.cdw += count;
 654 }
 655
 656 enum radeon_heap {
 657     RADEON_HEAP_VRAM_NO_CPU_ACCESS,
 658     RADEON_HEAP_VRAM,
 659     RADEON_HEAP_VRAM_GTT, /* combined heaps */
 660     RADEON_HEAP_GTT_WC,
 661     RADEON_HEAP_GTT,
 662     RADEON_MAX_SLAB_HEAPS,
 663     RADEON_MAX_CACHED_HEAPS = RADEON_MAX_SLAB_HEAPS,
 664 };
 665
 666 static inline enum radeon_bo_domain radeon_domain_from_heap(enum radeon_heap heap)
 667 {
 668     switch (heap) {
 669     case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
 670     case RADEON_HEAP_VRAM:
 671         return RADEON_DOMAIN_VRAM;
 672     case RADEON_HEAP_VRAM_GTT:
 673         return RADEON_DOMAIN_VRAM_GTT;
 674     case RADEON_HEAP_GTT_WC:
 675     case RADEON_HEAP_GTT:
 676         return RADEON_DOMAIN_GTT;
 677     default:
 678         assert(0);
 679         return (enum radeon_bo_domain)0;
 680     }
 681 }
 682
 683 static inline unsigned radeon_flags_from_heap(enum radeon_heap heap)
 684 {
 685     switch (heap) {
 686     case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
 687         return RADEON_FLAG_GTT_WC |
 688                RADEON_FLAG_NO_CPU_ACCESS |
 689                RADEON_FLAG_NO_INTERPROCESS_SHARING;
 690
 691     case RADEON_HEAP_VRAM:
 692     case RADEON_HEAP_VRAM_GTT:
 693     case RADEON_HEAP_GTT_WC:
 694         return RADEON_FLAG_GTT_WC |
 695                RADEON_FLAG_NO_INTERPROCESS_SHARING;
 696
 697     case RADEON_HEAP_GTT:
 698     default:
 699         return RADEON_FLAG_NO_INTERPROCESS_SHARING;
 700     }
 701 }
 702
 703 /* The pb cache bucket is chosen to minimize pb_cache misses.
 704  * It must be between 0 and 3 inclusive.
 705  */
 706 static inline unsigned radeon_get_pb_cache_bucket_index(enum radeon_heap heap)
 707 {
 708     switch (heap) {
 709     case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
 710         return 0;
 711     case RADEON_HEAP_VRAM:
 712     case RADEON_HEAP_VRAM_GTT:
 713         return 1;
 714     case RADEON_HEAP_GTT_WC:
 715         return 2;
 716     case RADEON_HEAP_GTT:
 717     default:
 718         return 3;
 719     }
 720 }
 721
 722 /* Return the heap index for winsys allocators, or -1 on failure. */
 723 static inline int radeon_get_heap_index(enum radeon_bo_domain domain,
 724                                         enum radeon_bo_flag flags)
 725 {
 726     /* VRAM implies WC (write combining) */
 727     assert(!(domain & RADEON_DOMAIN_VRAM) || flags & RADEON_FLAG_GTT_WC);
 728     /* NO_CPU_ACCESS implies VRAM only. */
 729     assert(!(flags & RADEON_FLAG_NO_CPU_ACCESS) || domain == RADEON_DOMAIN_VRAM);
 730
 731     /* Resources with interprocess sharing don't use any winsys allocators. */
 732     if (!(flags & RADEON_FLAG_NO_INTERPROCESS_SHARING))
 733         return -1;
 734
 735     /* Unsupported flags: NO_SUBALLOC, SPARSE. */
 736     if (flags & ~(RADEON_FLAG_GTT_WC |
 737                   RADEON_FLAG_NO_CPU_ACCESS |
 738                   RADEON_FLAG_NO_INTERPROCESS_SHARING))
 739         return -1;
 740
 741     switch (domain) {
 742     case RADEON_DOMAIN_VRAM:
 743         if (flags & RADEON_FLAG_NO_CPU_ACCESS)
 744             return RADEON_HEAP_VRAM_NO_CPU_ACCESS;
 745         else
 746             return RADEON_HEAP_VRAM;
 747     case RADEON_DOMAIN_VRAM_GTT:
 748         return RADEON_HEAP_VRAM_GTT;
 749     case RADEON_DOMAIN_GTT:
 750         if (flags & RADEON_FLAG_GTT_WC)
 751             return RADEON_HEAP_GTT_WC;
 752         else
 753             return RADEON_HEAP_GTT;
 754     }
 755     return -1;
 756 }
 757
 758 #endif