src/gallium/drivers/radeon/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #ifndef RADEON_WINSYS_H
  25 #define RADEON_WINSYS_H
  26
  27 /* The public winsys interface header for the radeon driver. */
  28
  29 #include "pipebuffer/pb_buffer.h"
  30
  31 #include "amd/common/amd_family.h"
  32
  33 #define RADEON_FLUSH_ASYNC              (1 << 0)
  34 #define RADEON_FLUSH_END_OF_FRAME       (1 << 1)
  35
  36 /* Tiling flags. */
  37 enum radeon_bo_layout {
  38     RADEON_LAYOUT_LINEAR = 0,
  39     RADEON_LAYOUT_TILED,
  40     RADEON_LAYOUT_SQUARETILED,
  41
  42     RADEON_LAYOUT_UNKNOWN
  43 };
  44
  45 enum radeon_bo_domain { /* bitfield */
  46     RADEON_DOMAIN_GTT  = 2,
  47     RADEON_DOMAIN_VRAM = 4,
  48     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  49 };
  50
  51 enum radeon_bo_flag { /* bitfield */
  52     RADEON_FLAG_GTT_WC =        (1 << 0),
  53     RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  54     RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  55 };
  56
  57 enum radeon_bo_usage { /* bitfield */
  58     RADEON_USAGE_READ = 2,
  59     RADEON_USAGE_WRITE = 4,
  60     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE,
  61
  62     /* The winsys ensures that the CS submission will be scheduled after
  63      * previously flushed CSs referencing this BO in a conflicting way.
  64      */
  65     RADEON_USAGE_SYNCHRONIZED = 8
  66 };
  67
  68 enum ring_type {
  69     RING_GFX = 0,
  70     RING_COMPUTE,
  71     RING_DMA,
  72     RING_UVD,
  73     RING_VCE,
  74     RING_LAST,
  75 };
  76
  77 enum radeon_value_id {
  78     RADEON_REQUESTED_VRAM_MEMORY,
  79     RADEON_REQUESTED_GTT_MEMORY,
  80     RADEON_MAPPED_VRAM,
  81     RADEON_MAPPED_GTT,
  82     RADEON_BUFFER_WAIT_TIME_NS,
  83     RADEON_TIMESTAMP,
  84     RADEON_NUM_CS_FLUSHES,
  85     RADEON_NUM_BYTES_MOVED,
  86     RADEON_NUM_EVICTIONS,
  87     RADEON_VRAM_USAGE,
  88     RADEON_GTT_USAGE,
  89     RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
  90     RADEON_CURRENT_SCLK,
  91     RADEON_CURRENT_MCLK,
  92     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
  93 };
  94
  95 /* Each group of four has the same priority. */
  96 enum radeon_bo_priority {
  97     RADEON_PRIO_FENCE = 0,
  98     RADEON_PRIO_TRACE,
  99     RADEON_PRIO_SO_FILLED_SIZE,
 100     RADEON_PRIO_QUERY,
 101
 102     RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
 103     RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
 104     RADEON_PRIO_DRAW_INDIRECT,
 105     RADEON_PRIO_INDEX_BUFFER,
 106
 107     RADEON_PRIO_VCE = 8,
 108     RADEON_PRIO_UVD,
 109     RADEON_PRIO_SDMA_BUFFER,
 110     RADEON_PRIO_SDMA_TEXTURE,
 111
 112     RADEON_PRIO_CP_DMA = 12,
 113
 114     RADEON_PRIO_CONST_BUFFER = 16,
 115     RADEON_PRIO_DESCRIPTORS,
 116     RADEON_PRIO_BORDER_COLORS,
 117
 118     RADEON_PRIO_SAMPLER_BUFFER = 20,
 119     RADEON_PRIO_VERTEX_BUFFER,
 120
 121     RADEON_PRIO_SHADER_RW_BUFFER = 24,
 122     RADEON_PRIO_COMPUTE_GLOBAL,
 123
 124     RADEON_PRIO_SAMPLER_TEXTURE = 28,
 125     RADEON_PRIO_SHADER_RW_IMAGE,
 126
 127     RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 32,
 128
 129     RADEON_PRIO_COLOR_BUFFER = 36,
 130
 131     RADEON_PRIO_DEPTH_BUFFER = 40,
 132
 133     RADEON_PRIO_COLOR_BUFFER_MSAA = 44,
 134
 135     RADEON_PRIO_DEPTH_BUFFER_MSAA = 48,
 136
 137     RADEON_PRIO_CMASK = 52,
 138     RADEON_PRIO_DCC,
 139     RADEON_PRIO_HTILE,
 140     RADEON_PRIO_SHADER_BINARY, /* the hw can't hide instruction cache misses */
 141
 142     RADEON_PRIO_SHADER_RINGS = 56,
 143
 144     RADEON_PRIO_SCRATCH_BUFFER = 60,
 145     /* 63 is the maximum value */
 146 };
 147
 148 struct winsys_handle;
 149 struct radeon_winsys_ctx;
 150
 151 struct radeon_winsys_cs_chunk {
 152     unsigned cdw;  /* Number of used dwords. */
 153     unsigned max_dw; /* Maximum number of dwords. */
 154     uint32_t *buf; /* The base pointer of the chunk. */
 155 };
 156
 157 struct radeon_winsys_cs {
 158     struct radeon_winsys_cs_chunk current;
 159     struct radeon_winsys_cs_chunk *prev;
 160     unsigned                      num_prev; /* Number of previous chunks. */
 161     unsigned                      max_prev; /* Space in array pointed to by prev. */
 162     unsigned                      prev_dw; /* Total number of dwords in previous chunks. */
 163
 164     /* Memory usage of the buffer list. These are always 0 for CE and preamble
 165      * IBs. */
 166     uint64_t                      used_vram;
 167     uint64_t                      used_gart;
 168 };
 169
 170 struct radeon_info {
 171     /* PCI info: domain:bus:dev:func */
 172     uint32_t                    pci_domain;
 173     uint32_t                    pci_bus;
 174     uint32_t                    pci_dev;
 175     uint32_t                    pci_func;
 176
 177     /* Device info. */
 178     uint32_t                    pci_id;
 179     enum radeon_family          family;
 180     enum chip_class             chip_class;
 181     uint32_t                    gart_page_size;
 182     uint64_t                    gart_size;
 183     uint64_t                    vram_size;
 184     uint64_t                    max_alloc_size;
 185     bool                        has_dedicated_vram;
 186     bool                        has_virtual_memory;
 187     bool                        gfx_ib_pad_with_type2;
 188     bool                        has_sdma;
 189     bool                        has_uvd;
 190     uint32_t                    uvd_fw_version;
 191     uint32_t                    vce_fw_version;
 192     uint32_t                    me_fw_version;
 193     uint32_t                    pfp_fw_version;
 194     uint32_t                    ce_fw_version;
 195     uint32_t                    vce_harvest_config;
 196     uint32_t                    clock_crystal_freq;
 197
 198     /* Kernel info. */
 199     uint32_t                    drm_major; /* version */
 200     uint32_t                    drm_minor;
 201     uint32_t                    drm_patchlevel;
 202     bool                        has_userptr;
 203
 204     /* Shader cores. */
 205     uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
 206     uint32_t                    max_shader_clock;
 207     uint32_t                    num_good_compute_units;
 208     uint32_t                    max_se; /* shader engines */
 209     uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 210
 211     /* Render backends (color + depth blocks). */
 212     uint32_t                    r300_num_gb_pipes;
 213     uint32_t                    r300_num_z_pipes;
 214     uint32_t                    r600_gb_backend_map; /* R600 harvest config */
 215     bool                        r600_gb_backend_map_valid;
 216     uint32_t                    r600_num_banks;
 217     uint32_t                    num_render_backends;
 218     uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
 219     uint32_t                    pipe_interleave_bytes;
 220     uint32_t                    enabled_rb_mask; /* GCN harvest config */
 221
 222     /* Tile modes. */
 223     uint32_t                    si_tile_mode_array[32];
 224     uint32_t                    cik_macrotile_mode_array[16];
 225 };
 226
 227 /* Tiling info for display code, DRI sharing, and other data. */
 228 struct radeon_bo_metadata {
 229     /* Tiling flags describing the texture layout for display code
 230      * and DRI sharing.
 231      */
 232     enum radeon_bo_layout   microtile;
 233     enum radeon_bo_layout   macrotile;
 234     unsigned                pipe_config;
 235     unsigned                bankw;
 236     unsigned                bankh;
 237     unsigned                tile_split;
 238     unsigned                mtilea;
 239     unsigned                num_banks;
 240     unsigned                stride;
 241     bool                    scanout;
 242
 243     /* Additional metadata associated with the buffer, in bytes.
 244      * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 245      * Supported by amdgpu only.
 246      */
 247     uint32_t                size_metadata;
 248     uint32_t                metadata[64];
 249 };
 250
 251 enum radeon_feature_id {
 252     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 253     RADEON_FID_R300_CMASK_ACCESS,
 254 };
 255
 256 #define RADEON_SURF_MAX_LEVEL                   32
 257
 258 #define RADEON_SURF_TYPE_MASK                   0xFF
 259 #define RADEON_SURF_TYPE_SHIFT                  0
 260 #define     RADEON_SURF_TYPE_1D                     0
 261 #define     RADEON_SURF_TYPE_2D                     1
 262 #define     RADEON_SURF_TYPE_3D                     2
 263 #define     RADEON_SURF_TYPE_CUBEMAP                3
 264 #define     RADEON_SURF_TYPE_1D_ARRAY               4
 265 #define     RADEON_SURF_TYPE_2D_ARRAY               5
 266 #define RADEON_SURF_MODE_MASK                   0xFF
 267 #define RADEON_SURF_MODE_SHIFT                  8
 268 #define     RADEON_SURF_MODE_LINEAR_ALIGNED         1
 269 #define     RADEON_SURF_MODE_1D                     2
 270 #define     RADEON_SURF_MODE_2D                     3
 271 #define RADEON_SURF_SCANOUT                     (1 << 16)
 272 #define RADEON_SURF_ZBUFFER                     (1 << 17)
 273 #define RADEON_SURF_SBUFFER                     (1 << 18)
 274 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
 275 #define RADEON_SURF_HAS_SBUFFER_MIPTREE         (1 << 19)
 276 #define RADEON_SURF_HAS_TILE_MODE_INDEX         (1 << 20)
 277 #define RADEON_SURF_FMASK                       (1 << 21)
 278 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
 279
 280 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
 281 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
 282 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
 283
 284 struct radeon_surf_level {
 285     uint64_t                    offset;
 286     uint64_t                    slice_size;
 287     uint32_t                    npix_x;
 288     uint32_t                    npix_y;
 289     uint32_t                    npix_z;
 290     uint32_t                    nblk_x;
 291     uint32_t                    nblk_y;
 292     uint32_t                    nblk_z;
 293     uint32_t                    pitch_bytes;
 294     uint32_t                    mode;
 295     uint64_t                    dcc_offset;
 296     uint64_t                    dcc_fast_clear_size;
 297     bool                        dcc_enabled;
 298 };
 299
 300 struct radeon_surf {
 301     /* These are inputs to the calculator. */
 302     uint32_t                    npix_x;
 303     uint32_t                    npix_y;
 304     uint32_t                    npix_z;
 305     uint32_t                    blk_w;
 306     uint32_t                    blk_h;
 307     uint32_t                    blk_d;
 308     uint32_t                    array_size;
 309     uint32_t                    last_level;
 310     uint32_t                    bpe;
 311     uint32_t                    nsamples;
 312     uint32_t                    flags;
 313
 314     /* These are return values. Some of them can be set by the caller, but
 315      * they will be treated as hints (e.g. bankw, bankh) and might be
 316      * changed by the calculator.
 317      */
 318     uint64_t                    bo_size;
 319     uint64_t                    bo_alignment;
 320     /* This applies to EG and later. */
 321     uint32_t                    bankw;
 322     uint32_t                    bankh;
 323     uint32_t                    mtilea;
 324     uint32_t                    tile_split;
 325     uint32_t                    stencil_tile_split;
 326     struct radeon_surf_level    level[RADEON_SURF_MAX_LEVEL];
 327     struct radeon_surf_level    stencil_level[RADEON_SURF_MAX_LEVEL];
 328     uint32_t                    tiling_index[RADEON_SURF_MAX_LEVEL];
 329     uint32_t                    stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
 330     uint32_t                    pipe_config;
 331     uint32_t                    num_banks;
 332     uint32_t                    macro_tile_index;
 333     uint32_t                    micro_tile_mode; /* displayable, thin, depth, rotated */
 334
 335     /* Whether the depth miptree or stencil miptree as used by the DB are
 336      * adjusted from their TC compatible form to ensure depth/stencil
 337      * compatibility. If either is true, the corresponding plane cannot be
 338      * sampled from.
 339      */
 340     bool                        depth_adjusted;
 341     bool                        stencil_adjusted;
 342
 343     uint64_t                    dcc_size;
 344     uint64_t                    dcc_alignment;
 345 };
 346
 347 struct radeon_bo_list_item {
 348     uint64_t bo_size;
 349     uint64_t vm_address;
 350     uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
 351 };
 352
 353 struct radeon_winsys {
 354     /**
 355      * The screen object this winsys was created for
 356      */
 357     struct pipe_screen *screen;
 358
 359     /**
 360      * Decrement the winsys reference count.
 361      *
 362      * \param ws  The winsys this function is called for.
 363      * \return    True if the winsys and screen should be destroyed.
 364      */
 365     bool (*unref)(struct radeon_winsys *ws);
 366
 367     /**
 368      * Destroy this winsys.
 369      *
 370      * \param ws        The winsys this function is called from.
 371      */
 372     void (*destroy)(struct radeon_winsys *ws);
 373
 374     /**
 375      * Query an info structure from winsys.
 376      *
 377      * \param ws        The winsys this function is called from.
 378      * \param info      Return structure
 379      */
 380     void (*query_info)(struct radeon_winsys *ws,
 381                        struct radeon_info *info);
 382
 383     /**************************************************************************
 384      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 385      *
 386      * Remember that gallium gets to choose the interface it needs, and the
 387      * window systems must then implement that interface (rather than the
 388      * other way around...).
 389      *************************************************************************/
 390
 391     /**
 392      * Create a buffer object.
 393      *
 394      * \param ws        The winsys this function is called from.
 395      * \param size      The size to allocate.
 396      * \param alignment An alignment of the buffer in memory.
 397      * \param use_reusable_pool Whether the cache buffer manager should be used.
 398      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 399      * \return          The created buffer object.
 400      */
 401     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 402                                        uint64_t size,
 403                                        unsigned alignment,
 404                                        enum radeon_bo_domain domain,
 405                                        enum radeon_bo_flag flags);
 406
 407     /**
 408      * Map the entire data store of a buffer object into the client's address
 409      * space.
 410      *
 411      * \param buf       A winsys buffer object to map.
 412      * \param cs        A command stream to flush if the buffer is referenced by it.
 413      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 414      * \return          The pointer at the beginning of the buffer.
 415      */
 416     void *(*buffer_map)(struct pb_buffer *buf,
 417                         struct radeon_winsys_cs *cs,
 418                         enum pipe_transfer_usage usage);
 419
 420     /**
 421      * Unmap a buffer object from the client's address space.
 422      *
 423      * \param buf       A winsys buffer object to unmap.
 424      */
 425     void (*buffer_unmap)(struct pb_buffer *buf);
 426
 427     /**
 428      * Wait for the buffer and return true if the buffer is not used
 429      * by the device.
 430      *
 431      * The timeout of 0 will only return the status.
 432      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
 433      * is idle.
 434      */
 435     bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
 436                         enum radeon_bo_usage usage);
 437
 438     /**
 439      * Return buffer metadata.
 440      * (tiling info for display code, DRI sharing, and other data)
 441      *
 442      * \param buf       A winsys buffer object to get the flags from.
 443      * \param md        Metadata
 444      */
 445     void (*buffer_get_metadata)(struct pb_buffer *buf,
 446                                 struct radeon_bo_metadata *md);
 447
 448     /**
 449      * Set buffer metadata.
 450      * (tiling info for display code, DRI sharing, and other data)
 451      *
 452      * \param buf       A winsys buffer object to set the flags for.
 453      * \param md        Metadata
 454      */
 455     void (*buffer_set_metadata)(struct pb_buffer *buf,
 456                                 struct radeon_bo_metadata *md);
 457
 458     /**
 459      * Get a winsys buffer from a winsys handle. The internal structure
 460      * of the handle is platform-specific and only a winsys should access it.
 461      *
 462      * \param ws        The winsys this function is called from.
 463      * \param whandle   A winsys handle pointer as was received from a state
 464      *                  tracker.
 465      * \param stride    The returned buffer stride in bytes.
 466      */
 467     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 468                                             struct winsys_handle *whandle,
 469                                             unsigned *stride, unsigned *offset);
 470
 471     /**
 472      * Get a winsys buffer from a user pointer. The resulting buffer can't
 473      * be exported. Both pointer and size must be page aligned.
 474      *
 475      * \param ws        The winsys this function is called from.
 476      * \param pointer   User pointer to turn into a buffer object.
 477      * \param Size      Size in bytes for the new buffer.
 478      */
 479     struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
 480                                          void *pointer, uint64_t size);
 481
 482     /**
 483      * Whether the buffer was created from a user pointer.
 484      *
 485      * \param buf       A winsys buffer object
 486      * \return          whether \p buf was created via buffer_from_ptr
 487      */
 488     bool (*buffer_is_user_ptr)(struct pb_buffer *buf);
 489
 490     /**
 491      * Get a winsys handle from a winsys buffer. The internal structure
 492      * of the handle is platform-specific and only a winsys should access it.
 493      *
 494      * \param buf       A winsys buffer object to get the handle from.
 495      * \param whandle   A winsys handle pointer.
 496      * \param stride    A stride of the buffer in bytes, for texturing.
 497      * \return          true on success.
 498      */
 499     bool (*buffer_get_handle)(struct pb_buffer *buf,
 500                               unsigned stride, unsigned offset,
 501                               unsigned slice_size,
 502                               struct winsys_handle *whandle);
 503
 504     /**
 505      * Return the virtual address of a buffer.
 506      *
 507      * \param buf       A winsys buffer object
 508      * \return          virtual address
 509      */
 510     uint64_t (*buffer_get_virtual_address)(struct pb_buffer *buf);
 511
 512     /**
 513      * Query the initial placement of the buffer from the kernel driver.
 514      */
 515     enum radeon_bo_domain (*buffer_get_initial_domain)(struct pb_buffer *buf);
 516
 517     /**************************************************************************
 518      * Command submission.
 519      *
 520      * Each pipe context should create its own command stream and submit
 521      * commands independently of other contexts.
 522      *************************************************************************/
 523
 524     /**
 525      * Create a command submission context.
 526      * Various command streams can be submitted to the same context.
 527      */
 528     struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 529
 530     /**
 531      * Destroy a context.
 532      */
 533     void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 534
 535     /**
 536      * Query a GPU reset status.
 537      */
 538     enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
 539
 540     /**
 541      * Create a command stream.
 542      *
 543      * \param ctx       The submission context
 544      * \param ring_type The ring type (GFX, DMA, UVD)
 545      * \param flush     Flush callback function associated with the command stream.
 546      * \param user      User pointer that will be passed to the flush callback.
 547      */
 548     struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys_ctx *ctx,
 549                                           enum ring_type ring_type,
 550                                           void (*flush)(void *ctx, unsigned flags,
 551                                                         struct pipe_fence_handle **fence),
 552                                           void *flush_ctx);
 553
 554     /**
 555      * Add a constant engine IB to a graphics CS. This makes the graphics CS
 556      * from "cs_create" a group of two IBs that share a buffer list and are
 557      * flushed together.
 558      *
 559      * The returned constant CS is only a stream for writing packets to the new
 560      * IB. Calling other winsys functions with it is not allowed, not even
 561      * "cs_destroy".
 562      *
 563      * In order to add buffers and check memory usage, use the graphics CS.
 564      * In order to flush it, use the graphics CS, which will flush both IBs.
 565      * Destroying the graphics CS will destroy both of them.
 566      *
 567      * \param cs  The graphics CS from "cs_create" that will hold the buffer
 568      *            list and will be used for flushing.
 569      */
 570     struct radeon_winsys_cs *(*cs_add_const_ib)(struct radeon_winsys_cs *cs);
 571
 572      /**
 573      * Add a constant engine preamble IB to a graphics CS. This add an extra IB
 574      * in similar manner to cs_add_const_ib. This should always be called after
 575      * cs_add_const_ib.
 576      *
 577      * The returned IB is a constant engine IB that only gets flushed if the
 578      * context changed.
 579      *
 580      * \param cs  The graphics CS from "cs_create" that will hold the buffer
 581      *            list and will be used for flushing.
 582      */
 583     struct radeon_winsys_cs *(*cs_add_const_preamble_ib)(struct radeon_winsys_cs *cs);
 584     /**
 585      * Destroy a command stream.
 586      *
 587      * \param cs        A command stream to destroy.
 588      */
 589     void (*cs_destroy)(struct radeon_winsys_cs *cs);
 590
 591     /**
 592      * Add a buffer. Each buffer used by a CS must be added using this function.
 593      *
 594      * \param cs      Command stream
 595      * \param buf     Buffer
 596      * \param usage   Whether the buffer is used for read and/or write.
 597      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 598      * \param priority  A higher number means a greater chance of being
 599      *                  placed in the requested domain. 15 is the maximum.
 600      * \return Buffer index.
 601      */
 602     unsigned (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 603                              struct pb_buffer *buf,
 604                              enum radeon_bo_usage usage,
 605                              enum radeon_bo_domain domain,
 606                              enum radeon_bo_priority priority);
 607
 608     /**
 609      * Return the index of an already-added buffer.
 610      *
 611      * Not supported on amdgpu. Drivers with GPUVM should not care about
 612      * buffer indices.
 613      *
 614      * \param cs        Command stream
 615      * \param buf       Buffer
 616      * \return          The buffer index, or -1 if the buffer has not been added.
 617      */
 618     int (*cs_lookup_buffer)(struct radeon_winsys_cs *cs,
 619                             struct pb_buffer *buf);
 620
 621     /**
 622      * Return true if there is enough memory in VRAM and GTT for the buffers
 623      * added so far. If the validation fails, all buffers which have
 624      * been added since the last call of cs_validate will be removed and
 625      * the CS will be flushed (provided there are still any buffers).
 626      *
 627      * \param cs        A command stream to validate.
 628      */
 629     bool (*cs_validate)(struct radeon_winsys_cs *cs);
 630
 631     /**
 632      * Check whether the given number of dwords is available in the IB.
 633      * Optionally chain a new chunk of the IB if necessary and supported.
 634      *
 635      * \param cs        A command stream.
 636      * \param dw        Number of CS dwords requested by the caller.
 637      */
 638     bool (*cs_check_space)(struct radeon_winsys_cs *cs, unsigned dw);
 639
 640     /**
 641      * Return the buffer list.
 642      *
 643      * \param cs    Command stream
 644      * \param list  Returned buffer list. Set to NULL to query the count only.
 645      * \return      The buffer count.
 646      */
 647     unsigned (*cs_get_buffer_list)(struct radeon_winsys_cs *cs,
 648                                    struct radeon_bo_list_item *list);
 649
 650     /**
 651      * Flush a command stream.
 652      *
 653      * \param cs          A command stream to flush.
 654      * \param flags,      RADEON_FLUSH_ASYNC or 0.
 655      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 656      *                    after the CS and is returned through this parameter.
 657      * \return Negative POSIX error code or 0 for success.
 658      *         Asynchronous submissions never return an error.
 659      */
 660     int (*cs_flush)(struct radeon_winsys_cs *cs,
 661                     unsigned flags,
 662                     struct pipe_fence_handle **fence);
 663
 664     /**
 665      * Create a fence before the CS is flushed.
 666      * The user must flush manually to complete the initializaton of the fence.
 667      * The fence must not be used before the flush.
 668      */
 669     struct pipe_fence_handle *(*cs_get_next_fence)(struct radeon_winsys_cs *cs);
 670
 671     /**
 672      * Return true if a buffer is referenced by a command stream.
 673      *
 674      * \param cs        A command stream.
 675      * \param buf       A winsys buffer.
 676      */
 677     bool (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
 678                                     struct pb_buffer *buf,
 679                                     enum radeon_bo_usage usage);
 680
 681     /**
 682      * Request access to a feature for a command stream.
 683      *
 684      * \param cs        A command stream.
 685      * \param fid       Feature ID, one of RADEON_FID_*
 686      * \param enable    Whether to enable or disable the feature.
 687      */
 688     bool (*cs_request_feature)(struct radeon_winsys_cs *cs,
 689                                enum radeon_feature_id fid,
 690                                bool enable);
 691      /**
 692       * Make sure all asynchronous flush of the cs have completed
 693       *
 694       * \param cs        A command stream.
 695       */
 696     void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
 697
 698     /**
 699      * Wait for the fence and return true if the fence has been signalled.
 700      * The timeout of 0 will only return the status.
 701      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 702      * is signalled.
 703      */
 704     bool (*fence_wait)(struct radeon_winsys *ws,
 705                        struct pipe_fence_handle *fence,
 706                        uint64_t timeout);
 707
 708     /**
 709      * Reference counting for fences.
 710      */
 711     void (*fence_reference)(struct pipe_fence_handle **dst,
 712                             struct pipe_fence_handle *src);
 713
 714     /**
 715      * Initialize surface
 716      *
 717      * \param ws        The winsys this function is called from.
 718      * \param surf      Surface structure ptr
 719      */
 720     int (*surface_init)(struct radeon_winsys *ws,
 721                         struct radeon_surf *surf);
 722
 723     /**
 724      * Find best values for a surface
 725      *
 726      * \param ws        The winsys this function is called from.
 727      * \param surf      Surface structure ptr
 728      */
 729     int (*surface_best)(struct radeon_winsys *ws,
 730                         struct radeon_surf *surf);
 731
 732     uint64_t (*query_value)(struct radeon_winsys *ws,
 733                             enum radeon_value_id value);
 734
 735     bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 736                            unsigned num_registers, uint32_t *out);
 737 };
 738
 739 static inline bool radeon_emitted(struct radeon_winsys_cs *cs, unsigned num_dw)
 740 {
 741     return cs && (cs->prev_dw + cs->current.cdw > num_dw);
 742 }
 743
 744 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 745 {
 746     cs->current.buf[cs->current.cdw++] = value;
 747 }
 748
 749 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 750                                      const uint32_t *values, unsigned count)
 751 {
 752     memcpy(cs->current.buf + cs->current.cdw, values, count * 4);
 753     cs->current.cdw += count;
 754 }
 755
 756 #endif