2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2014,2015 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include "radeon/r600_cs.h"
32 #include "util/u_format.h"
34 static uint32_t cik_micro_tile_mode(struct si_screen
*sscreen
, unsigned tile_mode
)
36 if (sscreen
->b
.info
.si_tile_mode_array_valid
) {
37 uint32_t gb_tile_mode
= sscreen
->b
.info
.si_tile_mode_array
[tile_mode
];
39 return G_009910_MICRO_TILE_MODE_NEW(gb_tile_mode
);
42 /* The kernel cannod return the tile mode array. Guess? */
43 return V_009910_ADDR_SURF_THIN_MICRO_TILING
;
46 static void cik_sdma_do_copy_buffer(struct si_context
*ctx
,
47 struct pipe_resource
*dst
,
48 struct pipe_resource
*src
,
53 struct radeon_winsys_cs
*cs
= ctx
->b
.rings
.dma
.cs
;
54 unsigned i
, ncopy
, csize
;
55 struct r600_resource
*rdst
= (struct r600_resource
*)dst
;
56 struct r600_resource
*rsrc
= (struct r600_resource
*)src
;
58 dst_offset
+= r600_resource(dst
)->gpu_address
;
59 src_offset
+= r600_resource(src
)->gpu_address
;
61 ncopy
= (size
+ CIK_SDMA_COPY_MAX_SIZE
- 1) / CIK_SDMA_COPY_MAX_SIZE
;
62 r600_need_dma_space(&ctx
->b
, ncopy
* 7);
64 r600_context_bo_reloc(&ctx
->b
, &ctx
->b
.rings
.dma
, rsrc
, RADEON_USAGE_READ
,
66 r600_context_bo_reloc(&ctx
->b
, &ctx
->b
.rings
.dma
, rdst
, RADEON_USAGE_WRITE
,
69 for (i
= 0; i
< ncopy
; i
++) {
70 csize
= size
< CIK_SDMA_COPY_MAX_SIZE
? size
: CIK_SDMA_COPY_MAX_SIZE
;
71 cs
->buf
[cs
->cdw
++] = CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY
,
72 CIK_SDMA_COPY_SUB_OPCODE_LINEAR
,
74 cs
->buf
[cs
->cdw
++] = csize
;
75 cs
->buf
[cs
->cdw
++] = 0; /* src/dst endian swap */
76 cs
->buf
[cs
->cdw
++] = src_offset
;
77 cs
->buf
[cs
->cdw
++] = src_offset
>> 32;
78 cs
->buf
[cs
->cdw
++] = dst_offset
;
79 cs
->buf
[cs
->cdw
++] = dst_offset
>> 32;
86 static void cik_sdma_copy_buffer(struct si_context
*ctx
,
87 struct pipe_resource
*dst
,
88 struct pipe_resource
*src
,
93 struct r600_resource
*rdst
= (struct r600_resource
*)dst
;
95 /* Mark the buffer range of destination as valid (initialized),
96 * so that transfer_map knows it should wait for the GPU when mapping
98 util_range_add(&rdst
->valid_buffer_range
, dst_offset
,
101 cik_sdma_do_copy_buffer(ctx
, dst
, src
, dst_offset
, src_offset
, size
);
104 static void cik_sdma_copy_tile(struct si_context
*ctx
,
105 struct pipe_resource
*dst
,
107 struct pipe_resource
*src
,
110 unsigned copy_height
,
115 struct radeon_winsys_cs
*cs
= ctx
->b
.rings
.dma
.cs
;
116 struct si_screen
*sscreen
= ctx
->screen
;
117 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
118 struct r600_texture
*rdst
= (struct r600_texture
*)dst
;
119 struct r600_texture
*rlinear
, *rtiled
;
120 unsigned linear_lvl
, tiled_lvl
;
121 unsigned array_mode
, lbpe
, pitch_tile_max
, slice_tile_max
, size
;
122 unsigned ncopy
, height
, cheight
, detile
, i
, src_mode
, dst_mode
;
123 unsigned sub_op
, bank_h
, bank_w
, mt_aspect
, nbanks
, tile_split
, mt
;
125 unsigned pipe_config
, tile_mode_index
;
127 dst_mode
= rdst
->surface
.level
[dst_level
].mode
;
128 src_mode
= rsrc
->surface
.level
[src_level
].mode
;
129 /* downcast linear aligned to linear to simplify test */
130 src_mode
= src_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: src_mode
;
131 dst_mode
= dst_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: dst_mode
;
132 assert(dst_mode
!= src_mode
);
133 assert(src_mode
== RADEON_SURF_MODE_LINEAR
|| dst_mode
== RADEON_SURF_MODE_LINEAR
);
135 sub_op
= CIK_SDMA_COPY_SUB_OPCODE_TILED
;
136 lbpe
= util_logbase2(bpe
);
137 pitch_tile_max
= ((pitch
/ bpe
) / 8) - 1;
139 detile
= dst_mode
== RADEON_SURF_MODE_LINEAR
;
140 rlinear
= detile
? rdst
: rsrc
;
141 rtiled
= detile
? rsrc
: rdst
;
142 linear_lvl
= detile
? dst_level
: src_level
;
143 tiled_lvl
= detile
? src_level
: dst_level
;
145 assert(!util_format_is_depth_and_stencil(rtiled
->resource
.b
.b
.format
));
147 array_mode
= si_array_mode(rtiled
->surface
.level
[tiled_lvl
].mode
);
148 slice_tile_max
= (rtiled
->surface
.level
[tiled_lvl
].nblk_x
*
149 rtiled
->surface
.level
[tiled_lvl
].nblk_y
) / (8*8) - 1;
150 height
= rlinear
->surface
.level
[linear_lvl
].nblk_y
;
151 base
= rtiled
->surface
.level
[tiled_lvl
].offset
;
152 addr
= rlinear
->surface
.level
[linear_lvl
].offset
;
153 bank_h
= cik_bank_wh(rtiled
->surface
.bankh
);
154 bank_w
= cik_bank_wh(rtiled
->surface
.bankw
);
155 mt_aspect
= cik_macro_tile_aspect(rtiled
->surface
.mtilea
);
156 tile_split
= cik_tile_split(rtiled
->surface
.tile_split
);
157 tile_mode_index
= si_tile_mode_index(rtiled
, tiled_lvl
, false);
158 nbanks
= si_num_banks(sscreen
, rtiled
);
159 base
+= rtiled
->resource
.gpu_address
;
160 addr
+= rlinear
->resource
.gpu_address
;
162 pipe_config
= cik_db_pipe_config(sscreen
, tile_mode_index
);
163 mt
= cik_micro_tile_mode(sscreen
, tile_mode_index
);
165 size
= (copy_height
* pitch
) / 4;
166 cheight
= copy_height
;
167 if (((cheight
* pitch
) / 4) > CIK_SDMA_COPY_MAX_SIZE
) {
168 cheight
= (CIK_SDMA_COPY_MAX_SIZE
* 4) / pitch
;
169 cheight
&= ~(y_align
- 1);
171 ncopy
= (copy_height
+ cheight
- 1) / cheight
;
172 r600_need_dma_space(&ctx
->b
, ncopy
* 12);
174 r600_context_bo_reloc(&ctx
->b
, &ctx
->b
.rings
.dma
, &rsrc
->resource
,
175 RADEON_USAGE_READ
, RADEON_PRIO_MIN
);
176 r600_context_bo_reloc(&ctx
->b
, &ctx
->b
.rings
.dma
, &rdst
->resource
,
177 RADEON_USAGE_WRITE
, RADEON_PRIO_MIN
);
179 copy_height
= size
* 4 / pitch
;
180 for (i
= 0; i
< ncopy
; i
++) {
181 cheight
= copy_height
;
182 if (((cheight
* pitch
) / 4) > CIK_SDMA_COPY_MAX_SIZE
) {
183 cheight
= (CIK_SDMA_COPY_MAX_SIZE
* 4) / pitch
;
184 cheight
&= ~(y_align
- 1);
186 size
= (cheight
* pitch
) / 4;
188 cs
->buf
[cs
->cdw
++] = CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY
,
189 sub_op
, detile
<< 15);
190 cs
->buf
[cs
->cdw
++] = base
;
191 cs
->buf
[cs
->cdw
++] = base
>> 32;
192 cs
->buf
[cs
->cdw
++] = ((height
- 1) << 16) | pitch_tile_max
;
193 cs
->buf
[cs
->cdw
++] = slice_tile_max
;
194 cs
->buf
[cs
->cdw
++] = (pipe_config
<< 26) | (mt_aspect
<< 24) |
195 (nbanks
<< 21) | (bank_h
<< 18) | (bank_w
<< 15) |
196 (tile_split
<< 11) | (mt
<< 8) | (array_mode
<< 3) |
198 cs
->buf
[cs
->cdw
++] = y
<< 16; /* | x */
199 cs
->buf
[cs
->cdw
++] = 0; /* z */;
200 cs
->buf
[cs
->cdw
++] = addr
& 0xfffffffc;
201 cs
->buf
[cs
->cdw
++] = addr
>> 32;
202 cs
->buf
[cs
->cdw
++] = (pitch
/ bpe
) - 1;
203 cs
->buf
[cs
->cdw
++] = size
;
205 copy_height
-= cheight
;
210 void cik_sdma_copy(struct pipe_context
*ctx
,
211 struct pipe_resource
*dst
,
213 unsigned dstx
, unsigned dsty
, unsigned dstz
,
214 struct pipe_resource
*src
,
216 const struct pipe_box
*src_box
)
218 struct si_context
*sctx
= (struct si_context
*)ctx
;
219 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
220 struct r600_texture
*rdst
= (struct r600_texture
*)dst
;
221 unsigned dst_pitch
, src_pitch
, bpe
, dst_mode
, src_mode
;
222 unsigned src_w
, dst_w
;
223 unsigned src_x
, src_y
;
224 unsigned copy_height
, y_align
;
225 unsigned dst_x
= dstx
, dst_y
= dsty
, dst_z
= dstz
;
227 if (sctx
->b
.rings
.dma
.cs
== NULL
) {
231 if (dst
->target
== PIPE_BUFFER
&& src
->target
== PIPE_BUFFER
) {
232 cik_sdma_copy_buffer(sctx
, dst
, src
, dst_x
, src_box
->x
, src_box
->width
);
236 /* Before re-enabling this, please make sure you can hit all newly
237 * enabled paths in your testing, preferably with both piglit (in
238 * particular the streaming-texture-leak test) and real world apps
239 * (e.g. the UE4 Elemental demo).
243 if (src
->format
!= dst
->format
||
244 rdst
->surface
.nsamples
> 1 || rsrc
->surface
.nsamples
> 1 ||
245 rdst
->dirty_level_mask
& (1 << dst_level
)) {
249 if (rsrc
->dirty_level_mask
& (1 << src_level
)) {
250 if (rsrc
->htile_buffer
)
253 ctx
->flush_resource(ctx
, src
);
256 src_x
= util_format_get_nblocksx(src
->format
, src_box
->x
);
257 dst_x
= util_format_get_nblocksx(src
->format
, dst_x
);
258 src_y
= util_format_get_nblocksy(src
->format
, src_box
->y
);
259 dst_y
= util_format_get_nblocksy(src
->format
, dst_y
);
261 dst_pitch
= rdst
->surface
.level
[dst_level
].pitch_bytes
;
262 src_pitch
= rsrc
->surface
.level
[src_level
].pitch_bytes
;
263 src_w
= rsrc
->surface
.level
[src_level
].npix_x
;
264 dst_w
= rdst
->surface
.level
[dst_level
].npix_x
;
266 if (src_pitch
!= dst_pitch
|| src_box
->x
|| dst_x
|| src_w
!= dst_w
||
267 src_box
->width
!= src_w
||
268 rsrc
->surface
.level
[src_level
].nblk_y
!=
269 rdst
->surface
.level
[dst_level
].nblk_y
) {
270 /* FIXME CIK can do partial blit */
274 bpe
= rdst
->surface
.bpe
;
275 copy_height
= src_box
->height
/ rsrc
->surface
.blk_h
;
276 dst_mode
= rdst
->surface
.level
[dst_level
].mode
;
277 src_mode
= rsrc
->surface
.level
[src_level
].mode
;
278 /* downcast linear aligned to linear to simplify test */
279 src_mode
= src_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: src_mode
;
280 dst_mode
= dst_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: dst_mode
;
282 /* Dimensions must be aligned to (macro)tiles */
283 switch (src_mode
== RADEON_SURF_MODE_LINEAR
? dst_mode
: src_mode
) {
284 case RADEON_SURF_MODE_1D
:
285 if ((src_x
% 8) || (src_y
% 8) || (dst_x
% 8) || (dst_y
% 8) ||
290 case RADEON_SURF_MODE_2D
: {
291 unsigned mtilew
, mtileh
, num_banks
;
293 switch (si_num_banks(sctx
->screen
, rsrc
)) {
294 case V_02803C_ADDR_SURF_2_BANK
:
298 case V_02803C_ADDR_SURF_4_BANK
:
301 case V_02803C_ADDR_SURF_8_BANK
:
304 case V_02803C_ADDR_SURF_16_BANK
:
309 mtilew
= (8 * rsrc
->surface
.bankw
*
310 sctx
->screen
->b
.tiling_info
.num_channels
) *
311 rsrc
->surface
.mtilea
;
312 assert(!(mtilew
& (mtilew
- 1)));
313 mtileh
= (8 * rsrc
->surface
.bankh
* num_banks
) /
314 rsrc
->surface
.mtilea
;
315 assert(!(mtileh
& (mtileh
- 1)));
317 if ((src_x
& (mtilew
- 1)) || (src_y
& (mtileh
- 1)) ||
318 (dst_x
& (mtilew
- 1)) || (dst_y
& (mtileh
- 1)) ||
319 (copy_height
& (mtileh
- 1)))
329 if (src_mode
== dst_mode
) {
330 uint64_t dst_offset
, src_offset
;
331 unsigned src_h
, dst_h
;
333 src_h
= rsrc
->surface
.level
[src_level
].npix_y
;
334 dst_h
= rdst
->surface
.level
[dst_level
].npix_y
;
336 if (src_box
->depth
> 1 &&
337 (src_y
|| dst_y
|| src_h
!= dst_h
|| src_box
->height
!= src_h
))
340 /* simple dma blit would do NOTE code here assume :
341 * dst_pitch == src_pitch
343 src_offset
= rsrc
->surface
.level
[src_level
].offset
;
344 src_offset
+= rsrc
->surface
.level
[src_level
].slice_size
* src_box
->z
;
345 src_offset
+= src_y
* src_pitch
+ src_x
* bpe
;
346 dst_offset
= rdst
->surface
.level
[dst_level
].offset
;
347 dst_offset
+= rdst
->surface
.level
[dst_level
].slice_size
* dst_z
;
348 dst_offset
+= dst_y
* dst_pitch
+ dst_x
* bpe
;
349 cik_sdma_do_copy_buffer(sctx
, dst
, src
, dst_offset
, src_offset
,
351 rsrc
->surface
.level
[src_level
].slice_size
);
353 if (dst_y
!= src_y
|| src_box
->depth
> 1 || src_box
->z
|| dst_z
)
356 cik_sdma_copy_tile(sctx
, dst
, dst_level
, src
, src_level
,
357 src_y
, copy_height
, y_align
, dst_pitch
, bpe
);
362 si_resource_copy_region(ctx
, dst
, dst_level
, dstx
, dsty
, dstz
,
363 src
, src_level
, src_box
);