src/gallium/drivers/radeonsi/cik_sdma.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  * Copyright 2015 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * on the rights to use, copy, modify, merge, publish, distribute, sub
  10  * license, and/or sell copies of the Software, and to permit persons to whom
  11  * the Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  21  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  22  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include "sid.h"
  27 #include "si_pipe.h"
  28
  29 static void cik_sdma_copy_buffer(struct si_context *ctx,
  30                                  struct pipe_resource *dst,
  31                                  struct pipe_resource *src,
  32                                  uint64_t dst_offset,
  33                                  uint64_t src_offset,
  34                                  uint64_t size)
  35 {
  36         struct radeon_cmdbuf *cs = ctx->dma_cs;
  37         unsigned i, ncopy, csize;
  38         unsigned align = ~0u;
  39         struct si_resource *sdst = si_resource(dst);
  40         struct si_resource *ssrc = si_resource(src);
  41
  42         /* Mark the buffer range of destination as valid (initialized),
  43          * so that transfer_map knows it should wait for the GPU when mapping
  44          * that range. */
  45         util_range_add(dst, &sdst->valid_buffer_range, dst_offset,
  46                        dst_offset + size);
  47
  48         dst_offset += sdst->gpu_address;
  49         src_offset += ssrc->gpu_address;
  50
  51         ncopy = DIV_ROUND_UP(size, CIK_SDMA_COPY_MAX_SIZE);
  52
  53         /* Align copy size to dw if src/dst address are dw aligned */
  54         if ((src_offset & 0x3) == 0 &&
  55             (dst_offset & 0x3) == 0 &&
  56             size > 4 &&
  57             (size & 3) != 0) {
  58                 align = ~0x3u;
  59                 ncopy++;
  60         }
  61
  62         si_need_dma_space(ctx, ncopy * 7, sdst, ssrc);
  63
  64         for (i = 0; i < ncopy; i++) {
  65                 csize = size >= 4 ? MIN2(size & align, CIK_SDMA_COPY_MAX_SIZE) : size;
  66                 radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
  67                                                 CIK_SDMA_COPY_SUB_OPCODE_LINEAR,
  68                                                 0));
  69                 radeon_emit(cs, ctx->chip_class >= GFX9 ? csize - 1 : csize);
  70                 radeon_emit(cs, 0); /* src/dst endian swap */
  71                 radeon_emit(cs, src_offset);
  72                 radeon_emit(cs, src_offset >> 32);
  73                 radeon_emit(cs, dst_offset);
  74                 radeon_emit(cs, dst_offset >> 32);
  75                 dst_offset += csize;
  76                 src_offset += csize;
  77                 size -= csize;
  78         }
  79 }
  80
  81 static unsigned minify_as_blocks(unsigned width, unsigned level, unsigned blk_w)
  82 {
  83         width = u_minify(width, level);
  84         return DIV_ROUND_UP(width, blk_w);
  85 }
  86
  87 static unsigned encode_tile_info(struct si_context *sctx,
  88                                  struct si_texture *tex, unsigned level,
  89                                  bool set_bpp)
  90 {
  91         struct radeon_info *info = &sctx->screen->info;
  92         unsigned tile_index = tex->surface.u.legacy.tiling_index[level];
  93         unsigned macro_tile_index = tex->surface.u.legacy.macro_tile_index;
  94         unsigned tile_mode = info->si_tile_mode_array[tile_index];
  95         unsigned macro_tile_mode = info->cik_macrotile_mode_array[macro_tile_index];
  96
  97         return (set_bpp ? util_logbase2(tex->surface.bpe) : 0) |
  98                 (G_009910_ARRAY_MODE(tile_mode) << 3) |
  99                 (G_009910_MICRO_TILE_MODE_NEW(tile_mode) << 8) |
 100                 /* Non-depth modes don't have TILE_SPLIT set. */
 101                 ((util_logbase2(tex->surface.u.legacy.tile_split >> 6)) << 11) |
 102                 (G_009990_BANK_WIDTH(macro_tile_mode) << 15) |
 103                 (G_009990_BANK_HEIGHT(macro_tile_mode) << 18) |
 104                 (G_009990_NUM_BANKS(macro_tile_mode) << 21) |
 105                 (G_009990_MACRO_TILE_ASPECT(macro_tile_mode) << 24) |
 106                 (G_009910_PIPE_CONFIG(tile_mode) << 26);
 107 }
 108
 109 static bool cik_sdma_copy_texture(struct si_context *sctx,
 110                                   struct pipe_resource *dst,
 111                                   unsigned dst_level,
 112                                   unsigned dstx, unsigned dsty, unsigned dstz,
 113                                   struct pipe_resource *src,
 114                                   unsigned src_level,
 115                                   const struct pipe_box *src_box)
 116 {
 117         struct radeon_info *info = &sctx->screen->info;
 118         struct si_texture *ssrc = (struct si_texture*)src;
 119         struct si_texture *sdst = (struct si_texture*)dst;
 120         unsigned bpp = sdst->surface.bpe;
 121         uint64_t dst_address = sdst->buffer.gpu_address +
 122                                sdst->surface.u.legacy.level[dst_level].offset;
 123         uint64_t src_address = ssrc->buffer.gpu_address +
 124                                ssrc->surface.u.legacy.level[src_level].offset;
 125         unsigned dst_mode = sdst->surface.u.legacy.level[dst_level].mode;
 126         unsigned src_mode = ssrc->surface.u.legacy.level[src_level].mode;
 127         unsigned dst_tile_index = sdst->surface.u.legacy.tiling_index[dst_level];
 128         unsigned src_tile_index = ssrc->surface.u.legacy.tiling_index[src_level];
 129         unsigned dst_tile_mode = info->si_tile_mode_array[dst_tile_index];
 130         unsigned src_tile_mode = info->si_tile_mode_array[src_tile_index];
 131         unsigned dst_micro_mode = G_009910_MICRO_TILE_MODE_NEW(dst_tile_mode);
 132         unsigned src_micro_mode = G_009910_MICRO_TILE_MODE_NEW(src_tile_mode);
 133         unsigned dst_tile_swizzle = dst_mode == RADEON_SURF_MODE_2D ?
 134                                             sdst->surface.tile_swizzle : 0;
 135         unsigned src_tile_swizzle = src_mode == RADEON_SURF_MODE_2D ?
 136                                             ssrc->surface.tile_swizzle : 0;
 137         unsigned dst_pitch = sdst->surface.u.legacy.level[dst_level].nblk_x;
 138         unsigned src_pitch = ssrc->surface.u.legacy.level[src_level].nblk_x;
 139         uint64_t dst_slice_pitch = ((uint64_t)sdst->surface.u.legacy.level[dst_level].slice_size_dw * 4) / bpp;
 140         uint64_t src_slice_pitch = ((uint64_t)ssrc->surface.u.legacy.level[src_level].slice_size_dw * 4) / bpp;
 141         unsigned dst_width = minify_as_blocks(sdst->buffer.b.b.width0,
 142                                               dst_level, sdst->surface.blk_w);
 143         unsigned src_width = minify_as_blocks(ssrc->buffer.b.b.width0,
 144                                               src_level, ssrc->surface.blk_w);
 145         unsigned dst_height = minify_as_blocks(sdst->buffer.b.b.height0,
 146                                                dst_level, sdst->surface.blk_h);
 147         unsigned src_height = minify_as_blocks(ssrc->buffer.b.b.height0,
 148                                                src_level, ssrc->surface.blk_h);
 149         unsigned srcx = src_box->x / ssrc->surface.blk_w;
 150         unsigned srcy = src_box->y / ssrc->surface.blk_h;
 151         unsigned srcz = src_box->z;
 152         unsigned copy_width = DIV_ROUND_UP(src_box->width, ssrc->surface.blk_w);
 153         unsigned copy_height = DIV_ROUND_UP(src_box->height, ssrc->surface.blk_h);
 154         unsigned copy_depth = src_box->depth;
 155
 156         assert(src_level <= src->last_level);
 157         assert(dst_level <= dst->last_level);
 158         assert(sdst->surface.u.legacy.level[dst_level].offset +
 159                dst_slice_pitch * bpp * (dstz + src_box->depth) <=
 160                sdst->buffer.buf->size);
 161         assert(ssrc->surface.u.legacy.level[src_level].offset +
 162                src_slice_pitch * bpp * (srcz + src_box->depth) <=
 163                ssrc->buffer.buf->size);
 164
 165         if (!si_prepare_for_dma_blit(sctx, sdst, dst_level, dstx, dsty,
 166                                      dstz, ssrc, src_level, src_box))
 167                 return false;
 168
 169         dstx /= sdst->surface.blk_w;
 170         dsty /= sdst->surface.blk_h;
 171
 172         if (srcx >= (1 << 14) ||
 173             srcy >= (1 << 14) ||
 174             srcz >= (1 << 11) ||
 175             dstx >= (1 << 14) ||
 176             dsty >= (1 << 14) ||
 177             dstz >= (1 << 11))
 178                 return false;
 179
 180         dst_address |= dst_tile_swizzle << 8;
 181         src_address |= src_tile_swizzle << 8;
 182
 183         /* Linear -> linear sub-window copy. */
 184         if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED &&
 185             src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED &&
 186             /* check if everything fits into the bitfields */
 187             src_pitch <= (1 << 14) &&
 188             dst_pitch <= (1 << 14) &&
 189             src_slice_pitch <= (1 << 28) &&
 190             dst_slice_pitch <= (1 << 28) &&
 191             copy_width <= (1 << 14) &&
 192             copy_height <= (1 << 14) &&
 193             copy_depth <= (1 << 11) &&
 194             /* HW limitation - GFX7: */
 195             (sctx->chip_class != GFX7 ||
 196              (copy_width < (1 << 14) &&
 197               copy_height < (1 << 14) &&
 198               copy_depth < (1 << 11))) &&
 199             /* HW limitation - some GFX7 parts: */
 200             ((sctx->family != CHIP_BONAIRE &&
 201               sctx->family != CHIP_KAVERI) ||
 202              (srcx + copy_width != (1 << 14) &&
 203               srcy + copy_height != (1 << 14)))) {
 204                 struct radeon_cmdbuf *cs = sctx->dma_cs;
 205
 206                 si_need_dma_space(sctx, 13, &sdst->buffer, &ssrc->buffer);
 207
 208                 radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
 209                                                 CIK_SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW, 0) |
 210                             (util_logbase2(bpp) << 29));
 211                 radeon_emit(cs, src_address);
 212                 radeon_emit(cs, src_address >> 32);
 213                 radeon_emit(cs, srcx | (srcy << 16));
 214                 radeon_emit(cs, srcz | ((src_pitch - 1) << 16));
 215                 radeon_emit(cs, src_slice_pitch - 1);
 216                 radeon_emit(cs, dst_address);
 217                 radeon_emit(cs, dst_address >> 32);
 218                 radeon_emit(cs, dstx | (dsty << 16));
 219                 radeon_emit(cs, dstz | ((dst_pitch - 1) << 16));
 220                 radeon_emit(cs, dst_slice_pitch - 1);
 221                 if (sctx->chip_class == GFX7) {
 222                         radeon_emit(cs, copy_width | (copy_height << 16));
 223                         radeon_emit(cs, copy_depth);
 224                 } else {
 225                         radeon_emit(cs, (copy_width - 1) | ((copy_height - 1) << 16));
 226                         radeon_emit(cs, (copy_depth - 1));
 227                 }
 228                 return true;
 229         }
 230
 231         /* Tiled <-> linear sub-window copy. */
 232         if ((src_mode >= RADEON_SURF_MODE_1D) != (dst_mode >= RADEON_SURF_MODE_1D)) {
 233                 struct si_texture *tiled = src_mode >= RADEON_SURF_MODE_1D ? ssrc : sdst;
 234                 struct si_texture *linear = tiled == ssrc ? sdst : ssrc;
 235                 unsigned tiled_level =  tiled   == ssrc ? src_level : dst_level;
 236                 unsigned linear_level = linear  == ssrc ? src_level : dst_level;
 237                 unsigned tiled_x =      tiled   == ssrc ? srcx : dstx;
 238                 unsigned linear_x =     linear  == ssrc ? srcx : dstx;
 239                 unsigned tiled_y =      tiled   == ssrc ? srcy : dsty;
 240                 unsigned linear_y =     linear  == ssrc ? srcy : dsty;
 241                 unsigned tiled_z =      tiled   == ssrc ? srcz : dstz;
 242                 unsigned linear_z =     linear  == ssrc ? srcz : dstz;
 243                 unsigned tiled_width =  tiled   == ssrc ? src_width : dst_width;
 244                 unsigned linear_width = linear  == ssrc ? src_width : dst_width;
 245                 unsigned tiled_pitch =  tiled   == ssrc ? src_pitch : dst_pitch;
 246                 unsigned linear_pitch = linear  == ssrc ? src_pitch : dst_pitch;
 247                 unsigned tiled_slice_pitch  = tiled  == ssrc ? src_slice_pitch : dst_slice_pitch;
 248                 unsigned linear_slice_pitch = linear == ssrc ? src_slice_pitch : dst_slice_pitch;
 249                 uint64_t tiled_address =  tiled  == ssrc ? src_address : dst_address;
 250                 uint64_t linear_address = linear == ssrc ? src_address : dst_address;
 251                 unsigned tiled_micro_mode = tiled == ssrc ? src_micro_mode : dst_micro_mode;
 252
 253                 assert(tiled_pitch % 8 == 0);
 254                 assert(tiled_slice_pitch % 64 == 0);
 255                 unsigned pitch_tile_max = tiled_pitch / 8 - 1;
 256                 unsigned slice_tile_max = tiled_slice_pitch / 64 - 1;
 257                 unsigned xalign = MAX2(1, 4 / bpp);
 258                 unsigned copy_width_aligned = copy_width;
 259
 260                 /* If the region ends at the last pixel and is unaligned, we
 261                  * can copy the remainder of the line that is not visible to
 262                  * make it aligned.
 263                  */
 264                 if (copy_width % xalign != 0 &&
 265                     linear_x + copy_width == linear_width &&
 266                     tiled_x  + copy_width == tiled_width &&
 267                     linear_x + align(copy_width, xalign) <= linear_pitch &&
 268                     tiled_x  + align(copy_width, xalign) <= tiled_pitch)
 269                         copy_width_aligned = align(copy_width, xalign);
 270
 271                 /* HW limitations. */
 272                 if ((sctx->family == CHIP_BONAIRE ||
 273                      sctx->family == CHIP_KAVERI) &&
 274                     linear_pitch - 1 == 0x3fff &&
 275                     bpp == 16)
 276                         return false;
 277
 278                 if (sctx->chip_class == GFX7 &&
 279                     (copy_width_aligned == (1 << 14) ||
 280                      copy_height == (1 << 14) ||
 281                      copy_depth == (1 << 11)))
 282                         return false;
 283
 284                 if ((sctx->family == CHIP_BONAIRE ||
 285                      sctx->family == CHIP_KAVERI ||
 286                      sctx->family == CHIP_KABINI) &&
 287                     (tiled_x + copy_width == (1 << 14) ||
 288                      tiled_y + copy_height == (1 << 14)))
 289                         return false;
 290
 291                 /* The hw can read outside of the given linear buffer bounds,
 292                  * or access those pages but not touch the memory in case
 293                  * of writes. (it still causes a VM fault)
 294                  *
 295                  * Out-of-bounds memory access or page directory access must
 296                  * be prevented.
 297                  */
 298                 int64_t start_linear_address, end_linear_address;
 299                 unsigned granularity;
 300
 301                 /* Deduce the size of reads from the linear surface. */
 302                 switch (tiled_micro_mode) {
 303                 case V_009910_ADDR_SURF_DISPLAY_MICRO_TILING:
 304                         granularity = bpp == 1 ? 64 / (8*bpp) :
 305                                                  128 / (8*bpp);
 306                         break;
 307                 case V_009910_ADDR_SURF_THIN_MICRO_TILING:
 308                 case V_009910_ADDR_SURF_DEPTH_MICRO_TILING:
 309                         if (0 /* TODO: THICK microtiling */)
 310                                 granularity = bpp == 1 ? 32 / (8*bpp) :
 311                                               bpp == 2 ? 64 / (8*bpp) :
 312                                               bpp <= 8 ? 128 / (8*bpp) :
 313                                                          256 / (8*bpp);
 314                         else
 315                                 granularity = bpp <= 2 ? 64 / (8*bpp) :
 316                                               bpp <= 8 ? 128 / (8*bpp) :
 317                                                          256 / (8*bpp);
 318                         break;
 319                 default:
 320                         return false;
 321                 }
 322
 323                 /* The linear reads start at tiled_x & ~(granularity - 1).
 324                  * If linear_x == 0 && tiled_x % granularity != 0, the hw
 325                  * starts reading from an address preceding linear_address!!!
 326                  */
 327                 start_linear_address =
 328                         linear->surface.u.legacy.level[linear_level].offset +
 329                         bpp * (linear_z * linear_slice_pitch +
 330                                linear_y * linear_pitch +
 331                                linear_x);
 332                 start_linear_address -= (int)(bpp * (tiled_x % granularity));
 333
 334                 end_linear_address =
 335                         linear->surface.u.legacy.level[linear_level].offset +
 336                         bpp * ((linear_z + copy_depth - 1) * linear_slice_pitch +
 337                                (linear_y + copy_height - 1) * linear_pitch +
 338                                (linear_x + copy_width));
 339
 340                 if ((tiled_x + copy_width) % granularity)
 341                         end_linear_address += granularity -
 342                                               (tiled_x + copy_width) % granularity;
 343
 344                 if (start_linear_address < 0 ||
 345                     end_linear_address > linear->surface.surf_size)
 346                         return false;
 347
 348                 /* Check requirements. */
 349                 if (tiled_address % 256 == 0 &&
 350                     linear_address % 4 == 0 &&
 351                     linear_pitch % xalign == 0 &&
 352                     linear_x % xalign == 0 &&
 353                     tiled_x % xalign == 0 &&
 354                     copy_width_aligned % xalign == 0 &&
 355                     tiled_micro_mode != V_009910_ADDR_SURF_ROTATED_MICRO_TILING &&
 356                     /* check if everything fits into the bitfields */
 357                     tiled->surface.u.legacy.tile_split <= 4096 &&
 358                     pitch_tile_max < (1 << 11) &&
 359                     slice_tile_max < (1 << 22) &&
 360                     linear_pitch <= (1 << 14) &&
 361                     linear_slice_pitch <= (1 << 28) &&
 362                     copy_width_aligned <= (1 << 14) &&
 363                     copy_height <= (1 << 14) &&
 364                     copy_depth <= (1 << 11)) {
 365                         struct radeon_cmdbuf *cs = sctx->dma_cs;
 366                         uint32_t direction = linear == sdst ? 1u << 31 : 0;
 367
 368                         si_need_dma_space(sctx, 14, &sdst->buffer, &ssrc->buffer);
 369
 370                         radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
 371                                                         CIK_SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW, 0) |
 372                                         direction);
 373                         radeon_emit(cs, tiled_address);
 374                         radeon_emit(cs, tiled_address >> 32);
 375                         radeon_emit(cs, tiled_x | (tiled_y << 16));
 376                         radeon_emit(cs, tiled_z | (pitch_tile_max << 16));
 377                         radeon_emit(cs, slice_tile_max);
 378                         radeon_emit(cs, encode_tile_info(sctx, tiled, tiled_level, true));
 379                         radeon_emit(cs, linear_address);
 380                         radeon_emit(cs, linear_address >> 32);
 381                         radeon_emit(cs, linear_x | (linear_y << 16));
 382                         radeon_emit(cs, linear_z | ((linear_pitch - 1) << 16));
 383                         radeon_emit(cs, linear_slice_pitch - 1);
 384                         if (sctx->chip_class == GFX7) {
 385                                 radeon_emit(cs, copy_width_aligned | (copy_height << 16));
 386                                 radeon_emit(cs, copy_depth);
 387                         } else {
 388                                 radeon_emit(cs, (copy_width_aligned - 1) | ((copy_height - 1) << 16));
 389                                 radeon_emit(cs, (copy_depth - 1));
 390                         }
 391                         return true;
 392                 }
 393         }
 394
 395         /* Tiled -> Tiled sub-window copy. */
 396         if (dst_mode >= RADEON_SURF_MODE_1D &&
 397             src_mode >= RADEON_SURF_MODE_1D &&
 398             /* check if these fit into the bitfields */
 399             src_address % 256 == 0 &&
 400             dst_address % 256 == 0 &&
 401             ssrc->surface.u.legacy.tile_split <= 4096 &&
 402             sdst->surface.u.legacy.tile_split <= 4096 &&
 403             dstx % 8 == 0 &&
 404             dsty % 8 == 0 &&
 405             srcx % 8 == 0 &&
 406             srcy % 8 == 0 &&
 407             /* this can either be equal, or display->rotated (GFX8+ only) */
 408             (src_micro_mode == dst_micro_mode ||
 409              (sctx->chip_class >= GFX8 &&
 410               src_micro_mode == V_009910_ADDR_SURF_DISPLAY_MICRO_TILING &&
 411               dst_micro_mode == V_009910_ADDR_SURF_ROTATED_MICRO_TILING))) {
 412                 assert(src_pitch % 8 == 0);
 413                 assert(dst_pitch % 8 == 0);
 414                 assert(src_slice_pitch % 64 == 0);
 415                 assert(dst_slice_pitch % 64 == 0);
 416                 unsigned src_pitch_tile_max = src_pitch / 8 - 1;
 417                 unsigned dst_pitch_tile_max = dst_pitch / 8 - 1;
 418                 unsigned src_slice_tile_max = src_slice_pitch / 64 - 1;
 419                 unsigned dst_slice_tile_max = dst_slice_pitch / 64 - 1;
 420                 unsigned copy_width_aligned = copy_width;
 421                 unsigned copy_height_aligned = copy_height;
 422
 423                 /* If the region ends at the last pixel and is unaligned, we
 424                  * can copy the remainder of the tile that is not visible to
 425                  * make it aligned.
 426                  */
 427                 if (copy_width % 8 != 0 &&
 428                     srcx + copy_width == src_width &&
 429                     dstx + copy_width == dst_width)
 430                         copy_width_aligned = align(copy_width, 8);
 431
 432                 if (copy_height % 8 != 0 &&
 433                     srcy + copy_height == src_height &&
 434                     dsty + copy_height == dst_height)
 435                         copy_height_aligned = align(copy_height, 8);
 436
 437                 /* check if these fit into the bitfields */
 438                 if (src_pitch_tile_max < (1 << 11) &&
 439                     dst_pitch_tile_max < (1 << 11) &&
 440                     src_slice_tile_max < (1 << 22) &&
 441                     dst_slice_tile_max < (1 << 22) &&
 442                     copy_width_aligned <= (1 << 14) &&
 443                     copy_height_aligned <= (1 << 14) &&
 444                     copy_depth <= (1 << 11) &&
 445                     copy_width_aligned % 8 == 0 &&
 446                     copy_height_aligned % 8 == 0 &&
 447                     /* HW limitation - GFX7: */
 448                     (sctx->chip_class != GFX7 ||
 449                      (copy_width_aligned < (1 << 14) &&
 450                       copy_height_aligned < (1 << 14) &&
 451                       copy_depth < (1 << 11))) &&
 452                     /* HW limitation - some GFX7 parts: */
 453                     ((sctx->family != CHIP_BONAIRE &&
 454                       sctx->family != CHIP_KAVERI &&
 455                       sctx->family != CHIP_KABINI) ||
 456                      (srcx + copy_width_aligned != (1 << 14) &&
 457                       srcy + copy_height_aligned != (1 << 14) &&
 458                       dstx + copy_width != (1 << 14)))) {
 459                         struct radeon_cmdbuf *cs = sctx->dma_cs;
 460
 461                         si_need_dma_space(sctx, 15, &sdst->buffer, &ssrc->buffer);
 462
 463                         radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
 464                                                         CIK_SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW, 0));
 465                         radeon_emit(cs, src_address);
 466                         radeon_emit(cs, src_address >> 32);
 467                         radeon_emit(cs, srcx | (srcy << 16));
 468                         radeon_emit(cs, srcz | (src_pitch_tile_max << 16));
 469                         radeon_emit(cs, src_slice_tile_max);
 470                         radeon_emit(cs, encode_tile_info(sctx, ssrc, src_level, true));
 471                         radeon_emit(cs, dst_address);
 472                         radeon_emit(cs, dst_address >> 32);
 473                         radeon_emit(cs, dstx | (dsty << 16));
 474                         radeon_emit(cs, dstz | (dst_pitch_tile_max << 16));
 475                         radeon_emit(cs, dst_slice_tile_max);
 476                         radeon_emit(cs, encode_tile_info(sctx, sdst, dst_level, false));
 477                         if (sctx->chip_class == GFX7) {
 478                                 radeon_emit(cs, copy_width_aligned |
 479                                                 (copy_height_aligned << 16));
 480                                 radeon_emit(cs, copy_depth);
 481                         } else {
 482                                 radeon_emit(cs, (copy_width_aligned - 8) |
 483                                                 ((copy_height_aligned - 8) << 16));
 484                                 radeon_emit(cs, (copy_depth - 1));
 485                         }
 486                         return true;
 487                 }
 488         }
 489
 490         return false;
 491 }
 492
 493 static void cik_sdma_copy(struct pipe_context *ctx,
 494                           struct pipe_resource *dst,
 495                           unsigned dst_level,
 496                           unsigned dstx, unsigned dsty, unsigned dstz,
 497                           struct pipe_resource *src,
 498                           unsigned src_level,
 499                           const struct pipe_box *src_box)
 500 {
 501         struct si_context *sctx = (struct si_context *)ctx;
 502
 503         if (!sctx->dma_cs ||
 504             src->flags & PIPE_RESOURCE_FLAG_SPARSE ||
 505             dst->flags & PIPE_RESOURCE_FLAG_SPARSE)
 506                 goto fallback;
 507
 508         /* If src is a buffer and dst is a texture, we are uploading metadata. */
 509         if (src->target == PIPE_BUFFER) {
 510                 cik_sdma_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width);
 511                 return;
 512         }
 513
 514         /* SDMA causes corruption. See:
 515          *   https://bugs.freedesktop.org/show_bug.cgi?id=110575
 516          *   https://bugs.freedesktop.org/show_bug.cgi?id=110635
 517          *
 518          * Keep SDMA enabled on APUs.
 519          */
 520         if ((sctx->screen->debug_flags & DBG(FORCE_DMA) ||
 521              !sctx->screen->info.has_dedicated_vram) &&
 522             (sctx->chip_class == GFX7 || sctx->chip_class == GFX8) &&
 523             cik_sdma_copy_texture(sctx, dst, dst_level, dstx, dsty, dstz,
 524                                   src, src_level, src_box))
 525                 return;
 526
 527 fallback:
 528         si_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
 529                                 src, src_level, src_box);
 530 }
 531
 532 void cik_init_sdma_functions(struct si_context *sctx)
 533 {
 534         sctx->dma_copy = cik_sdma_copy;
 535 }