2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2015 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 static unsigned minify_as_blocks(unsigned width
, unsigned level
, unsigned blk_w
)
31 width
= u_minify(width
, level
);
32 return DIV_ROUND_UP(width
, blk_w
);
35 static unsigned encode_tile_info(struct si_context
*sctx
, struct si_texture
*tex
, unsigned level
,
38 struct radeon_info
*info
= &sctx
->screen
->info
;
39 unsigned tile_index
= tex
->surface
.u
.legacy
.tiling_index
[level
];
40 unsigned macro_tile_index
= tex
->surface
.u
.legacy
.macro_tile_index
;
41 unsigned tile_mode
= info
->si_tile_mode_array
[tile_index
];
42 unsigned macro_tile_mode
= info
->cik_macrotile_mode_array
[macro_tile_index
];
44 return (set_bpp
? util_logbase2(tex
->surface
.bpe
) : 0) | (G_009910_ARRAY_MODE(tile_mode
) << 3) |
45 (G_009910_MICRO_TILE_MODE_NEW(tile_mode
) << 8) |
46 /* Non-depth modes don't have TILE_SPLIT set. */
47 ((util_logbase2(tex
->surface
.u
.legacy
.tile_split
>> 6)) << 11) |
48 (G_009990_BANK_WIDTH(macro_tile_mode
) << 15) |
49 (G_009990_BANK_HEIGHT(macro_tile_mode
) << 18) |
50 (G_009990_NUM_BANKS(macro_tile_mode
) << 21) |
51 (G_009990_MACRO_TILE_ASPECT(macro_tile_mode
) << 24) |
52 (G_009910_PIPE_CONFIG(tile_mode
) << 26);
55 static bool si_sdma_v4_copy_texture(struct si_context
*sctx
, struct pipe_resource
*dst
,
56 unsigned dst_level
, unsigned dstx
, unsigned dsty
, unsigned dstz
,
57 struct pipe_resource
*src
, unsigned src_level
,
58 const struct pipe_box
*src_box
)
60 struct si_texture
*ssrc
= (struct si_texture
*)src
;
61 struct si_texture
*sdst
= (struct si_texture
*)dst
;
63 unsigned bpp
= sdst
->surface
.bpe
;
64 uint64_t dst_address
= sdst
->buffer
.gpu_address
+ sdst
->surface
.u
.gfx9
.surf_offset
;
65 uint64_t src_address
= ssrc
->buffer
.gpu_address
+ ssrc
->surface
.u
.gfx9
.surf_offset
;
66 unsigned dst_pitch
= sdst
->surface
.u
.gfx9
.surf_pitch
;
67 unsigned src_pitch
= ssrc
->surface
.u
.gfx9
.surf_pitch
;
68 uint64_t dst_slice_pitch
= ((uint64_t)sdst
->surface
.u
.gfx9
.surf_slice_size
) / bpp
;
69 uint64_t src_slice_pitch
= ((uint64_t)ssrc
->surface
.u
.gfx9
.surf_slice_size
) / bpp
;
70 unsigned srcx
= src_box
->x
/ ssrc
->surface
.blk_w
;
71 unsigned srcy
= src_box
->y
/ ssrc
->surface
.blk_h
;
72 unsigned srcz
= src_box
->z
;
73 unsigned copy_width
= DIV_ROUND_UP(src_box
->width
, ssrc
->surface
.blk_w
);
74 unsigned copy_height
= DIV_ROUND_UP(src_box
->height
, ssrc
->surface
.blk_h
);
75 unsigned copy_depth
= src_box
->depth
;
76 unsigned xalign
= MAX2(1, 4 / bpp
);
78 assert(src_level
<= src
->last_level
);
79 assert(dst_level
<= dst
->last_level
);
80 assert(sdst
->surface
.u
.gfx9
.surf_offset
+ dst_slice_pitch
* bpp
* (dstz
+ src_box
->depth
) <=
81 sdst
->buffer
.buf
->size
);
82 assert(ssrc
->surface
.u
.gfx9
.surf_offset
+ src_slice_pitch
* bpp
* (srcz
+ src_box
->depth
) <=
83 ssrc
->buffer
.buf
->size
);
85 if (!si_prepare_for_dma_blit(sctx
, sdst
, dst_level
, dstx
, dsty
, dstz
, ssrc
, src_level
, src_box
))
88 dstx
/= sdst
->surface
.blk_w
;
89 dsty
/= sdst
->surface
.blk_h
;
91 if (srcx
>= (1 << 14) || srcy
>= (1 << 14) || srcz
>= (1 << 11) || dstx
>= (1 << 14) ||
92 dsty
>= (1 << 14) || dstz
>= (1 << 11))
95 /* Linear -> linear sub-window copy. */
96 if (ssrc
->surface
.is_linear
&& sdst
->surface
.is_linear
) {
97 struct radeon_cmdbuf
*cs
= sctx
->sdma_cs
;
99 /* Check if everything fits into the bitfields */
100 if (!(src_pitch
<= (1 << 19) && dst_pitch
<= (1 << 19) && src_slice_pitch
<= (1 << 28) &&
101 dst_slice_pitch
<= (1 << 28) && copy_width
<= (1 << 14) && copy_height
<= (1 << 14) &&
102 copy_depth
<= (1 << 11)))
105 si_need_dma_space(sctx
, 13, &sdst
->buffer
, &ssrc
->buffer
);
107 src_address
+= ssrc
->surface
.u
.gfx9
.offset
[src_level
];
108 dst_address
+= sdst
->surface
.u
.gfx9
.offset
[dst_level
];
110 /* Check alignments */
111 if ((src_address
% 4) != 0 || (dst_address
% 4) != 0 || (src_pitch
% xalign
) != 0)
115 cs
, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY
, CIK_SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW
,
116 sctx
->ws
->cs_is_secure(cs
) ? (1u << 2) : 0) |
117 (util_logbase2(bpp
) << 29));
118 radeon_emit(cs
, src_address
);
119 radeon_emit(cs
, src_address
>> 32);
120 radeon_emit(cs
, srcx
| (srcy
<< 16));
121 radeon_emit(cs
, srcz
| ((src_pitch
- 1) << 13));
122 radeon_emit(cs
, src_slice_pitch
- 1);
123 radeon_emit(cs
, dst_address
);
124 radeon_emit(cs
, dst_address
>> 32);
125 radeon_emit(cs
, dstx
| (dsty
<< 16));
126 radeon_emit(cs
, dstz
| ((dst_pitch
- 1) << 13));
127 radeon_emit(cs
, dst_slice_pitch
- 1);
128 radeon_emit(cs
, (copy_width
- 1) | ((copy_height
- 1) << 16));
129 radeon_emit(cs
, (copy_depth
- 1));
133 /* Linear <-> Tiled sub-window copy */
134 if (ssrc
->surface
.is_linear
!= sdst
->surface
.is_linear
) {
135 struct si_texture
*tiled
= ssrc
->surface
.is_linear
? sdst
: ssrc
;
136 struct si_texture
*linear
= tiled
== ssrc
? sdst
: ssrc
;
137 unsigned tiled_level
= tiled
== ssrc
? src_level
: dst_level
;
138 unsigned linear_level
= linear
== ssrc
? src_level
: dst_level
;
139 unsigned tiled_x
= tiled
== ssrc
? srcx
: dstx
;
140 unsigned linear_x
= linear
== ssrc
? srcx
: dstx
;
141 unsigned tiled_y
= tiled
== ssrc
? srcy
: dsty
;
142 unsigned linear_y
= linear
== ssrc
? srcy
: dsty
;
143 unsigned tiled_z
= tiled
== ssrc
? srcz
: dstz
;
144 unsigned linear_z
= linear
== ssrc
? srcz
: dstz
;
145 unsigned tiled_width
= tiled
== ssrc
146 ? DIV_ROUND_UP(ssrc
->buffer
.b
.b
.width0
, ssrc
->surface
.blk_w
)
147 : DIV_ROUND_UP(sdst
->buffer
.b
.b
.width0
, sdst
->surface
.blk_w
);
148 unsigned tiled_height
= tiled
== ssrc
149 ? DIV_ROUND_UP(ssrc
->buffer
.b
.b
.height0
, ssrc
->surface
.blk_h
)
150 : DIV_ROUND_UP(sdst
->buffer
.b
.b
.height0
, sdst
->surface
.blk_h
);
151 unsigned tiled_depth
= tiled
== ssrc
? ssrc
->buffer
.b
.b
.depth0
: sdst
->buffer
.b
.b
.depth0
;
152 unsigned linear_pitch
= linear
== ssrc
? src_pitch
: dst_pitch
;
153 unsigned linear_slice_pitch
= linear
== ssrc
? src_slice_pitch
: dst_slice_pitch
;
154 uint64_t tiled_address
= tiled
== ssrc
? src_address
: dst_address
;
155 uint64_t linear_address
= linear
== ssrc
? src_address
: dst_address
;
156 struct radeon_cmdbuf
*cs
= sctx
->sdma_cs
;
158 linear_address
+= linear
->surface
.u
.gfx9
.offset
[linear_level
];
160 /* Check if everything fits into the bitfields */
161 if (!(tiled_x
<= (1 << 14) && tiled_y
<= (1 << 14) && tiled_z
<= (1 << 11) &&
162 tiled_width
<= (1 << 14) && tiled_height
<= (1 << 14) && tiled_depth
<= (1 << 11) &&
163 linear_x
<= (1 << 14) && linear_y
<= (1 << 14) && linear_z
<= (1 << 11) &&
164 linear_pitch
<= (1 << 14) && linear_slice_pitch
<= (1 << 28) &&
165 copy_width
<= (1 << 14) && copy_height
<= (1 << 14) && copy_depth
<= (1 << 11)))
168 /* Check alignments */
169 if ((tiled_address
% 256 != 0) || (linear_address
% 4 != 0) || (linear_pitch
% xalign
!= 0) ||
170 (linear_slice_pitch
% xalign
!= 0))
173 si_need_dma_space(sctx
, 14, &sdst
->buffer
, &ssrc
->buffer
);
176 cs
, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY
, CIK_SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW
,
177 sctx
->ws
->cs_is_secure(cs
) ? (1u << 2) : 0) |
178 tiled
->buffer
.b
.b
.last_level
<< 20 | tiled_level
<< 24 |
179 (linear
== sdst
? 1u : 0) << 31);
180 radeon_emit(cs
, (uint32_t)tiled_address
);
181 radeon_emit(cs
, (uint32_t)(tiled_address
>> 32));
182 radeon_emit(cs
, tiled_x
| (tiled_y
<< 16));
183 radeon_emit(cs
, tiled_z
| ((tiled_width
- 1) << 16));
184 radeon_emit(cs
, (tiled_height
- 1) | (tiled_depth
- 1) << 16);
185 radeon_emit(cs
, util_logbase2(bpp
) | tiled
->surface
.u
.gfx9
.surf
.swizzle_mode
<< 3 |
186 tiled
->surface
.u
.gfx9
.resource_type
<< 9 |
187 tiled
->surface
.u
.gfx9
.surf
.epitch
<< 16);
188 radeon_emit(cs
, (uint32_t)linear_address
);
189 radeon_emit(cs
, (uint32_t)(linear_address
>> 32));
190 radeon_emit(cs
, linear_x
| (linear_y
<< 16));
191 radeon_emit(cs
, linear_z
| ((linear_pitch
- 1) << 16));
192 radeon_emit(cs
, linear_slice_pitch
- 1);
193 radeon_emit(cs
, (copy_width
- 1) | ((copy_height
- 1) << 16));
194 radeon_emit(cs
, (copy_depth
- 1));
201 static bool cik_sdma_copy_texture(struct si_context
*sctx
, struct pipe_resource
*dst
,
202 unsigned dst_level
, unsigned dstx
, unsigned dsty
, unsigned dstz
,
203 struct pipe_resource
*src
, unsigned src_level
,
204 const struct pipe_box
*src_box
)
206 struct radeon_info
*info
= &sctx
->screen
->info
;
207 struct si_texture
*ssrc
= (struct si_texture
*)src
;
208 struct si_texture
*sdst
= (struct si_texture
*)dst
;
209 unsigned bpp
= sdst
->surface
.bpe
;
210 uint64_t dst_address
= sdst
->buffer
.gpu_address
+ sdst
->surface
.u
.legacy
.level
[dst_level
].offset
;
211 uint64_t src_address
= ssrc
->buffer
.gpu_address
+ ssrc
->surface
.u
.legacy
.level
[src_level
].offset
;
212 unsigned dst_mode
= sdst
->surface
.u
.legacy
.level
[dst_level
].mode
;
213 unsigned src_mode
= ssrc
->surface
.u
.legacy
.level
[src_level
].mode
;
214 unsigned dst_tile_index
= sdst
->surface
.u
.legacy
.tiling_index
[dst_level
];
215 unsigned src_tile_index
= ssrc
->surface
.u
.legacy
.tiling_index
[src_level
];
216 unsigned dst_tile_mode
= info
->si_tile_mode_array
[dst_tile_index
];
217 unsigned src_tile_mode
= info
->si_tile_mode_array
[src_tile_index
];
218 unsigned dst_micro_mode
= G_009910_MICRO_TILE_MODE_NEW(dst_tile_mode
);
219 unsigned src_micro_mode
= G_009910_MICRO_TILE_MODE_NEW(src_tile_mode
);
220 unsigned dst_tile_swizzle
= dst_mode
== RADEON_SURF_MODE_2D
? sdst
->surface
.tile_swizzle
: 0;
221 unsigned src_tile_swizzle
= src_mode
== RADEON_SURF_MODE_2D
? ssrc
->surface
.tile_swizzle
: 0;
222 unsigned dst_pitch
= sdst
->surface
.u
.legacy
.level
[dst_level
].nblk_x
;
223 unsigned src_pitch
= ssrc
->surface
.u
.legacy
.level
[src_level
].nblk_x
;
224 uint64_t dst_slice_pitch
=
225 ((uint64_t)sdst
->surface
.u
.legacy
.level
[dst_level
].slice_size_dw
* 4) / bpp
;
226 uint64_t src_slice_pitch
=
227 ((uint64_t)ssrc
->surface
.u
.legacy
.level
[src_level
].slice_size_dw
* 4) / bpp
;
228 unsigned dst_width
= minify_as_blocks(sdst
->buffer
.b
.b
.width0
, dst_level
, sdst
->surface
.blk_w
);
229 unsigned src_width
= minify_as_blocks(ssrc
->buffer
.b
.b
.width0
, src_level
, ssrc
->surface
.blk_w
);
230 unsigned dst_height
= minify_as_blocks(sdst
->buffer
.b
.b
.height0
, dst_level
, sdst
->surface
.blk_h
);
231 unsigned src_height
= minify_as_blocks(ssrc
->buffer
.b
.b
.height0
, src_level
, ssrc
->surface
.blk_h
);
232 unsigned srcx
= src_box
->x
/ ssrc
->surface
.blk_w
;
233 unsigned srcy
= src_box
->y
/ ssrc
->surface
.blk_h
;
234 unsigned srcz
= src_box
->z
;
235 unsigned copy_width
= DIV_ROUND_UP(src_box
->width
, ssrc
->surface
.blk_w
);
236 unsigned copy_height
= DIV_ROUND_UP(src_box
->height
, ssrc
->surface
.blk_h
);
237 unsigned copy_depth
= src_box
->depth
;
239 assert(src_level
<= src
->last_level
);
240 assert(dst_level
<= dst
->last_level
);
241 assert(sdst
->surface
.u
.legacy
.level
[dst_level
].offset
+
242 dst_slice_pitch
* bpp
* (dstz
+ src_box
->depth
) <=
243 sdst
->buffer
.buf
->size
);
244 assert(ssrc
->surface
.u
.legacy
.level
[src_level
].offset
+
245 src_slice_pitch
* bpp
* (srcz
+ src_box
->depth
) <=
246 ssrc
->buffer
.buf
->size
);
248 if (!si_prepare_for_dma_blit(sctx
, sdst
, dst_level
, dstx
, dsty
, dstz
, ssrc
, src_level
, src_box
))
251 dstx
/= sdst
->surface
.blk_w
;
252 dsty
/= sdst
->surface
.blk_h
;
254 if (srcx
>= (1 << 14) || srcy
>= (1 << 14) || srcz
>= (1 << 11) || dstx
>= (1 << 14) ||
255 dsty
>= (1 << 14) || dstz
>= (1 << 11))
258 dst_address
|= dst_tile_swizzle
<< 8;
259 src_address
|= src_tile_swizzle
<< 8;
261 /* Linear -> linear sub-window copy. */
262 if (dst_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
&& src_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
&&
263 /* check if everything fits into the bitfields */
264 src_pitch
<= (1 << 14) && dst_pitch
<= (1 << 14) && src_slice_pitch
<= (1 << 28) &&
265 dst_slice_pitch
<= (1 << 28) && copy_width
<= (1 << 14) && copy_height
<= (1 << 14) &&
266 copy_depth
<= (1 << 11) &&
267 /* HW limitation - GFX7: */
268 (sctx
->chip_class
!= GFX7
||
269 (copy_width
< (1 << 14) && copy_height
< (1 << 14) && copy_depth
< (1 << 11))) &&
270 /* HW limitation - some GFX7 parts: */
271 ((sctx
->family
!= CHIP_BONAIRE
&& sctx
->family
!= CHIP_KAVERI
) ||
272 (srcx
+ copy_width
!= (1 << 14) && srcy
+ copy_height
!= (1 << 14)))) {
273 struct radeon_cmdbuf
*cs
= sctx
->sdma_cs
;
275 si_need_dma_space(sctx
, 13, &sdst
->buffer
, &ssrc
->buffer
);
278 cs
, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY
, CIK_SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW
, 0) |
279 (util_logbase2(bpp
) << 29));
280 radeon_emit(cs
, src_address
);
281 radeon_emit(cs
, src_address
>> 32);
282 radeon_emit(cs
, srcx
| (srcy
<< 16));
283 radeon_emit(cs
, srcz
| ((src_pitch
- 1) << 16));
284 radeon_emit(cs
, src_slice_pitch
- 1);
285 radeon_emit(cs
, dst_address
);
286 radeon_emit(cs
, dst_address
>> 32);
287 radeon_emit(cs
, dstx
| (dsty
<< 16));
288 radeon_emit(cs
, dstz
| ((dst_pitch
- 1) << 16));
289 radeon_emit(cs
, dst_slice_pitch
- 1);
290 if (sctx
->chip_class
== GFX7
) {
291 radeon_emit(cs
, copy_width
| (copy_height
<< 16));
292 radeon_emit(cs
, copy_depth
);
294 radeon_emit(cs
, (copy_width
- 1) | ((copy_height
- 1) << 16));
295 radeon_emit(cs
, (copy_depth
- 1));
300 /* Tiled <-> linear sub-window copy. */
301 if ((src_mode
>= RADEON_SURF_MODE_1D
) != (dst_mode
>= RADEON_SURF_MODE_1D
)) {
302 struct si_texture
*tiled
= src_mode
>= RADEON_SURF_MODE_1D
? ssrc
: sdst
;
303 struct si_texture
*linear
= tiled
== ssrc
? sdst
: ssrc
;
304 unsigned tiled_level
= tiled
== ssrc
? src_level
: dst_level
;
305 unsigned linear_level
= linear
== ssrc
? src_level
: dst_level
;
306 unsigned tiled_x
= tiled
== ssrc
? srcx
: dstx
;
307 unsigned linear_x
= linear
== ssrc
? srcx
: dstx
;
308 unsigned tiled_y
= tiled
== ssrc
? srcy
: dsty
;
309 unsigned linear_y
= linear
== ssrc
? srcy
: dsty
;
310 unsigned tiled_z
= tiled
== ssrc
? srcz
: dstz
;
311 unsigned linear_z
= linear
== ssrc
? srcz
: dstz
;
312 unsigned tiled_width
= tiled
== ssrc
? src_width
: dst_width
;
313 unsigned linear_width
= linear
== ssrc
? src_width
: dst_width
;
314 unsigned tiled_pitch
= tiled
== ssrc
? src_pitch
: dst_pitch
;
315 unsigned linear_pitch
= linear
== ssrc
? src_pitch
: dst_pitch
;
316 unsigned tiled_slice_pitch
= tiled
== ssrc
? src_slice_pitch
: dst_slice_pitch
;
317 unsigned linear_slice_pitch
= linear
== ssrc
? src_slice_pitch
: dst_slice_pitch
;
318 uint64_t tiled_address
= tiled
== ssrc
? src_address
: dst_address
;
319 uint64_t linear_address
= linear
== ssrc
? src_address
: dst_address
;
320 unsigned tiled_micro_mode
= tiled
== ssrc
? src_micro_mode
: dst_micro_mode
;
322 assert(tiled_pitch
% 8 == 0);
323 assert(tiled_slice_pitch
% 64 == 0);
324 unsigned pitch_tile_max
= tiled_pitch
/ 8 - 1;
325 unsigned slice_tile_max
= tiled_slice_pitch
/ 64 - 1;
326 unsigned xalign
= MAX2(1, 4 / bpp
);
327 unsigned copy_width_aligned
= copy_width
;
329 /* If the region ends at the last pixel and is unaligned, we
330 * can copy the remainder of the line that is not visible to
333 if (copy_width
% xalign
!= 0 && linear_x
+ copy_width
== linear_width
&&
334 tiled_x
+ copy_width
== tiled_width
&&
335 linear_x
+ align(copy_width
, xalign
) <= linear_pitch
&&
336 tiled_x
+ align(copy_width
, xalign
) <= tiled_pitch
)
337 copy_width_aligned
= align(copy_width
, xalign
);
339 /* HW limitations. */
340 if ((sctx
->family
== CHIP_BONAIRE
|| sctx
->family
== CHIP_KAVERI
) &&
341 linear_pitch
- 1 == 0x3fff && bpp
== 16)
344 if (sctx
->chip_class
== GFX7
&&
345 (copy_width_aligned
== (1 << 14) || copy_height
== (1 << 14) || copy_depth
== (1 << 11)))
348 if ((sctx
->family
== CHIP_BONAIRE
|| sctx
->family
== CHIP_KAVERI
||
349 sctx
->family
== CHIP_KABINI
) &&
350 (tiled_x
+ copy_width
== (1 << 14) || tiled_y
+ copy_height
== (1 << 14)))
353 /* The hw can read outside of the given linear buffer bounds,
354 * or access those pages but not touch the memory in case
355 * of writes. (it still causes a VM fault)
357 * Out-of-bounds memory access or page directory access must
360 int64_t start_linear_address
, end_linear_address
;
361 unsigned granularity
;
363 /* Deduce the size of reads from the linear surface. */
364 switch (tiled_micro_mode
) {
365 case V_009910_ADDR_SURF_DISPLAY_MICRO_TILING
:
366 granularity
= bpp
== 1 ? 64 / (8 * bpp
) : 128 / (8 * bpp
);
368 case V_009910_ADDR_SURF_THIN_MICRO_TILING
:
369 case V_009910_ADDR_SURF_DEPTH_MICRO_TILING
:
370 if (0 /* TODO: THICK microtiling */)
372 bpp
== 1 ? 32 / (8 * bpp
)
373 : bpp
== 2 ? 64 / (8 * bpp
) : bpp
<= 8 ? 128 / (8 * bpp
) : 256 / (8 * bpp
);
375 granularity
= bpp
<= 2 ? 64 / (8 * bpp
) : bpp
<= 8 ? 128 / (8 * bpp
) : 256 / (8 * bpp
);
381 /* The linear reads start at tiled_x & ~(granularity - 1).
382 * If linear_x == 0 && tiled_x % granularity != 0, the hw
383 * starts reading from an address preceding linear_address!!!
385 start_linear_address
=
386 linear
->surface
.u
.legacy
.level
[linear_level
].offset
+
387 bpp
* (linear_z
* linear_slice_pitch
+ linear_y
* linear_pitch
+ linear_x
);
388 start_linear_address
-= (int)(bpp
* (tiled_x
% granularity
));
391 linear
->surface
.u
.legacy
.level
[linear_level
].offset
+
392 bpp
* ((linear_z
+ copy_depth
- 1) * linear_slice_pitch
+
393 (linear_y
+ copy_height
- 1) * linear_pitch
+ (linear_x
+ copy_width
));
395 if ((tiled_x
+ copy_width
) % granularity
)
396 end_linear_address
+= granularity
- (tiled_x
+ copy_width
) % granularity
;
398 if (start_linear_address
< 0 || end_linear_address
> linear
->surface
.surf_size
)
401 /* Check requirements. */
402 if (tiled_address
% 256 == 0 && linear_address
% 4 == 0 && linear_pitch
% xalign
== 0 &&
403 linear_x
% xalign
== 0 && tiled_x
% xalign
== 0 && copy_width_aligned
% xalign
== 0 &&
404 tiled_micro_mode
!= V_009910_ADDR_SURF_ROTATED_MICRO_TILING
&&
405 /* check if everything fits into the bitfields */
406 tiled
->surface
.u
.legacy
.tile_split
<= 4096 && pitch_tile_max
< (1 << 11) &&
407 slice_tile_max
< (1 << 22) && linear_pitch
<= (1 << 14) &&
408 linear_slice_pitch
<= (1 << 28) && copy_width_aligned
<= (1 << 14) &&
409 copy_height
<= (1 << 14) && copy_depth
<= (1 << 11)) {
410 struct radeon_cmdbuf
*cs
= sctx
->sdma_cs
;
411 uint32_t direction
= linear
== sdst
? 1u << 31 : 0;
413 si_need_dma_space(sctx
, 14, &sdst
->buffer
, &ssrc
->buffer
);
415 radeon_emit(cs
, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY
,
416 CIK_SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW
, 0) |
418 radeon_emit(cs
, tiled_address
);
419 radeon_emit(cs
, tiled_address
>> 32);
420 radeon_emit(cs
, tiled_x
| (tiled_y
<< 16));
421 radeon_emit(cs
, tiled_z
| (pitch_tile_max
<< 16));
422 radeon_emit(cs
, slice_tile_max
);
423 radeon_emit(cs
, encode_tile_info(sctx
, tiled
, tiled_level
, true));
424 radeon_emit(cs
, linear_address
);
425 radeon_emit(cs
, linear_address
>> 32);
426 radeon_emit(cs
, linear_x
| (linear_y
<< 16));
427 radeon_emit(cs
, linear_z
| ((linear_pitch
- 1) << 16));
428 radeon_emit(cs
, linear_slice_pitch
- 1);
429 if (sctx
->chip_class
== GFX7
) {
430 radeon_emit(cs
, copy_width_aligned
| (copy_height
<< 16));
431 radeon_emit(cs
, copy_depth
);
433 radeon_emit(cs
, (copy_width_aligned
- 1) | ((copy_height
- 1) << 16));
434 radeon_emit(cs
, (copy_depth
- 1));
440 /* Tiled -> Tiled sub-window copy. */
441 if (dst_mode
>= RADEON_SURF_MODE_1D
&& src_mode
>= RADEON_SURF_MODE_1D
&&
442 /* check if these fit into the bitfields */
443 src_address
% 256 == 0 && dst_address
% 256 == 0 &&
444 ssrc
->surface
.u
.legacy
.tile_split
<= 4096 && sdst
->surface
.u
.legacy
.tile_split
<= 4096 &&
445 dstx
% 8 == 0 && dsty
% 8 == 0 && srcx
% 8 == 0 && srcy
% 8 == 0 &&
446 /* this can either be equal, or display->rotated (GFX8+ only) */
447 (src_micro_mode
== dst_micro_mode
||
448 (sctx
->chip_class
>= GFX8
&& src_micro_mode
== V_009910_ADDR_SURF_DISPLAY_MICRO_TILING
&&
449 dst_micro_mode
== V_009910_ADDR_SURF_ROTATED_MICRO_TILING
))) {
450 assert(src_pitch
% 8 == 0);
451 assert(dst_pitch
% 8 == 0);
452 assert(src_slice_pitch
% 64 == 0);
453 assert(dst_slice_pitch
% 64 == 0);
454 unsigned src_pitch_tile_max
= src_pitch
/ 8 - 1;
455 unsigned dst_pitch_tile_max
= dst_pitch
/ 8 - 1;
456 unsigned src_slice_tile_max
= src_slice_pitch
/ 64 - 1;
457 unsigned dst_slice_tile_max
= dst_slice_pitch
/ 64 - 1;
458 unsigned copy_width_aligned
= copy_width
;
459 unsigned copy_height_aligned
= copy_height
;
461 /* If the region ends at the last pixel and is unaligned, we
462 * can copy the remainder of the tile that is not visible to
465 if (copy_width
% 8 != 0 && srcx
+ copy_width
== src_width
&& dstx
+ copy_width
== dst_width
)
466 copy_width_aligned
= align(copy_width
, 8);
468 if (copy_height
% 8 != 0 && srcy
+ copy_height
== src_height
&&
469 dsty
+ copy_height
== dst_height
)
470 copy_height_aligned
= align(copy_height
, 8);
472 /* check if these fit into the bitfields */
473 if (src_pitch_tile_max
< (1 << 11) && dst_pitch_tile_max
< (1 << 11) &&
474 src_slice_tile_max
< (1 << 22) && dst_slice_tile_max
< (1 << 22) &&
475 copy_width_aligned
<= (1 << 14) && copy_height_aligned
<= (1 << 14) &&
476 copy_depth
<= (1 << 11) && copy_width_aligned
% 8 == 0 && copy_height_aligned
% 8 == 0 &&
477 /* HW limitation - GFX7: */
478 (sctx
->chip_class
!= GFX7
||
479 (copy_width_aligned
< (1 << 14) && copy_height_aligned
< (1 << 14) &&
480 copy_depth
< (1 << 11))) &&
481 /* HW limitation - some GFX7 parts: */
482 ((sctx
->family
!= CHIP_BONAIRE
&& sctx
->family
!= CHIP_KAVERI
&&
483 sctx
->family
!= CHIP_KABINI
) ||
484 (srcx
+ copy_width_aligned
!= (1 << 14) && srcy
+ copy_height_aligned
!= (1 << 14) &&
485 dstx
+ copy_width
!= (1 << 14)))) {
486 struct radeon_cmdbuf
*cs
= sctx
->sdma_cs
;
488 si_need_dma_space(sctx
, 15, &sdst
->buffer
, &ssrc
->buffer
);
491 cs
, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY
, CIK_SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW
, 0));
492 radeon_emit(cs
, src_address
);
493 radeon_emit(cs
, src_address
>> 32);
494 radeon_emit(cs
, srcx
| (srcy
<< 16));
495 radeon_emit(cs
, srcz
| (src_pitch_tile_max
<< 16));
496 radeon_emit(cs
, src_slice_tile_max
);
497 radeon_emit(cs
, encode_tile_info(sctx
, ssrc
, src_level
, true));
498 radeon_emit(cs
, dst_address
);
499 radeon_emit(cs
, dst_address
>> 32);
500 radeon_emit(cs
, dstx
| (dsty
<< 16));
501 radeon_emit(cs
, dstz
| (dst_pitch_tile_max
<< 16));
502 radeon_emit(cs
, dst_slice_tile_max
);
503 radeon_emit(cs
, encode_tile_info(sctx
, sdst
, dst_level
, false));
504 if (sctx
->chip_class
== GFX7
) {
505 radeon_emit(cs
, copy_width_aligned
| (copy_height_aligned
<< 16));
506 radeon_emit(cs
, copy_depth
);
508 radeon_emit(cs
, (copy_width_aligned
- 8) | ((copy_height_aligned
- 8) << 16));
509 radeon_emit(cs
, (copy_depth
- 1));
518 static void cik_sdma_copy(struct pipe_context
*ctx
, struct pipe_resource
*dst
, unsigned dst_level
,
519 unsigned dstx
, unsigned dsty
, unsigned dstz
, struct pipe_resource
*src
,
520 unsigned src_level
, const struct pipe_box
*src_box
)
522 struct si_context
*sctx
= (struct si_context
*)ctx
;
524 assert(src
->target
!= PIPE_BUFFER
);
526 if (!sctx
->sdma_cs
|| src
->flags
& PIPE_RESOURCE_FLAG_SPARSE
||
527 dst
->flags
& PIPE_RESOURCE_FLAG_SPARSE
)
530 /* SDMA causes corruption. See:
531 * https://bugs.freedesktop.org/show_bug.cgi?id=110575
532 * https://bugs.freedesktop.org/show_bug.cgi?id=110635
534 * Keep SDMA enabled on APUs.
536 if (sctx
->screen
->debug_flags
& DBG(FORCE_SDMA
) ||
537 (!sctx
->screen
->info
.has_dedicated_vram
&&
538 !(sctx
->screen
->debug_flags
& DBG(NO_SDMA_COPY_IMAGE
)))) {
539 if ((sctx
->chip_class
== GFX7
|| sctx
->chip_class
== GFX8
) &&
540 cik_sdma_copy_texture(sctx
, dst
, dst_level
, dstx
, dsty
, dstz
, src
, src_level
, src_box
))
542 else if (sctx
->chip_class
== GFX9
&& si_sdma_v4_copy_texture(sctx
, dst
, dst_level
, dstx
, dsty
,
543 dstz
, src
, src_level
, src_box
))
548 si_resource_copy_region(ctx
, dst
, dst_level
, dstx
, dsty
, dstz
, src
, src_level
, src_box
);
551 void cik_init_sdma_functions(struct si_context
*sctx
)
553 sctx
->dma_copy
= cik_sdma_copy
;