2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2015 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 static void cik_sdma_copy_buffer(struct si_context
*ctx
,
30 struct pipe_resource
*dst
,
31 struct pipe_resource
*src
,
36 struct radeon_cmdbuf
*cs
= ctx
->dma_cs
;
37 unsigned i
, ncopy
, csize
;
38 struct si_resource
*sdst
= si_resource(dst
);
39 struct si_resource
*ssrc
= si_resource(src
);
41 /* Mark the buffer range of destination as valid (initialized),
42 * so that transfer_map knows it should wait for the GPU when mapping
44 util_range_add(&sdst
->valid_buffer_range
, dst_offset
,
47 dst_offset
+= sdst
->gpu_address
;
48 src_offset
+= ssrc
->gpu_address
;
50 ncopy
= DIV_ROUND_UP(size
, CIK_SDMA_COPY_MAX_SIZE
);
51 si_need_dma_space(ctx
, ncopy
* 7, sdst
, ssrc
);
53 for (i
= 0; i
< ncopy
; i
++) {
54 csize
= MIN2(size
, CIK_SDMA_COPY_MAX_SIZE
);
55 radeon_emit(cs
, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY
,
56 CIK_SDMA_COPY_SUB_OPCODE_LINEAR
,
58 radeon_emit(cs
, ctx
->chip_class
>= GFX9
? csize
- 1 : csize
);
59 radeon_emit(cs
, 0); /* src/dst endian swap */
60 radeon_emit(cs
, src_offset
);
61 radeon_emit(cs
, src_offset
>> 32);
62 radeon_emit(cs
, dst_offset
);
63 radeon_emit(cs
, dst_offset
>> 32);
70 static unsigned minify_as_blocks(unsigned width
, unsigned level
, unsigned blk_w
)
72 width
= u_minify(width
, level
);
73 return DIV_ROUND_UP(width
, blk_w
);
76 static unsigned encode_tile_info(struct si_context
*sctx
,
77 struct si_texture
*tex
, unsigned level
,
80 struct radeon_info
*info
= &sctx
->screen
->info
;
81 unsigned tile_index
= tex
->surface
.u
.legacy
.tiling_index
[level
];
82 unsigned macro_tile_index
= tex
->surface
.u
.legacy
.macro_tile_index
;
83 unsigned tile_mode
= info
->si_tile_mode_array
[tile_index
];
84 unsigned macro_tile_mode
= info
->cik_macrotile_mode_array
[macro_tile_index
];
86 return (set_bpp
? util_logbase2(tex
->surface
.bpe
) : 0) |
87 (G_009910_ARRAY_MODE(tile_mode
) << 3) |
88 (G_009910_MICRO_TILE_MODE_NEW(tile_mode
) << 8) |
89 /* Non-depth modes don't have TILE_SPLIT set. */
90 ((util_logbase2(tex
->surface
.u
.legacy
.tile_split
>> 6)) << 11) |
91 (G_009990_BANK_WIDTH(macro_tile_mode
) << 15) |
92 (G_009990_BANK_HEIGHT(macro_tile_mode
) << 18) |
93 (G_009990_NUM_BANKS(macro_tile_mode
) << 21) |
94 (G_009990_MACRO_TILE_ASPECT(macro_tile_mode
) << 24) |
95 (G_009910_PIPE_CONFIG(tile_mode
) << 26);
98 static bool cik_sdma_copy_texture(struct si_context
*sctx
,
99 struct pipe_resource
*dst
,
101 unsigned dstx
, unsigned dsty
, unsigned dstz
,
102 struct pipe_resource
*src
,
104 const struct pipe_box
*src_box
)
106 struct radeon_info
*info
= &sctx
->screen
->info
;
107 struct si_texture
*ssrc
= (struct si_texture
*)src
;
108 struct si_texture
*sdst
= (struct si_texture
*)dst
;
109 unsigned bpp
= sdst
->surface
.bpe
;
110 uint64_t dst_address
= sdst
->buffer
.gpu_address
+
111 sdst
->surface
.u
.legacy
.level
[dst_level
].offset
;
112 uint64_t src_address
= ssrc
->buffer
.gpu_address
+
113 ssrc
->surface
.u
.legacy
.level
[src_level
].offset
;
114 unsigned dst_mode
= sdst
->surface
.u
.legacy
.level
[dst_level
].mode
;
115 unsigned src_mode
= ssrc
->surface
.u
.legacy
.level
[src_level
].mode
;
116 unsigned dst_tile_index
= sdst
->surface
.u
.legacy
.tiling_index
[dst_level
];
117 unsigned src_tile_index
= ssrc
->surface
.u
.legacy
.tiling_index
[src_level
];
118 unsigned dst_tile_mode
= info
->si_tile_mode_array
[dst_tile_index
];
119 unsigned src_tile_mode
= info
->si_tile_mode_array
[src_tile_index
];
120 unsigned dst_micro_mode
= G_009910_MICRO_TILE_MODE_NEW(dst_tile_mode
);
121 unsigned src_micro_mode
= G_009910_MICRO_TILE_MODE_NEW(src_tile_mode
);
122 unsigned dst_tile_swizzle
= dst_mode
== RADEON_SURF_MODE_2D
?
123 sdst
->surface
.tile_swizzle
: 0;
124 unsigned src_tile_swizzle
= src_mode
== RADEON_SURF_MODE_2D
?
125 ssrc
->surface
.tile_swizzle
: 0;
126 unsigned dst_pitch
= sdst
->surface
.u
.legacy
.level
[dst_level
].nblk_x
;
127 unsigned src_pitch
= ssrc
->surface
.u
.legacy
.level
[src_level
].nblk_x
;
128 uint64_t dst_slice_pitch
= ((uint64_t)sdst
->surface
.u
.legacy
.level
[dst_level
].slice_size_dw
* 4) / bpp
;
129 uint64_t src_slice_pitch
= ((uint64_t)ssrc
->surface
.u
.legacy
.level
[src_level
].slice_size_dw
* 4) / bpp
;
130 unsigned dst_width
= minify_as_blocks(sdst
->buffer
.b
.b
.width0
,
131 dst_level
, sdst
->surface
.blk_w
);
132 unsigned src_width
= minify_as_blocks(ssrc
->buffer
.b
.b
.width0
,
133 src_level
, ssrc
->surface
.blk_w
);
134 unsigned dst_height
= minify_as_blocks(sdst
->buffer
.b
.b
.height0
,
135 dst_level
, sdst
->surface
.blk_h
);
136 unsigned src_height
= minify_as_blocks(ssrc
->buffer
.b
.b
.height0
,
137 src_level
, ssrc
->surface
.blk_h
);
138 unsigned srcx
= src_box
->x
/ ssrc
->surface
.blk_w
;
139 unsigned srcy
= src_box
->y
/ ssrc
->surface
.blk_h
;
140 unsigned srcz
= src_box
->z
;
141 unsigned copy_width
= DIV_ROUND_UP(src_box
->width
, ssrc
->surface
.blk_w
);
142 unsigned copy_height
= DIV_ROUND_UP(src_box
->height
, ssrc
->surface
.blk_h
);
143 unsigned copy_depth
= src_box
->depth
;
145 assert(src_level
<= src
->last_level
);
146 assert(dst_level
<= dst
->last_level
);
147 assert(sdst
->surface
.u
.legacy
.level
[dst_level
].offset
+
148 dst_slice_pitch
* bpp
* (dstz
+ src_box
->depth
) <=
149 sdst
->buffer
.buf
->size
);
150 assert(ssrc
->surface
.u
.legacy
.level
[src_level
].offset
+
151 src_slice_pitch
* bpp
* (srcz
+ src_box
->depth
) <=
152 ssrc
->buffer
.buf
->size
);
154 if (!si_prepare_for_dma_blit(sctx
, sdst
, dst_level
, dstx
, dsty
,
155 dstz
, ssrc
, src_level
, src_box
))
158 dstx
/= sdst
->surface
.blk_w
;
159 dsty
/= sdst
->surface
.blk_h
;
161 if (srcx
>= (1 << 14) ||
169 dst_address
|= dst_tile_swizzle
<< 8;
170 src_address
|= src_tile_swizzle
<< 8;
172 /* Linear -> linear sub-window copy. */
173 if (dst_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
&&
174 src_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
&&
175 /* check if everything fits into the bitfields */
176 src_pitch
<= (1 << 14) &&
177 dst_pitch
<= (1 << 14) &&
178 src_slice_pitch
<= (1 << 28) &&
179 dst_slice_pitch
<= (1 << 28) &&
180 copy_width
<= (1 << 14) &&
181 copy_height
<= (1 << 14) &&
182 copy_depth
<= (1 << 11) &&
183 /* HW limitation - CIK: */
184 (sctx
->chip_class
!= CIK
||
185 (copy_width
< (1 << 14) &&
186 copy_height
< (1 << 14) &&
187 copy_depth
< (1 << 11))) &&
188 /* HW limitation - some CIK parts: */
189 ((sctx
->family
!= CHIP_BONAIRE
&&
190 sctx
->family
!= CHIP_KAVERI
) ||
191 (srcx
+ copy_width
!= (1 << 14) &&
192 srcy
+ copy_height
!= (1 << 14)))) {
193 struct radeon_cmdbuf
*cs
= sctx
->dma_cs
;
195 si_need_dma_space(sctx
, 13, &sdst
->buffer
, &ssrc
->buffer
);
197 radeon_emit(cs
, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY
,
198 CIK_SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW
, 0) |
199 (util_logbase2(bpp
) << 29));
200 radeon_emit(cs
, src_address
);
201 radeon_emit(cs
, src_address
>> 32);
202 radeon_emit(cs
, srcx
| (srcy
<< 16));
203 radeon_emit(cs
, srcz
| ((src_pitch
- 1) << 16));
204 radeon_emit(cs
, src_slice_pitch
- 1);
205 radeon_emit(cs
, dst_address
);
206 radeon_emit(cs
, dst_address
>> 32);
207 radeon_emit(cs
, dstx
| (dsty
<< 16));
208 radeon_emit(cs
, dstz
| ((dst_pitch
- 1) << 16));
209 radeon_emit(cs
, dst_slice_pitch
- 1);
210 if (sctx
->chip_class
== CIK
) {
211 radeon_emit(cs
, copy_width
| (copy_height
<< 16));
212 radeon_emit(cs
, copy_depth
);
214 radeon_emit(cs
, (copy_width
- 1) | ((copy_height
- 1) << 16));
215 radeon_emit(cs
, (copy_depth
- 1));
220 /* Tiled <-> linear sub-window copy. */
221 if ((src_mode
>= RADEON_SURF_MODE_1D
) != (dst_mode
>= RADEON_SURF_MODE_1D
)) {
222 struct si_texture
*tiled
= src_mode
>= RADEON_SURF_MODE_1D
? ssrc
: sdst
;
223 struct si_texture
*linear
= tiled
== ssrc
? sdst
: ssrc
;
224 unsigned tiled_level
= tiled
== ssrc
? src_level
: dst_level
;
225 unsigned linear_level
= linear
== ssrc
? src_level
: dst_level
;
226 unsigned tiled_x
= tiled
== ssrc
? srcx
: dstx
;
227 unsigned linear_x
= linear
== ssrc
? srcx
: dstx
;
228 unsigned tiled_y
= tiled
== ssrc
? srcy
: dsty
;
229 unsigned linear_y
= linear
== ssrc
? srcy
: dsty
;
230 unsigned tiled_z
= tiled
== ssrc
? srcz
: dstz
;
231 unsigned linear_z
= linear
== ssrc
? srcz
: dstz
;
232 unsigned tiled_width
= tiled
== ssrc
? src_width
: dst_width
;
233 unsigned linear_width
= linear
== ssrc
? src_width
: dst_width
;
234 unsigned tiled_pitch
= tiled
== ssrc
? src_pitch
: dst_pitch
;
235 unsigned linear_pitch
= linear
== ssrc
? src_pitch
: dst_pitch
;
236 unsigned tiled_slice_pitch
= tiled
== ssrc
? src_slice_pitch
: dst_slice_pitch
;
237 unsigned linear_slice_pitch
= linear
== ssrc
? src_slice_pitch
: dst_slice_pitch
;
238 uint64_t tiled_address
= tiled
== ssrc
? src_address
: dst_address
;
239 uint64_t linear_address
= linear
== ssrc
? src_address
: dst_address
;
240 unsigned tiled_micro_mode
= tiled
== ssrc
? src_micro_mode
: dst_micro_mode
;
242 assert(tiled_pitch
% 8 == 0);
243 assert(tiled_slice_pitch
% 64 == 0);
244 unsigned pitch_tile_max
= tiled_pitch
/ 8 - 1;
245 unsigned slice_tile_max
= tiled_slice_pitch
/ 64 - 1;
246 unsigned xalign
= MAX2(1, 4 / bpp
);
247 unsigned copy_width_aligned
= copy_width
;
249 /* If the region ends at the last pixel and is unaligned, we
250 * can copy the remainder of the line that is not visible to
253 if (copy_width
% xalign
!= 0 &&
254 linear_x
+ copy_width
== linear_width
&&
255 tiled_x
+ copy_width
== tiled_width
&&
256 linear_x
+ align(copy_width
, xalign
) <= linear_pitch
&&
257 tiled_x
+ align(copy_width
, xalign
) <= tiled_pitch
)
258 copy_width_aligned
= align(copy_width
, xalign
);
260 /* HW limitations. */
261 if ((sctx
->family
== CHIP_BONAIRE
||
262 sctx
->family
== CHIP_KAVERI
) &&
263 linear_pitch
- 1 == 0x3fff &&
267 if (sctx
->chip_class
== CIK
&&
268 (copy_width_aligned
== (1 << 14) ||
269 copy_height
== (1 << 14) ||
270 copy_depth
== (1 << 11)))
273 if ((sctx
->family
== CHIP_BONAIRE
||
274 sctx
->family
== CHIP_KAVERI
||
275 sctx
->family
== CHIP_KABINI
||
276 sctx
->family
== CHIP_MULLINS
) &&
277 (tiled_x
+ copy_width
== (1 << 14) ||
278 tiled_y
+ copy_height
== (1 << 14)))
281 /* The hw can read outside of the given linear buffer bounds,
282 * or access those pages but not touch the memory in case
283 * of writes. (it still causes a VM fault)
285 * Out-of-bounds memory access or page directory access must
288 int64_t start_linear_address
, end_linear_address
;
289 unsigned granularity
;
291 /* Deduce the size of reads from the linear surface. */
292 switch (tiled_micro_mode
) {
293 case V_009910_ADDR_SURF_DISPLAY_MICRO_TILING
:
294 granularity
= bpp
== 1 ? 64 / (8*bpp
) :
297 case V_009910_ADDR_SURF_THIN_MICRO_TILING
:
298 case V_009910_ADDR_SURF_DEPTH_MICRO_TILING
:
299 if (0 /* TODO: THICK microtiling */)
300 granularity
= bpp
== 1 ? 32 / (8*bpp
) :
301 bpp
== 2 ? 64 / (8*bpp
) :
302 bpp
<= 8 ? 128 / (8*bpp
) :
305 granularity
= bpp
<= 2 ? 64 / (8*bpp
) :
306 bpp
<= 8 ? 128 / (8*bpp
) :
313 /* The linear reads start at tiled_x & ~(granularity - 1).
314 * If linear_x == 0 && tiled_x % granularity != 0, the hw
315 * starts reading from an address preceding linear_address!!!
317 start_linear_address
=
318 linear
->surface
.u
.legacy
.level
[linear_level
].offset
+
319 bpp
* (linear_z
* linear_slice_pitch
+
320 linear_y
* linear_pitch
+
322 start_linear_address
-= (int)(bpp
* (tiled_x
% granularity
));
325 linear
->surface
.u
.legacy
.level
[linear_level
].offset
+
326 bpp
* ((linear_z
+ copy_depth
- 1) * linear_slice_pitch
+
327 (linear_y
+ copy_height
- 1) * linear_pitch
+
328 (linear_x
+ copy_width
));
330 if ((tiled_x
+ copy_width
) % granularity
)
331 end_linear_address
+= granularity
-
332 (tiled_x
+ copy_width
) % granularity
;
334 if (start_linear_address
< 0 ||
335 end_linear_address
> linear
->surface
.surf_size
)
338 /* Check requirements. */
339 if (tiled_address
% 256 == 0 &&
340 linear_address
% 4 == 0 &&
341 linear_pitch
% xalign
== 0 &&
342 linear_x
% xalign
== 0 &&
343 tiled_x
% xalign
== 0 &&
344 copy_width_aligned
% xalign
== 0 &&
345 tiled_micro_mode
!= V_009910_ADDR_SURF_ROTATED_MICRO_TILING
&&
346 /* check if everything fits into the bitfields */
347 tiled
->surface
.u
.legacy
.tile_split
<= 4096 &&
348 pitch_tile_max
< (1 << 11) &&
349 slice_tile_max
< (1 << 22) &&
350 linear_pitch
<= (1 << 14) &&
351 linear_slice_pitch
<= (1 << 28) &&
352 copy_width_aligned
<= (1 << 14) &&
353 copy_height
<= (1 << 14) &&
354 copy_depth
<= (1 << 11)) {
355 struct radeon_cmdbuf
*cs
= sctx
->dma_cs
;
356 uint32_t direction
= linear
== sdst
? 1u << 31 : 0;
358 si_need_dma_space(sctx
, 14, &sdst
->buffer
, &ssrc
->buffer
);
360 radeon_emit(cs
, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY
,
361 CIK_SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW
, 0) |
363 radeon_emit(cs
, tiled_address
);
364 radeon_emit(cs
, tiled_address
>> 32);
365 radeon_emit(cs
, tiled_x
| (tiled_y
<< 16));
366 radeon_emit(cs
, tiled_z
| (pitch_tile_max
<< 16));
367 radeon_emit(cs
, slice_tile_max
);
368 radeon_emit(cs
, encode_tile_info(sctx
, tiled
, tiled_level
, true));
369 radeon_emit(cs
, linear_address
);
370 radeon_emit(cs
, linear_address
>> 32);
371 radeon_emit(cs
, linear_x
| (linear_y
<< 16));
372 radeon_emit(cs
, linear_z
| ((linear_pitch
- 1) << 16));
373 radeon_emit(cs
, linear_slice_pitch
- 1);
374 if (sctx
->chip_class
== CIK
) {
375 radeon_emit(cs
, copy_width_aligned
| (copy_height
<< 16));
376 radeon_emit(cs
, copy_depth
);
378 radeon_emit(cs
, (copy_width_aligned
- 1) | ((copy_height
- 1) << 16));
379 radeon_emit(cs
, (copy_depth
- 1));
385 /* Tiled -> Tiled sub-window copy. */
386 if (dst_mode
>= RADEON_SURF_MODE_1D
&&
387 src_mode
>= RADEON_SURF_MODE_1D
&&
388 /* check if these fit into the bitfields */
389 src_address
% 256 == 0 &&
390 dst_address
% 256 == 0 &&
391 ssrc
->surface
.u
.legacy
.tile_split
<= 4096 &&
392 sdst
->surface
.u
.legacy
.tile_split
<= 4096 &&
397 /* this can either be equal, or display->rotated (VI+ only) */
398 (src_micro_mode
== dst_micro_mode
||
399 (sctx
->chip_class
>= VI
&&
400 src_micro_mode
== V_009910_ADDR_SURF_DISPLAY_MICRO_TILING
&&
401 dst_micro_mode
== V_009910_ADDR_SURF_ROTATED_MICRO_TILING
))) {
402 assert(src_pitch
% 8 == 0);
403 assert(dst_pitch
% 8 == 0);
404 assert(src_slice_pitch
% 64 == 0);
405 assert(dst_slice_pitch
% 64 == 0);
406 unsigned src_pitch_tile_max
= src_pitch
/ 8 - 1;
407 unsigned dst_pitch_tile_max
= dst_pitch
/ 8 - 1;
408 unsigned src_slice_tile_max
= src_slice_pitch
/ 64 - 1;
409 unsigned dst_slice_tile_max
= dst_slice_pitch
/ 64 - 1;
410 unsigned copy_width_aligned
= copy_width
;
411 unsigned copy_height_aligned
= copy_height
;
413 /* If the region ends at the last pixel and is unaligned, we
414 * can copy the remainder of the tile that is not visible to
417 if (copy_width
% 8 != 0 &&
418 srcx
+ copy_width
== src_width
&&
419 dstx
+ copy_width
== dst_width
)
420 copy_width_aligned
= align(copy_width
, 8);
422 if (copy_height
% 8 != 0 &&
423 srcy
+ copy_height
== src_height
&&
424 dsty
+ copy_height
== dst_height
)
425 copy_height_aligned
= align(copy_height
, 8);
427 /* check if these fit into the bitfields */
428 if (src_pitch_tile_max
< (1 << 11) &&
429 dst_pitch_tile_max
< (1 << 11) &&
430 src_slice_tile_max
< (1 << 22) &&
431 dst_slice_tile_max
< (1 << 22) &&
432 copy_width_aligned
<= (1 << 14) &&
433 copy_height_aligned
<= (1 << 14) &&
434 copy_depth
<= (1 << 11) &&
435 copy_width_aligned
% 8 == 0 &&
436 copy_height_aligned
% 8 == 0 &&
437 /* HW limitation - CIK: */
438 (sctx
->chip_class
!= CIK
||
439 (copy_width_aligned
< (1 << 14) &&
440 copy_height_aligned
< (1 << 14) &&
441 copy_depth
< (1 << 11))) &&
442 /* HW limitation - some CIK parts: */
443 ((sctx
->family
!= CHIP_BONAIRE
&&
444 sctx
->family
!= CHIP_KAVERI
&&
445 sctx
->family
!= CHIP_KABINI
&&
446 sctx
->family
!= CHIP_MULLINS
) ||
447 (srcx
+ copy_width_aligned
!= (1 << 14) &&
448 srcy
+ copy_height_aligned
!= (1 << 14) &&
449 dstx
+ copy_width
!= (1 << 14)))) {
450 struct radeon_cmdbuf
*cs
= sctx
->dma_cs
;
452 si_need_dma_space(sctx
, 15, &sdst
->buffer
, &ssrc
->buffer
);
454 radeon_emit(cs
, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY
,
455 CIK_SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW
, 0));
456 radeon_emit(cs
, src_address
);
457 radeon_emit(cs
, src_address
>> 32);
458 radeon_emit(cs
, srcx
| (srcy
<< 16));
459 radeon_emit(cs
, srcz
| (src_pitch_tile_max
<< 16));
460 radeon_emit(cs
, src_slice_tile_max
);
461 radeon_emit(cs
, encode_tile_info(sctx
, ssrc
, src_level
, true));
462 radeon_emit(cs
, dst_address
);
463 radeon_emit(cs
, dst_address
>> 32);
464 radeon_emit(cs
, dstx
| (dsty
<< 16));
465 radeon_emit(cs
, dstz
| (dst_pitch_tile_max
<< 16));
466 radeon_emit(cs
, dst_slice_tile_max
);
467 radeon_emit(cs
, encode_tile_info(sctx
, sdst
, dst_level
, false));
468 if (sctx
->chip_class
== CIK
) {
469 radeon_emit(cs
, copy_width_aligned
|
470 (copy_height_aligned
<< 16));
471 radeon_emit(cs
, copy_depth
);
473 radeon_emit(cs
, (copy_width_aligned
- 8) |
474 ((copy_height_aligned
- 8) << 16));
475 radeon_emit(cs
, (copy_depth
- 1));
484 static void cik_sdma_copy(struct pipe_context
*ctx
,
485 struct pipe_resource
*dst
,
487 unsigned dstx
, unsigned dsty
, unsigned dstz
,
488 struct pipe_resource
*src
,
490 const struct pipe_box
*src_box
)
492 struct si_context
*sctx
= (struct si_context
*)ctx
;
495 src
->flags
& PIPE_RESOURCE_FLAG_SPARSE
||
496 dst
->flags
& PIPE_RESOURCE_FLAG_SPARSE
)
499 /* If src is a buffer and dst is a texture, we are uploading metadata. */
500 if (src
->target
== PIPE_BUFFER
) {
501 cik_sdma_copy_buffer(sctx
, dst
, src
, dstx
, src_box
->x
, src_box
->width
);
505 if ((sctx
->chip_class
== CIK
|| sctx
->chip_class
== VI
) &&
506 cik_sdma_copy_texture(sctx
, dst
, dst_level
, dstx
, dsty
, dstz
,
507 src
, src_level
, src_box
))
511 si_resource_copy_region(ctx
, dst
, dst_level
, dstx
, dsty
, dstz
,
512 src
, src_level
, src_box
);
515 void cik_init_sdma_functions(struct si_context
*sctx
)
517 sctx
->dma_copy
= cik_sdma_copy
;