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radeonsi: fold si_create_function into si_llvm_create_func
[mesa.git] / src / gallium / drivers / radeonsi / cik_sdma.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2015 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "sid.h"
27 #include "si_pipe.h"
28
29 static unsigned minify_as_blocks(unsigned width, unsigned level, unsigned blk_w)
30 {
31 width = u_minify(width, level);
32 return DIV_ROUND_UP(width, blk_w);
33 }
34
35 static unsigned encode_tile_info(struct si_context *sctx,
36 struct si_texture *tex, unsigned level,
37 bool set_bpp)
38 {
39 struct radeon_info *info = &sctx->screen->info;
40 unsigned tile_index = tex->surface.u.legacy.tiling_index[level];
41 unsigned macro_tile_index = tex->surface.u.legacy.macro_tile_index;
42 unsigned tile_mode = info->si_tile_mode_array[tile_index];
43 unsigned macro_tile_mode = info->cik_macrotile_mode_array[macro_tile_index];
44
45 return (set_bpp ? util_logbase2(tex->surface.bpe) : 0) |
46 (G_009910_ARRAY_MODE(tile_mode) << 3) |
47 (G_009910_MICRO_TILE_MODE_NEW(tile_mode) << 8) |
48 /* Non-depth modes don't have TILE_SPLIT set. */
49 ((util_logbase2(tex->surface.u.legacy.tile_split >> 6)) << 11) |
50 (G_009990_BANK_WIDTH(macro_tile_mode) << 15) |
51 (G_009990_BANK_HEIGHT(macro_tile_mode) << 18) |
52 (G_009990_NUM_BANKS(macro_tile_mode) << 21) |
53 (G_009990_MACRO_TILE_ASPECT(macro_tile_mode) << 24) |
54 (G_009910_PIPE_CONFIG(tile_mode) << 26);
55 }
56
57
58 static bool si_sdma_v4_copy_texture(struct si_context *sctx,
59 struct pipe_resource *dst,
60 unsigned dst_level,
61 unsigned dstx, unsigned dsty, unsigned dstz,
62 struct pipe_resource *src,
63 unsigned src_level,
64 const struct pipe_box *src_box)
65 {
66 struct si_texture *ssrc = (struct si_texture*)src;
67 struct si_texture *sdst = (struct si_texture*)dst;
68
69 unsigned bpp = sdst->surface.bpe;
70 uint64_t dst_address = sdst->buffer.gpu_address +
71 sdst->surface.u.gfx9.surf_offset;
72 uint64_t src_address = ssrc->buffer.gpu_address +
73 ssrc->surface.u.gfx9.surf_offset;
74 unsigned dst_pitch = sdst->surface.u.gfx9.surf_pitch;
75 unsigned src_pitch = ssrc->surface.u.gfx9.surf_pitch;
76 uint64_t dst_slice_pitch = ((uint64_t)sdst->surface.u.gfx9.surf_slice_size) / bpp;
77 uint64_t src_slice_pitch = ((uint64_t)ssrc->surface.u.gfx9.surf_slice_size) / bpp;
78 unsigned srcx = src_box->x / ssrc->surface.blk_w;
79 unsigned srcy = src_box->y / ssrc->surface.blk_h;
80 unsigned srcz = src_box->z;
81 unsigned copy_width = DIV_ROUND_UP(src_box->width, ssrc->surface.blk_w);
82 unsigned copy_height = DIV_ROUND_UP(src_box->height, ssrc->surface.blk_h);
83 unsigned copy_depth = src_box->depth;
84 unsigned xalign = MAX2(1, 4 / bpp);
85
86 assert(src_level <= src->last_level);
87 assert(dst_level <= dst->last_level);
88 assert(sdst->surface.u.gfx9.surf_offset +
89 dst_slice_pitch * bpp * (dstz + src_box->depth) <=
90 sdst->buffer.buf->size);
91 assert(ssrc->surface.u.gfx9.surf_offset +
92 src_slice_pitch * bpp * (srcz + src_box->depth) <=
93 ssrc->buffer.buf->size);
94
95 if (!si_prepare_for_dma_blit(sctx, sdst, dst_level, dstx, dsty,
96 dstz, ssrc, src_level, src_box))
97 return false;
98
99 dstx /= sdst->surface.blk_w;
100 dsty /= sdst->surface.blk_h;
101
102 if (srcx >= (1 << 14) ||
103 srcy >= (1 << 14) ||
104 srcz >= (1 << 11) ||
105 dstx >= (1 << 14) ||
106 dsty >= (1 << 14) ||
107 dstz >= (1 << 11))
108 return false;
109
110 /* Linear -> linear sub-window copy. */
111 if (ssrc->surface.is_linear &&
112 sdst->surface.is_linear) {
113 struct radeon_cmdbuf *cs = sctx->sdma_cs;
114
115 /* Check if everything fits into the bitfields */
116 if (!(src_pitch <= (1 << 19) &&
117 dst_pitch <= (1 << 19) &&
118 src_slice_pitch <= (1 << 28) &&
119 dst_slice_pitch <= (1 << 28) &&
120 copy_width <= (1 << 14) &&
121 copy_height <= (1 << 14) &&
122 copy_depth <= (1 << 11)))
123 return false;
124
125 si_need_dma_space(sctx, 13, &sdst->buffer, &ssrc->buffer);
126
127 src_address += ssrc->surface.u.gfx9.offset[src_level];
128 dst_address += sdst->surface.u.gfx9.offset[dst_level];
129
130 /* Check alignments */
131 if ((src_address % 4) != 0 ||
132 (dst_address % 4) != 0 ||
133 (src_pitch % xalign) != 0)
134 return false;
135
136 radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
137 CIK_SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW, 0) |
138 (util_logbase2(bpp) << 29));
139 radeon_emit(cs, src_address);
140 radeon_emit(cs, src_address >> 32);
141 radeon_emit(cs, srcx | (srcy << 16));
142 radeon_emit(cs, srcz | ((src_pitch - 1) << 13));
143 radeon_emit(cs, src_slice_pitch - 1);
144 radeon_emit(cs, dst_address);
145 radeon_emit(cs, dst_address >> 32);
146 radeon_emit(cs, dstx | (dsty << 16));
147 radeon_emit(cs, dstz | ((dst_pitch - 1) << 13));
148 radeon_emit(cs, dst_slice_pitch - 1);
149 radeon_emit(cs, (copy_width - 1) | ((copy_height - 1) << 16));
150 radeon_emit(cs, (copy_depth - 1));
151 return true;
152 }
153
154 /* Linear <-> Tiled sub-window copy */
155 if (ssrc->surface.is_linear != sdst->surface.is_linear) {
156 struct si_texture *tiled = ssrc->surface.is_linear ? sdst : ssrc;
157 struct si_texture *linear = tiled == ssrc ? sdst : ssrc;
158 unsigned tiled_level = tiled == ssrc ? src_level : dst_level;
159 unsigned linear_level = linear == ssrc ? src_level : dst_level;
160 unsigned tiled_x = tiled == ssrc ? srcx : dstx;
161 unsigned linear_x = linear == ssrc ? srcx : dstx;
162 unsigned tiled_y = tiled == ssrc ? srcy : dsty;
163 unsigned linear_y = linear == ssrc ? srcy : dsty;
164 unsigned tiled_z = tiled == ssrc ? srcz : dstz;
165 unsigned linear_z = linear == ssrc ? srcz : dstz;
166 unsigned tiled_width = tiled == ssrc ?
167 DIV_ROUND_UP(ssrc->buffer.b.b.width0, ssrc->surface.blk_w) :
168 DIV_ROUND_UP(sdst->buffer.b.b.width0, sdst->surface.blk_w);
169 unsigned tiled_height = tiled == ssrc ?
170 DIV_ROUND_UP(ssrc->buffer.b.b.height0, ssrc->surface.blk_h) :
171 DIV_ROUND_UP(sdst->buffer.b.b.height0, sdst->surface.blk_h);
172 unsigned tiled_depth = tiled == ssrc ?
173 ssrc->buffer.b.b.depth0 :
174 sdst->buffer.b.b.depth0;
175 unsigned linear_pitch = linear == ssrc ? src_pitch : dst_pitch;
176 unsigned linear_slice_pitch = linear == ssrc ? src_slice_pitch : dst_slice_pitch;
177 uint64_t tiled_address = tiled == ssrc ? src_address : dst_address;
178 uint64_t linear_address = linear == ssrc ? src_address : dst_address;
179 struct radeon_cmdbuf *cs = sctx->sdma_cs;
180
181 linear_address += linear->surface.u.gfx9.offset[linear_level];
182
183 /* Check if everything fits into the bitfields */
184 if (!(tiled_x <= (1 << 14) &&
185 tiled_y <= (1 << 14) &&
186 tiled_z <= (1 << 11) &&
187 tiled_width <= (1 << 14) &&
188 tiled_height <= (1 << 14) &&
189 tiled_depth <= (1 << 11) &&
190 tiled->surface.u.gfx9.surf.epitch <= (1 << 16) &&
191 linear_x <= (1 << 14) &&
192 linear_y <= (1 << 14) &&
193 linear_z <= (1 << 11) &&
194 linear_pitch <= (1 << 14) &&
195 linear_slice_pitch <= (1 << 28) &&
196 copy_width <= (1 << 14) &&
197 copy_height <= (1 << 14) &&
198 copy_depth <= (1 << 11)))
199 return false;
200
201 /* Check alignments */
202 if ((tiled_address % 256 != 0) ||
203 (linear_address % 4 != 0) ||
204 (linear_pitch % xalign != 0) ||
205 (linear_slice_pitch % xalign != 0))
206 return false;
207
208 si_need_dma_space(sctx, 14, &sdst->buffer, &ssrc->buffer);
209
210 radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
211 CIK_SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW, 0) |
212 tiled->buffer.b.b.last_level << 20 |
213 tiled_level << 24 |
214 (linear == sdst ? 1u : 0) << 31);
215 radeon_emit(cs, (uint32_t) tiled_address);
216 radeon_emit(cs, (uint32_t) (tiled_address >> 32));
217 radeon_emit(cs, tiled_x | (tiled_y << 16));
218 radeon_emit(cs, tiled_z | ((tiled_width - 1) << 16));
219 radeon_emit(cs, (tiled_height - 1) | (tiled_depth - 1) << 16);
220 radeon_emit(cs, util_logbase2(bpp) |
221 tiled->surface.u.gfx9.surf.swizzle_mode << 3 |
222 tiled->surface.u.gfx9.resource_type << 9 |
223 tiled->surface.u.gfx9.surf.epitch << 16);
224 radeon_emit(cs, (uint32_t) linear_address);
225 radeon_emit(cs, (uint32_t) (linear_address >> 32));
226 radeon_emit(cs, linear_x | (linear_y << 16));
227 radeon_emit(cs, linear_z | ((linear_pitch - 1) << 16));
228 radeon_emit(cs, linear_slice_pitch - 1);
229 radeon_emit(cs, (copy_width - 1) | ((copy_height - 1) << 16));
230 radeon_emit(cs, (copy_depth - 1));
231 return true;
232 }
233
234 return false;
235 }
236
237 static bool cik_sdma_copy_texture(struct si_context *sctx,
238 struct pipe_resource *dst,
239 unsigned dst_level,
240 unsigned dstx, unsigned dsty, unsigned dstz,
241 struct pipe_resource *src,
242 unsigned src_level,
243 const struct pipe_box *src_box)
244 {
245 struct radeon_info *info = &sctx->screen->info;
246 struct si_texture *ssrc = (struct si_texture*)src;
247 struct si_texture *sdst = (struct si_texture*)dst;
248 unsigned bpp = sdst->surface.bpe;
249 uint64_t dst_address = sdst->buffer.gpu_address +
250 sdst->surface.u.legacy.level[dst_level].offset;
251 uint64_t src_address = ssrc->buffer.gpu_address +
252 ssrc->surface.u.legacy.level[src_level].offset;
253 unsigned dst_mode = sdst->surface.u.legacy.level[dst_level].mode;
254 unsigned src_mode = ssrc->surface.u.legacy.level[src_level].mode;
255 unsigned dst_tile_index = sdst->surface.u.legacy.tiling_index[dst_level];
256 unsigned src_tile_index = ssrc->surface.u.legacy.tiling_index[src_level];
257 unsigned dst_tile_mode = info->si_tile_mode_array[dst_tile_index];
258 unsigned src_tile_mode = info->si_tile_mode_array[src_tile_index];
259 unsigned dst_micro_mode = G_009910_MICRO_TILE_MODE_NEW(dst_tile_mode);
260 unsigned src_micro_mode = G_009910_MICRO_TILE_MODE_NEW(src_tile_mode);
261 unsigned dst_tile_swizzle = dst_mode == RADEON_SURF_MODE_2D ?
262 sdst->surface.tile_swizzle : 0;
263 unsigned src_tile_swizzle = src_mode == RADEON_SURF_MODE_2D ?
264 ssrc->surface.tile_swizzle : 0;
265 unsigned dst_pitch = sdst->surface.u.legacy.level[dst_level].nblk_x;
266 unsigned src_pitch = ssrc->surface.u.legacy.level[src_level].nblk_x;
267 uint64_t dst_slice_pitch = ((uint64_t)sdst->surface.u.legacy.level[dst_level].slice_size_dw * 4) / bpp;
268 uint64_t src_slice_pitch = ((uint64_t)ssrc->surface.u.legacy.level[src_level].slice_size_dw * 4) / bpp;
269 unsigned dst_width = minify_as_blocks(sdst->buffer.b.b.width0,
270 dst_level, sdst->surface.blk_w);
271 unsigned src_width = minify_as_blocks(ssrc->buffer.b.b.width0,
272 src_level, ssrc->surface.blk_w);
273 unsigned dst_height = minify_as_blocks(sdst->buffer.b.b.height0,
274 dst_level, sdst->surface.blk_h);
275 unsigned src_height = minify_as_blocks(ssrc->buffer.b.b.height0,
276 src_level, ssrc->surface.blk_h);
277 unsigned srcx = src_box->x / ssrc->surface.blk_w;
278 unsigned srcy = src_box->y / ssrc->surface.blk_h;
279 unsigned srcz = src_box->z;
280 unsigned copy_width = DIV_ROUND_UP(src_box->width, ssrc->surface.blk_w);
281 unsigned copy_height = DIV_ROUND_UP(src_box->height, ssrc->surface.blk_h);
282 unsigned copy_depth = src_box->depth;
283
284 assert(src_level <= src->last_level);
285 assert(dst_level <= dst->last_level);
286 assert(sdst->surface.u.legacy.level[dst_level].offset +
287 dst_slice_pitch * bpp * (dstz + src_box->depth) <=
288 sdst->buffer.buf->size);
289 assert(ssrc->surface.u.legacy.level[src_level].offset +
290 src_slice_pitch * bpp * (srcz + src_box->depth) <=
291 ssrc->buffer.buf->size);
292
293 if (!si_prepare_for_dma_blit(sctx, sdst, dst_level, dstx, dsty,
294 dstz, ssrc, src_level, src_box))
295 return false;
296
297 dstx /= sdst->surface.blk_w;
298 dsty /= sdst->surface.blk_h;
299
300 if (srcx >= (1 << 14) ||
301 srcy >= (1 << 14) ||
302 srcz >= (1 << 11) ||
303 dstx >= (1 << 14) ||
304 dsty >= (1 << 14) ||
305 dstz >= (1 << 11))
306 return false;
307
308 dst_address |= dst_tile_swizzle << 8;
309 src_address |= src_tile_swizzle << 8;
310
311 /* Linear -> linear sub-window copy. */
312 if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED &&
313 src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED &&
314 /* check if everything fits into the bitfields */
315 src_pitch <= (1 << 14) &&
316 dst_pitch <= (1 << 14) &&
317 src_slice_pitch <= (1 << 28) &&
318 dst_slice_pitch <= (1 << 28) &&
319 copy_width <= (1 << 14) &&
320 copy_height <= (1 << 14) &&
321 copy_depth <= (1 << 11) &&
322 /* HW limitation - GFX7: */
323 (sctx->chip_class != GFX7 ||
324 (copy_width < (1 << 14) &&
325 copy_height < (1 << 14) &&
326 copy_depth < (1 << 11))) &&
327 /* HW limitation - some GFX7 parts: */
328 ((sctx->family != CHIP_BONAIRE &&
329 sctx->family != CHIP_KAVERI) ||
330 (srcx + copy_width != (1 << 14) &&
331 srcy + copy_height != (1 << 14)))) {
332 struct radeon_cmdbuf *cs = sctx->sdma_cs;
333
334 si_need_dma_space(sctx, 13, &sdst->buffer, &ssrc->buffer);
335
336 radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
337 CIK_SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW, 0) |
338 (util_logbase2(bpp) << 29));
339 radeon_emit(cs, src_address);
340 radeon_emit(cs, src_address >> 32);
341 radeon_emit(cs, srcx | (srcy << 16));
342 radeon_emit(cs, srcz | ((src_pitch - 1) << 16));
343 radeon_emit(cs, src_slice_pitch - 1);
344 radeon_emit(cs, dst_address);
345 radeon_emit(cs, dst_address >> 32);
346 radeon_emit(cs, dstx | (dsty << 16));
347 radeon_emit(cs, dstz | ((dst_pitch - 1) << 16));
348 radeon_emit(cs, dst_slice_pitch - 1);
349 if (sctx->chip_class == GFX7) {
350 radeon_emit(cs, copy_width | (copy_height << 16));
351 radeon_emit(cs, copy_depth);
352 } else {
353 radeon_emit(cs, (copy_width - 1) | ((copy_height - 1) << 16));
354 radeon_emit(cs, (copy_depth - 1));
355 }
356 return true;
357 }
358
359 /* Tiled <-> linear sub-window copy. */
360 if ((src_mode >= RADEON_SURF_MODE_1D) != (dst_mode >= RADEON_SURF_MODE_1D)) {
361 struct si_texture *tiled = src_mode >= RADEON_SURF_MODE_1D ? ssrc : sdst;
362 struct si_texture *linear = tiled == ssrc ? sdst : ssrc;
363 unsigned tiled_level = tiled == ssrc ? src_level : dst_level;
364 unsigned linear_level = linear == ssrc ? src_level : dst_level;
365 unsigned tiled_x = tiled == ssrc ? srcx : dstx;
366 unsigned linear_x = linear == ssrc ? srcx : dstx;
367 unsigned tiled_y = tiled == ssrc ? srcy : dsty;
368 unsigned linear_y = linear == ssrc ? srcy : dsty;
369 unsigned tiled_z = tiled == ssrc ? srcz : dstz;
370 unsigned linear_z = linear == ssrc ? srcz : dstz;
371 unsigned tiled_width = tiled == ssrc ? src_width : dst_width;
372 unsigned linear_width = linear == ssrc ? src_width : dst_width;
373 unsigned tiled_pitch = tiled == ssrc ? src_pitch : dst_pitch;
374 unsigned linear_pitch = linear == ssrc ? src_pitch : dst_pitch;
375 unsigned tiled_slice_pitch = tiled == ssrc ? src_slice_pitch : dst_slice_pitch;
376 unsigned linear_slice_pitch = linear == ssrc ? src_slice_pitch : dst_slice_pitch;
377 uint64_t tiled_address = tiled == ssrc ? src_address : dst_address;
378 uint64_t linear_address = linear == ssrc ? src_address : dst_address;
379 unsigned tiled_micro_mode = tiled == ssrc ? src_micro_mode : dst_micro_mode;
380
381 assert(tiled_pitch % 8 == 0);
382 assert(tiled_slice_pitch % 64 == 0);
383 unsigned pitch_tile_max = tiled_pitch / 8 - 1;
384 unsigned slice_tile_max = tiled_slice_pitch / 64 - 1;
385 unsigned xalign = MAX2(1, 4 / bpp);
386 unsigned copy_width_aligned = copy_width;
387
388 /* If the region ends at the last pixel and is unaligned, we
389 * can copy the remainder of the line that is not visible to
390 * make it aligned.
391 */
392 if (copy_width % xalign != 0 &&
393 linear_x + copy_width == linear_width &&
394 tiled_x + copy_width == tiled_width &&
395 linear_x + align(copy_width, xalign) <= linear_pitch &&
396 tiled_x + align(copy_width, xalign) <= tiled_pitch)
397 copy_width_aligned = align(copy_width, xalign);
398
399 /* HW limitations. */
400 if ((sctx->family == CHIP_BONAIRE ||
401 sctx->family == CHIP_KAVERI) &&
402 linear_pitch - 1 == 0x3fff &&
403 bpp == 16)
404 return false;
405
406 if (sctx->chip_class == GFX7 &&
407 (copy_width_aligned == (1 << 14) ||
408 copy_height == (1 << 14) ||
409 copy_depth == (1 << 11)))
410 return false;
411
412 if ((sctx->family == CHIP_BONAIRE ||
413 sctx->family == CHIP_KAVERI ||
414 sctx->family == CHIP_KABINI) &&
415 (tiled_x + copy_width == (1 << 14) ||
416 tiled_y + copy_height == (1 << 14)))
417 return false;
418
419 /* The hw can read outside of the given linear buffer bounds,
420 * or access those pages but not touch the memory in case
421 * of writes. (it still causes a VM fault)
422 *
423 * Out-of-bounds memory access or page directory access must
424 * be prevented.
425 */
426 int64_t start_linear_address, end_linear_address;
427 unsigned granularity;
428
429 /* Deduce the size of reads from the linear surface. */
430 switch (tiled_micro_mode) {
431 case V_009910_ADDR_SURF_DISPLAY_MICRO_TILING:
432 granularity = bpp == 1 ? 64 / (8*bpp) :
433 128 / (8*bpp);
434 break;
435 case V_009910_ADDR_SURF_THIN_MICRO_TILING:
436 case V_009910_ADDR_SURF_DEPTH_MICRO_TILING:
437 if (0 /* TODO: THICK microtiling */)
438 granularity = bpp == 1 ? 32 / (8*bpp) :
439 bpp == 2 ? 64 / (8*bpp) :
440 bpp <= 8 ? 128 / (8*bpp) :
441 256 / (8*bpp);
442 else
443 granularity = bpp <= 2 ? 64 / (8*bpp) :
444 bpp <= 8 ? 128 / (8*bpp) :
445 256 / (8*bpp);
446 break;
447 default:
448 return false;
449 }
450
451 /* The linear reads start at tiled_x & ~(granularity - 1).
452 * If linear_x == 0 && tiled_x % granularity != 0, the hw
453 * starts reading from an address preceding linear_address!!!
454 */
455 start_linear_address =
456 linear->surface.u.legacy.level[linear_level].offset +
457 bpp * (linear_z * linear_slice_pitch +
458 linear_y * linear_pitch +
459 linear_x);
460 start_linear_address -= (int)(bpp * (tiled_x % granularity));
461
462 end_linear_address =
463 linear->surface.u.legacy.level[linear_level].offset +
464 bpp * ((linear_z + copy_depth - 1) * linear_slice_pitch +
465 (linear_y + copy_height - 1) * linear_pitch +
466 (linear_x + copy_width));
467
468 if ((tiled_x + copy_width) % granularity)
469 end_linear_address += granularity -
470 (tiled_x + copy_width) % granularity;
471
472 if (start_linear_address < 0 ||
473 end_linear_address > linear->surface.surf_size)
474 return false;
475
476 /* Check requirements. */
477 if (tiled_address % 256 == 0 &&
478 linear_address % 4 == 0 &&
479 linear_pitch % xalign == 0 &&
480 linear_x % xalign == 0 &&
481 tiled_x % xalign == 0 &&
482 copy_width_aligned % xalign == 0 &&
483 tiled_micro_mode != V_009910_ADDR_SURF_ROTATED_MICRO_TILING &&
484 /* check if everything fits into the bitfields */
485 tiled->surface.u.legacy.tile_split <= 4096 &&
486 pitch_tile_max < (1 << 11) &&
487 slice_tile_max < (1 << 22) &&
488 linear_pitch <= (1 << 14) &&
489 linear_slice_pitch <= (1 << 28) &&
490 copy_width_aligned <= (1 << 14) &&
491 copy_height <= (1 << 14) &&
492 copy_depth <= (1 << 11)) {
493 struct radeon_cmdbuf *cs = sctx->sdma_cs;
494 uint32_t direction = linear == sdst ? 1u << 31 : 0;
495
496 si_need_dma_space(sctx, 14, &sdst->buffer, &ssrc->buffer);
497
498 radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
499 CIK_SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW, 0) |
500 direction);
501 radeon_emit(cs, tiled_address);
502 radeon_emit(cs, tiled_address >> 32);
503 radeon_emit(cs, tiled_x | (tiled_y << 16));
504 radeon_emit(cs, tiled_z | (pitch_tile_max << 16));
505 radeon_emit(cs, slice_tile_max);
506 radeon_emit(cs, encode_tile_info(sctx, tiled, tiled_level, true));
507 radeon_emit(cs, linear_address);
508 radeon_emit(cs, linear_address >> 32);
509 radeon_emit(cs, linear_x | (linear_y << 16));
510 radeon_emit(cs, linear_z | ((linear_pitch - 1) << 16));
511 radeon_emit(cs, linear_slice_pitch - 1);
512 if (sctx->chip_class == GFX7) {
513 radeon_emit(cs, copy_width_aligned | (copy_height << 16));
514 radeon_emit(cs, copy_depth);
515 } else {
516 radeon_emit(cs, (copy_width_aligned - 1) | ((copy_height - 1) << 16));
517 radeon_emit(cs, (copy_depth - 1));
518 }
519 return true;
520 }
521 }
522
523 /* Tiled -> Tiled sub-window copy. */
524 if (dst_mode >= RADEON_SURF_MODE_1D &&
525 src_mode >= RADEON_SURF_MODE_1D &&
526 /* check if these fit into the bitfields */
527 src_address % 256 == 0 &&
528 dst_address % 256 == 0 &&
529 ssrc->surface.u.legacy.tile_split <= 4096 &&
530 sdst->surface.u.legacy.tile_split <= 4096 &&
531 dstx % 8 == 0 &&
532 dsty % 8 == 0 &&
533 srcx % 8 == 0 &&
534 srcy % 8 == 0 &&
535 /* this can either be equal, or display->rotated (GFX8+ only) */
536 (src_micro_mode == dst_micro_mode ||
537 (sctx->chip_class >= GFX8 &&
538 src_micro_mode == V_009910_ADDR_SURF_DISPLAY_MICRO_TILING &&
539 dst_micro_mode == V_009910_ADDR_SURF_ROTATED_MICRO_TILING))) {
540 assert(src_pitch % 8 == 0);
541 assert(dst_pitch % 8 == 0);
542 assert(src_slice_pitch % 64 == 0);
543 assert(dst_slice_pitch % 64 == 0);
544 unsigned src_pitch_tile_max = src_pitch / 8 - 1;
545 unsigned dst_pitch_tile_max = dst_pitch / 8 - 1;
546 unsigned src_slice_tile_max = src_slice_pitch / 64 - 1;
547 unsigned dst_slice_tile_max = dst_slice_pitch / 64 - 1;
548 unsigned copy_width_aligned = copy_width;
549 unsigned copy_height_aligned = copy_height;
550
551 /* If the region ends at the last pixel and is unaligned, we
552 * can copy the remainder of the tile that is not visible to
553 * make it aligned.
554 */
555 if (copy_width % 8 != 0 &&
556 srcx + copy_width == src_width &&
557 dstx + copy_width == dst_width)
558 copy_width_aligned = align(copy_width, 8);
559
560 if (copy_height % 8 != 0 &&
561 srcy + copy_height == src_height &&
562 dsty + copy_height == dst_height)
563 copy_height_aligned = align(copy_height, 8);
564
565 /* check if these fit into the bitfields */
566 if (src_pitch_tile_max < (1 << 11) &&
567 dst_pitch_tile_max < (1 << 11) &&
568 src_slice_tile_max < (1 << 22) &&
569 dst_slice_tile_max < (1 << 22) &&
570 copy_width_aligned <= (1 << 14) &&
571 copy_height_aligned <= (1 << 14) &&
572 copy_depth <= (1 << 11) &&
573 copy_width_aligned % 8 == 0 &&
574 copy_height_aligned % 8 == 0 &&
575 /* HW limitation - GFX7: */
576 (sctx->chip_class != GFX7 ||
577 (copy_width_aligned < (1 << 14) &&
578 copy_height_aligned < (1 << 14) &&
579 copy_depth < (1 << 11))) &&
580 /* HW limitation - some GFX7 parts: */
581 ((sctx->family != CHIP_BONAIRE &&
582 sctx->family != CHIP_KAVERI &&
583 sctx->family != CHIP_KABINI) ||
584 (srcx + copy_width_aligned != (1 << 14) &&
585 srcy + copy_height_aligned != (1 << 14) &&
586 dstx + copy_width != (1 << 14)))) {
587 struct radeon_cmdbuf *cs = sctx->sdma_cs;
588
589 si_need_dma_space(sctx, 15, &sdst->buffer, &ssrc->buffer);
590
591 radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
592 CIK_SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW, 0));
593 radeon_emit(cs, src_address);
594 radeon_emit(cs, src_address >> 32);
595 radeon_emit(cs, srcx | (srcy << 16));
596 radeon_emit(cs, srcz | (src_pitch_tile_max << 16));
597 radeon_emit(cs, src_slice_tile_max);
598 radeon_emit(cs, encode_tile_info(sctx, ssrc, src_level, true));
599 radeon_emit(cs, dst_address);
600 radeon_emit(cs, dst_address >> 32);
601 radeon_emit(cs, dstx | (dsty << 16));
602 radeon_emit(cs, dstz | (dst_pitch_tile_max << 16));
603 radeon_emit(cs, dst_slice_tile_max);
604 radeon_emit(cs, encode_tile_info(sctx, sdst, dst_level, false));
605 if (sctx->chip_class == GFX7) {
606 radeon_emit(cs, copy_width_aligned |
607 (copy_height_aligned << 16));
608 radeon_emit(cs, copy_depth);
609 } else {
610 radeon_emit(cs, (copy_width_aligned - 8) |
611 ((copy_height_aligned - 8) << 16));
612 radeon_emit(cs, (copy_depth - 1));
613 }
614 return true;
615 }
616 }
617
618 return false;
619 }
620
621 static void cik_sdma_copy(struct pipe_context *ctx,
622 struct pipe_resource *dst,
623 unsigned dst_level,
624 unsigned dstx, unsigned dsty, unsigned dstz,
625 struct pipe_resource *src,
626 unsigned src_level,
627 const struct pipe_box *src_box)
628 {
629 struct si_context *sctx = (struct si_context *)ctx;
630
631 assert(src->target != PIPE_BUFFER);
632
633 if (!sctx->sdma_cs ||
634 src->flags & PIPE_RESOURCE_FLAG_SPARSE ||
635 dst->flags & PIPE_RESOURCE_FLAG_SPARSE)
636 goto fallback;
637
638 /* SDMA causes corruption. See:
639 * https://bugs.freedesktop.org/show_bug.cgi?id=110575
640 * https://bugs.freedesktop.org/show_bug.cgi?id=110635
641 *
642 * Keep SDMA enabled on APUs.
643 */
644 if (sctx->screen->debug_flags & DBG(FORCE_SDMA) ||
645 (!sctx->screen->info.has_dedicated_vram &&
646 !(sctx->screen->debug_flags & DBG(NO_SDMA_COPY_IMAGE)))) {
647 if ((sctx->chip_class == GFX7 || sctx->chip_class == GFX8) &&
648 cik_sdma_copy_texture(sctx, dst, dst_level, dstx, dsty, dstz,
649 src, src_level, src_box))
650 return;
651 else if (sctx->chip_class == GFX9 &&
652 si_sdma_v4_copy_texture(sctx, dst, dst_level, dstx, dsty, dstz,
653 src, src_level, src_box))
654 return;
655 }
656
657 fallback:
658 si_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
659 src, src_level, src_box);
660 }
661
662 void cik_init_sdma_functions(struct si_context *sctx)
663 {
664 sctx->dma_copy = cik_sdma_copy;
665 }