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radeonsi: rename dma_cs -> sdma_cs
[mesa.git] / src / gallium / drivers / radeonsi / cik_sdma.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2015 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "sid.h"
27 #include "si_pipe.h"
28
29 static void cik_sdma_copy_buffer(struct si_context *ctx,
30 struct pipe_resource *dst,
31 struct pipe_resource *src,
32 uint64_t dst_offset,
33 uint64_t src_offset,
34 uint64_t size)
35 {
36 struct radeon_cmdbuf *cs = ctx->sdma_cs;
37 unsigned i, ncopy, csize;
38 unsigned align = ~0u;
39 struct si_resource *sdst = si_resource(dst);
40 struct si_resource *ssrc = si_resource(src);
41
42 /* Mark the buffer range of destination as valid (initialized),
43 * so that transfer_map knows it should wait for the GPU when mapping
44 * that range. */
45 util_range_add(dst, &sdst->valid_buffer_range, dst_offset,
46 dst_offset + size);
47
48 dst_offset += sdst->gpu_address;
49 src_offset += ssrc->gpu_address;
50
51 ncopy = DIV_ROUND_UP(size, CIK_SDMA_COPY_MAX_SIZE);
52
53 /* Align copy size to dw if src/dst address are dw aligned */
54 if ((src_offset & 0x3) == 0 &&
55 (dst_offset & 0x3) == 0 &&
56 size > 4 &&
57 (size & 3) != 0) {
58 align = ~0x3u;
59 ncopy++;
60 }
61
62 si_need_dma_space(ctx, ncopy * 7, sdst, ssrc);
63
64 for (i = 0; i < ncopy; i++) {
65 csize = size >= 4 ? MIN2(size & align, CIK_SDMA_COPY_MAX_SIZE) : size;
66 radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
67 CIK_SDMA_COPY_SUB_OPCODE_LINEAR,
68 0));
69 radeon_emit(cs, ctx->chip_class >= GFX9 ? csize - 1 : csize);
70 radeon_emit(cs, 0); /* src/dst endian swap */
71 radeon_emit(cs, src_offset);
72 radeon_emit(cs, src_offset >> 32);
73 radeon_emit(cs, dst_offset);
74 radeon_emit(cs, dst_offset >> 32);
75 dst_offset += csize;
76 src_offset += csize;
77 size -= csize;
78 }
79 }
80
81 static unsigned minify_as_blocks(unsigned width, unsigned level, unsigned blk_w)
82 {
83 width = u_minify(width, level);
84 return DIV_ROUND_UP(width, blk_w);
85 }
86
87 static unsigned encode_tile_info(struct si_context *sctx,
88 struct si_texture *tex, unsigned level,
89 bool set_bpp)
90 {
91 struct radeon_info *info = &sctx->screen->info;
92 unsigned tile_index = tex->surface.u.legacy.tiling_index[level];
93 unsigned macro_tile_index = tex->surface.u.legacy.macro_tile_index;
94 unsigned tile_mode = info->si_tile_mode_array[tile_index];
95 unsigned macro_tile_mode = info->cik_macrotile_mode_array[macro_tile_index];
96
97 return (set_bpp ? util_logbase2(tex->surface.bpe) : 0) |
98 (G_009910_ARRAY_MODE(tile_mode) << 3) |
99 (G_009910_MICRO_TILE_MODE_NEW(tile_mode) << 8) |
100 /* Non-depth modes don't have TILE_SPLIT set. */
101 ((util_logbase2(tex->surface.u.legacy.tile_split >> 6)) << 11) |
102 (G_009990_BANK_WIDTH(macro_tile_mode) << 15) |
103 (G_009990_BANK_HEIGHT(macro_tile_mode) << 18) |
104 (G_009990_NUM_BANKS(macro_tile_mode) << 21) |
105 (G_009990_MACRO_TILE_ASPECT(macro_tile_mode) << 24) |
106 (G_009910_PIPE_CONFIG(tile_mode) << 26);
107 }
108
109
110 static bool si_sdma_v4_copy_texture(struct si_context *sctx,
111 struct pipe_resource *dst,
112 unsigned dst_level,
113 unsigned dstx, unsigned dsty, unsigned dstz,
114 struct pipe_resource *src,
115 unsigned src_level,
116 const struct pipe_box *src_box)
117 {
118 struct si_texture *ssrc = (struct si_texture*)src;
119 struct si_texture *sdst = (struct si_texture*)dst;
120
121 unsigned bpp = sdst->surface.bpe;
122 uint64_t dst_address = sdst->buffer.gpu_address +
123 sdst->surface.u.gfx9.surf_offset;
124 uint64_t src_address = ssrc->buffer.gpu_address +
125 ssrc->surface.u.gfx9.surf_offset;
126 unsigned dst_pitch = sdst->surface.u.gfx9.surf_pitch;
127 unsigned src_pitch = ssrc->surface.u.gfx9.surf_pitch;
128 uint64_t dst_slice_pitch = ((uint64_t)sdst->surface.u.gfx9.surf_slice_size) / bpp;
129 uint64_t src_slice_pitch = ((uint64_t)ssrc->surface.u.gfx9.surf_slice_size) / bpp;
130 unsigned srcx = src_box->x / ssrc->surface.blk_w;
131 unsigned srcy = src_box->y / ssrc->surface.blk_h;
132 unsigned srcz = src_box->z;
133 unsigned copy_width = DIV_ROUND_UP(src_box->width, ssrc->surface.blk_w);
134 unsigned copy_height = DIV_ROUND_UP(src_box->height, ssrc->surface.blk_h);
135 unsigned copy_depth = src_box->depth;
136 unsigned xalign = MAX2(1, 4 / bpp);
137
138 assert(src_level <= src->last_level);
139 assert(dst_level <= dst->last_level);
140 assert(sdst->surface.u.gfx9.surf_offset +
141 dst_slice_pitch * bpp * (dstz + src_box->depth) <=
142 sdst->buffer.buf->size);
143 assert(ssrc->surface.u.gfx9.surf_offset +
144 src_slice_pitch * bpp * (srcz + src_box->depth) <=
145 ssrc->buffer.buf->size);
146
147 if (!si_prepare_for_dma_blit(sctx, sdst, dst_level, dstx, dsty,
148 dstz, ssrc, src_level, src_box))
149 return false;
150
151 dstx /= sdst->surface.blk_w;
152 dsty /= sdst->surface.blk_h;
153
154 if (srcx >= (1 << 14) ||
155 srcy >= (1 << 14) ||
156 srcz >= (1 << 11) ||
157 dstx >= (1 << 14) ||
158 dsty >= (1 << 14) ||
159 dstz >= (1 << 11))
160 return false;
161
162 /* Linear -> linear sub-window copy. */
163 if (ssrc->surface.is_linear &&
164 sdst->surface.is_linear) {
165 struct radeon_cmdbuf *cs = sctx->sdma_cs;
166
167 /* Check if everything fits into the bitfields */
168 if (!(src_pitch <= (1 << 19) &&
169 dst_pitch <= (1 << 19) &&
170 src_slice_pitch <= (1 << 28) &&
171 dst_slice_pitch <= (1 << 28) &&
172 copy_width <= (1 << 14) &&
173 copy_height <= (1 << 14) &&
174 copy_depth <= (1 << 11)))
175 return false;
176
177 si_need_dma_space(sctx, 13, &sdst->buffer, &ssrc->buffer);
178
179 src_address += ssrc->surface.u.gfx9.offset[src_level];
180 dst_address += sdst->surface.u.gfx9.offset[dst_level];
181
182 /* Check alignments */
183 if ((src_address % 4) != 0 ||
184 (dst_address % 4) != 0 ||
185 (src_pitch % xalign) != 0)
186 return false;
187
188 radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
189 CIK_SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW, 0) |
190 (util_logbase2(bpp) << 29));
191 radeon_emit(cs, src_address);
192 radeon_emit(cs, src_address >> 32);
193 radeon_emit(cs, srcx | (srcy << 16));
194 radeon_emit(cs, srcz | ((src_pitch - 1) << 13));
195 radeon_emit(cs, src_slice_pitch - 1);
196 radeon_emit(cs, dst_address);
197 radeon_emit(cs, dst_address >> 32);
198 radeon_emit(cs, dstx | (dsty << 16));
199 radeon_emit(cs, dstz | ((dst_pitch - 1) << 13));
200 radeon_emit(cs, dst_slice_pitch - 1);
201 radeon_emit(cs, (copy_width - 1) | ((copy_height - 1) << 16));
202 radeon_emit(cs, (copy_depth - 1));
203 return true;
204 }
205
206 /* Linear <-> Tiled sub-window copy */
207 if (ssrc->surface.is_linear != sdst->surface.is_linear) {
208 struct si_texture *tiled = ssrc->surface.is_linear ? sdst : ssrc;
209 struct si_texture *linear = tiled == ssrc ? sdst : ssrc;
210 unsigned tiled_level = tiled == ssrc ? src_level : dst_level;
211 unsigned linear_level = linear == ssrc ? src_level : dst_level;
212 unsigned tiled_x = tiled == ssrc ? srcx : dstx;
213 unsigned linear_x = linear == ssrc ? srcx : dstx;
214 unsigned tiled_y = tiled == ssrc ? srcy : dsty;
215 unsigned linear_y = linear == ssrc ? srcy : dsty;
216 unsigned tiled_z = tiled == ssrc ? srcz : dstz;
217 unsigned linear_z = linear == ssrc ? srcz : dstz;
218 unsigned tiled_width = tiled == ssrc ?
219 DIV_ROUND_UP(ssrc->buffer.b.b.width0, ssrc->surface.blk_w) :
220 DIV_ROUND_UP(sdst->buffer.b.b.width0, sdst->surface.blk_w);
221 unsigned tiled_height = tiled == ssrc ?
222 DIV_ROUND_UP(ssrc->buffer.b.b.height0, ssrc->surface.blk_h) :
223 DIV_ROUND_UP(sdst->buffer.b.b.height0, sdst->surface.blk_h);
224 unsigned tiled_depth = tiled == ssrc ?
225 ssrc->buffer.b.b.depth0 :
226 sdst->buffer.b.b.depth0;
227 unsigned linear_pitch = linear == ssrc ? src_pitch : dst_pitch;
228 unsigned linear_slice_pitch = linear == ssrc ? src_slice_pitch : dst_slice_pitch;
229 uint64_t tiled_address = tiled == ssrc ? src_address : dst_address;
230 uint64_t linear_address = linear == ssrc ? src_address : dst_address;
231 struct radeon_cmdbuf *cs = sctx->sdma_cs;
232
233 linear_address += linear->surface.u.gfx9.offset[linear_level];
234
235 /* Check if everything fits into the bitfields */
236 if (!(tiled_x <= (1 << 14) &&
237 tiled_y <= (1 << 14) &&
238 tiled_z <= (1 << 11) &&
239 tiled_width <= (1 << 14) &&
240 tiled_height <= (1 << 14) &&
241 tiled_depth <= (1 << 11) &&
242 tiled->surface.u.gfx9.surf.epitch <= (1 << 16) &&
243 linear_x <= (1 << 14) &&
244 linear_y <= (1 << 14) &&
245 linear_z <= (1 << 11) &&
246 linear_pitch <= (1 << 14) &&
247 linear_slice_pitch <= (1 << 28) &&
248 copy_width <= (1 << 14) &&
249 copy_height <= (1 << 14) &&
250 copy_depth <= (1 << 11)))
251 return false;
252
253 /* Check alignments */
254 if ((tiled_address % 256 != 0) ||
255 (linear_address % 4 != 0) ||
256 (linear_pitch % xalign != 0) ||
257 (linear_slice_pitch % xalign != 0))
258 return false;
259
260 si_need_dma_space(sctx, 14, &sdst->buffer, &ssrc->buffer);
261
262 radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
263 CIK_SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW, 0) |
264 tiled->buffer.b.b.last_level << 20 |
265 tiled_level << 24 |
266 (linear == sdst ? 1u : 0) << 31);
267 radeon_emit(cs, (uint32_t) tiled_address);
268 radeon_emit(cs, (uint32_t) (tiled_address >> 32));
269 radeon_emit(cs, tiled_x | (tiled_y << 16));
270 radeon_emit(cs, tiled_z | ((tiled_width - 1) << 16));
271 radeon_emit(cs, (tiled_height - 1) | (tiled_depth - 1) << 16);
272 radeon_emit(cs, util_logbase2(bpp) |
273 tiled->surface.u.gfx9.surf.swizzle_mode << 3 |
274 tiled->surface.u.gfx9.resource_type << 9 |
275 tiled->surface.u.gfx9.surf.epitch << 16);
276 radeon_emit(cs, (uint32_t) linear_address);
277 radeon_emit(cs, (uint32_t) (linear_address >> 32));
278 radeon_emit(cs, linear_x | (linear_y << 16));
279 radeon_emit(cs, linear_z | ((linear_pitch - 1) << 16));
280 radeon_emit(cs, linear_slice_pitch - 1);
281 radeon_emit(cs, (copy_width - 1) | ((copy_height - 1) << 16));
282 radeon_emit(cs, (copy_depth - 1));
283 return true;
284 }
285
286 return false;
287 }
288
289 static bool cik_sdma_copy_texture(struct si_context *sctx,
290 struct pipe_resource *dst,
291 unsigned dst_level,
292 unsigned dstx, unsigned dsty, unsigned dstz,
293 struct pipe_resource *src,
294 unsigned src_level,
295 const struct pipe_box *src_box)
296 {
297 struct radeon_info *info = &sctx->screen->info;
298 struct si_texture *ssrc = (struct si_texture*)src;
299 struct si_texture *sdst = (struct si_texture*)dst;
300 unsigned bpp = sdst->surface.bpe;
301 uint64_t dst_address = sdst->buffer.gpu_address +
302 sdst->surface.u.legacy.level[dst_level].offset;
303 uint64_t src_address = ssrc->buffer.gpu_address +
304 ssrc->surface.u.legacy.level[src_level].offset;
305 unsigned dst_mode = sdst->surface.u.legacy.level[dst_level].mode;
306 unsigned src_mode = ssrc->surface.u.legacy.level[src_level].mode;
307 unsigned dst_tile_index = sdst->surface.u.legacy.tiling_index[dst_level];
308 unsigned src_tile_index = ssrc->surface.u.legacy.tiling_index[src_level];
309 unsigned dst_tile_mode = info->si_tile_mode_array[dst_tile_index];
310 unsigned src_tile_mode = info->si_tile_mode_array[src_tile_index];
311 unsigned dst_micro_mode = G_009910_MICRO_TILE_MODE_NEW(dst_tile_mode);
312 unsigned src_micro_mode = G_009910_MICRO_TILE_MODE_NEW(src_tile_mode);
313 unsigned dst_tile_swizzle = dst_mode == RADEON_SURF_MODE_2D ?
314 sdst->surface.tile_swizzle : 0;
315 unsigned src_tile_swizzle = src_mode == RADEON_SURF_MODE_2D ?
316 ssrc->surface.tile_swizzle : 0;
317 unsigned dst_pitch = sdst->surface.u.legacy.level[dst_level].nblk_x;
318 unsigned src_pitch = ssrc->surface.u.legacy.level[src_level].nblk_x;
319 uint64_t dst_slice_pitch = ((uint64_t)sdst->surface.u.legacy.level[dst_level].slice_size_dw * 4) / bpp;
320 uint64_t src_slice_pitch = ((uint64_t)ssrc->surface.u.legacy.level[src_level].slice_size_dw * 4) / bpp;
321 unsigned dst_width = minify_as_blocks(sdst->buffer.b.b.width0,
322 dst_level, sdst->surface.blk_w);
323 unsigned src_width = minify_as_blocks(ssrc->buffer.b.b.width0,
324 src_level, ssrc->surface.blk_w);
325 unsigned dst_height = minify_as_blocks(sdst->buffer.b.b.height0,
326 dst_level, sdst->surface.blk_h);
327 unsigned src_height = minify_as_blocks(ssrc->buffer.b.b.height0,
328 src_level, ssrc->surface.blk_h);
329 unsigned srcx = src_box->x / ssrc->surface.blk_w;
330 unsigned srcy = src_box->y / ssrc->surface.blk_h;
331 unsigned srcz = src_box->z;
332 unsigned copy_width = DIV_ROUND_UP(src_box->width, ssrc->surface.blk_w);
333 unsigned copy_height = DIV_ROUND_UP(src_box->height, ssrc->surface.blk_h);
334 unsigned copy_depth = src_box->depth;
335
336 assert(src_level <= src->last_level);
337 assert(dst_level <= dst->last_level);
338 assert(sdst->surface.u.legacy.level[dst_level].offset +
339 dst_slice_pitch * bpp * (dstz + src_box->depth) <=
340 sdst->buffer.buf->size);
341 assert(ssrc->surface.u.legacy.level[src_level].offset +
342 src_slice_pitch * bpp * (srcz + src_box->depth) <=
343 ssrc->buffer.buf->size);
344
345 if (!si_prepare_for_dma_blit(sctx, sdst, dst_level, dstx, dsty,
346 dstz, ssrc, src_level, src_box))
347 return false;
348
349 dstx /= sdst->surface.blk_w;
350 dsty /= sdst->surface.blk_h;
351
352 if (srcx >= (1 << 14) ||
353 srcy >= (1 << 14) ||
354 srcz >= (1 << 11) ||
355 dstx >= (1 << 14) ||
356 dsty >= (1 << 14) ||
357 dstz >= (1 << 11))
358 return false;
359
360 dst_address |= dst_tile_swizzle << 8;
361 src_address |= src_tile_swizzle << 8;
362
363 /* Linear -> linear sub-window copy. */
364 if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED &&
365 src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED &&
366 /* check if everything fits into the bitfields */
367 src_pitch <= (1 << 14) &&
368 dst_pitch <= (1 << 14) &&
369 src_slice_pitch <= (1 << 28) &&
370 dst_slice_pitch <= (1 << 28) &&
371 copy_width <= (1 << 14) &&
372 copy_height <= (1 << 14) &&
373 copy_depth <= (1 << 11) &&
374 /* HW limitation - GFX7: */
375 (sctx->chip_class != GFX7 ||
376 (copy_width < (1 << 14) &&
377 copy_height < (1 << 14) &&
378 copy_depth < (1 << 11))) &&
379 /* HW limitation - some GFX7 parts: */
380 ((sctx->family != CHIP_BONAIRE &&
381 sctx->family != CHIP_KAVERI) ||
382 (srcx + copy_width != (1 << 14) &&
383 srcy + copy_height != (1 << 14)))) {
384 struct radeon_cmdbuf *cs = sctx->sdma_cs;
385
386 si_need_dma_space(sctx, 13, &sdst->buffer, &ssrc->buffer);
387
388 radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
389 CIK_SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW, 0) |
390 (util_logbase2(bpp) << 29));
391 radeon_emit(cs, src_address);
392 radeon_emit(cs, src_address >> 32);
393 radeon_emit(cs, srcx | (srcy << 16));
394 radeon_emit(cs, srcz | ((src_pitch - 1) << 16));
395 radeon_emit(cs, src_slice_pitch - 1);
396 radeon_emit(cs, dst_address);
397 radeon_emit(cs, dst_address >> 32);
398 radeon_emit(cs, dstx | (dsty << 16));
399 radeon_emit(cs, dstz | ((dst_pitch - 1) << 16));
400 radeon_emit(cs, dst_slice_pitch - 1);
401 if (sctx->chip_class == GFX7) {
402 radeon_emit(cs, copy_width | (copy_height << 16));
403 radeon_emit(cs, copy_depth);
404 } else {
405 radeon_emit(cs, (copy_width - 1) | ((copy_height - 1) << 16));
406 radeon_emit(cs, (copy_depth - 1));
407 }
408 return true;
409 }
410
411 /* Tiled <-> linear sub-window copy. */
412 if ((src_mode >= RADEON_SURF_MODE_1D) != (dst_mode >= RADEON_SURF_MODE_1D)) {
413 struct si_texture *tiled = src_mode >= RADEON_SURF_MODE_1D ? ssrc : sdst;
414 struct si_texture *linear = tiled == ssrc ? sdst : ssrc;
415 unsigned tiled_level = tiled == ssrc ? src_level : dst_level;
416 unsigned linear_level = linear == ssrc ? src_level : dst_level;
417 unsigned tiled_x = tiled == ssrc ? srcx : dstx;
418 unsigned linear_x = linear == ssrc ? srcx : dstx;
419 unsigned tiled_y = tiled == ssrc ? srcy : dsty;
420 unsigned linear_y = linear == ssrc ? srcy : dsty;
421 unsigned tiled_z = tiled == ssrc ? srcz : dstz;
422 unsigned linear_z = linear == ssrc ? srcz : dstz;
423 unsigned tiled_width = tiled == ssrc ? src_width : dst_width;
424 unsigned linear_width = linear == ssrc ? src_width : dst_width;
425 unsigned tiled_pitch = tiled == ssrc ? src_pitch : dst_pitch;
426 unsigned linear_pitch = linear == ssrc ? src_pitch : dst_pitch;
427 unsigned tiled_slice_pitch = tiled == ssrc ? src_slice_pitch : dst_slice_pitch;
428 unsigned linear_slice_pitch = linear == ssrc ? src_slice_pitch : dst_slice_pitch;
429 uint64_t tiled_address = tiled == ssrc ? src_address : dst_address;
430 uint64_t linear_address = linear == ssrc ? src_address : dst_address;
431 unsigned tiled_micro_mode = tiled == ssrc ? src_micro_mode : dst_micro_mode;
432
433 assert(tiled_pitch % 8 == 0);
434 assert(tiled_slice_pitch % 64 == 0);
435 unsigned pitch_tile_max = tiled_pitch / 8 - 1;
436 unsigned slice_tile_max = tiled_slice_pitch / 64 - 1;
437 unsigned xalign = MAX2(1, 4 / bpp);
438 unsigned copy_width_aligned = copy_width;
439
440 /* If the region ends at the last pixel and is unaligned, we
441 * can copy the remainder of the line that is not visible to
442 * make it aligned.
443 */
444 if (copy_width % xalign != 0 &&
445 linear_x + copy_width == linear_width &&
446 tiled_x + copy_width == tiled_width &&
447 linear_x + align(copy_width, xalign) <= linear_pitch &&
448 tiled_x + align(copy_width, xalign) <= tiled_pitch)
449 copy_width_aligned = align(copy_width, xalign);
450
451 /* HW limitations. */
452 if ((sctx->family == CHIP_BONAIRE ||
453 sctx->family == CHIP_KAVERI) &&
454 linear_pitch - 1 == 0x3fff &&
455 bpp == 16)
456 return false;
457
458 if (sctx->chip_class == GFX7 &&
459 (copy_width_aligned == (1 << 14) ||
460 copy_height == (1 << 14) ||
461 copy_depth == (1 << 11)))
462 return false;
463
464 if ((sctx->family == CHIP_BONAIRE ||
465 sctx->family == CHIP_KAVERI ||
466 sctx->family == CHIP_KABINI) &&
467 (tiled_x + copy_width == (1 << 14) ||
468 tiled_y + copy_height == (1 << 14)))
469 return false;
470
471 /* The hw can read outside of the given linear buffer bounds,
472 * or access those pages but not touch the memory in case
473 * of writes. (it still causes a VM fault)
474 *
475 * Out-of-bounds memory access or page directory access must
476 * be prevented.
477 */
478 int64_t start_linear_address, end_linear_address;
479 unsigned granularity;
480
481 /* Deduce the size of reads from the linear surface. */
482 switch (tiled_micro_mode) {
483 case V_009910_ADDR_SURF_DISPLAY_MICRO_TILING:
484 granularity = bpp == 1 ? 64 / (8*bpp) :
485 128 / (8*bpp);
486 break;
487 case V_009910_ADDR_SURF_THIN_MICRO_TILING:
488 case V_009910_ADDR_SURF_DEPTH_MICRO_TILING:
489 if (0 /* TODO: THICK microtiling */)
490 granularity = bpp == 1 ? 32 / (8*bpp) :
491 bpp == 2 ? 64 / (8*bpp) :
492 bpp <= 8 ? 128 / (8*bpp) :
493 256 / (8*bpp);
494 else
495 granularity = bpp <= 2 ? 64 / (8*bpp) :
496 bpp <= 8 ? 128 / (8*bpp) :
497 256 / (8*bpp);
498 break;
499 default:
500 return false;
501 }
502
503 /* The linear reads start at tiled_x & ~(granularity - 1).
504 * If linear_x == 0 && tiled_x % granularity != 0, the hw
505 * starts reading from an address preceding linear_address!!!
506 */
507 start_linear_address =
508 linear->surface.u.legacy.level[linear_level].offset +
509 bpp * (linear_z * linear_slice_pitch +
510 linear_y * linear_pitch +
511 linear_x);
512 start_linear_address -= (int)(bpp * (tiled_x % granularity));
513
514 end_linear_address =
515 linear->surface.u.legacy.level[linear_level].offset +
516 bpp * ((linear_z + copy_depth - 1) * linear_slice_pitch +
517 (linear_y + copy_height - 1) * linear_pitch +
518 (linear_x + copy_width));
519
520 if ((tiled_x + copy_width) % granularity)
521 end_linear_address += granularity -
522 (tiled_x + copy_width) % granularity;
523
524 if (start_linear_address < 0 ||
525 end_linear_address > linear->surface.surf_size)
526 return false;
527
528 /* Check requirements. */
529 if (tiled_address % 256 == 0 &&
530 linear_address % 4 == 0 &&
531 linear_pitch % xalign == 0 &&
532 linear_x % xalign == 0 &&
533 tiled_x % xalign == 0 &&
534 copy_width_aligned % xalign == 0 &&
535 tiled_micro_mode != V_009910_ADDR_SURF_ROTATED_MICRO_TILING &&
536 /* check if everything fits into the bitfields */
537 tiled->surface.u.legacy.tile_split <= 4096 &&
538 pitch_tile_max < (1 << 11) &&
539 slice_tile_max < (1 << 22) &&
540 linear_pitch <= (1 << 14) &&
541 linear_slice_pitch <= (1 << 28) &&
542 copy_width_aligned <= (1 << 14) &&
543 copy_height <= (1 << 14) &&
544 copy_depth <= (1 << 11)) {
545 struct radeon_cmdbuf *cs = sctx->sdma_cs;
546 uint32_t direction = linear == sdst ? 1u << 31 : 0;
547
548 si_need_dma_space(sctx, 14, &sdst->buffer, &ssrc->buffer);
549
550 radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
551 CIK_SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW, 0) |
552 direction);
553 radeon_emit(cs, tiled_address);
554 radeon_emit(cs, tiled_address >> 32);
555 radeon_emit(cs, tiled_x | (tiled_y << 16));
556 radeon_emit(cs, tiled_z | (pitch_tile_max << 16));
557 radeon_emit(cs, slice_tile_max);
558 radeon_emit(cs, encode_tile_info(sctx, tiled, tiled_level, true));
559 radeon_emit(cs, linear_address);
560 radeon_emit(cs, linear_address >> 32);
561 radeon_emit(cs, linear_x | (linear_y << 16));
562 radeon_emit(cs, linear_z | ((linear_pitch - 1) << 16));
563 radeon_emit(cs, linear_slice_pitch - 1);
564 if (sctx->chip_class == GFX7) {
565 radeon_emit(cs, copy_width_aligned | (copy_height << 16));
566 radeon_emit(cs, copy_depth);
567 } else {
568 radeon_emit(cs, (copy_width_aligned - 1) | ((copy_height - 1) << 16));
569 radeon_emit(cs, (copy_depth - 1));
570 }
571 return true;
572 }
573 }
574
575 /* Tiled -> Tiled sub-window copy. */
576 if (dst_mode >= RADEON_SURF_MODE_1D &&
577 src_mode >= RADEON_SURF_MODE_1D &&
578 /* check if these fit into the bitfields */
579 src_address % 256 == 0 &&
580 dst_address % 256 == 0 &&
581 ssrc->surface.u.legacy.tile_split <= 4096 &&
582 sdst->surface.u.legacy.tile_split <= 4096 &&
583 dstx % 8 == 0 &&
584 dsty % 8 == 0 &&
585 srcx % 8 == 0 &&
586 srcy % 8 == 0 &&
587 /* this can either be equal, or display->rotated (GFX8+ only) */
588 (src_micro_mode == dst_micro_mode ||
589 (sctx->chip_class >= GFX8 &&
590 src_micro_mode == V_009910_ADDR_SURF_DISPLAY_MICRO_TILING &&
591 dst_micro_mode == V_009910_ADDR_SURF_ROTATED_MICRO_TILING))) {
592 assert(src_pitch % 8 == 0);
593 assert(dst_pitch % 8 == 0);
594 assert(src_slice_pitch % 64 == 0);
595 assert(dst_slice_pitch % 64 == 0);
596 unsigned src_pitch_tile_max = src_pitch / 8 - 1;
597 unsigned dst_pitch_tile_max = dst_pitch / 8 - 1;
598 unsigned src_slice_tile_max = src_slice_pitch / 64 - 1;
599 unsigned dst_slice_tile_max = dst_slice_pitch / 64 - 1;
600 unsigned copy_width_aligned = copy_width;
601 unsigned copy_height_aligned = copy_height;
602
603 /* If the region ends at the last pixel and is unaligned, we
604 * can copy the remainder of the tile that is not visible to
605 * make it aligned.
606 */
607 if (copy_width % 8 != 0 &&
608 srcx + copy_width == src_width &&
609 dstx + copy_width == dst_width)
610 copy_width_aligned = align(copy_width, 8);
611
612 if (copy_height % 8 != 0 &&
613 srcy + copy_height == src_height &&
614 dsty + copy_height == dst_height)
615 copy_height_aligned = align(copy_height, 8);
616
617 /* check if these fit into the bitfields */
618 if (src_pitch_tile_max < (1 << 11) &&
619 dst_pitch_tile_max < (1 << 11) &&
620 src_slice_tile_max < (1 << 22) &&
621 dst_slice_tile_max < (1 << 22) &&
622 copy_width_aligned <= (1 << 14) &&
623 copy_height_aligned <= (1 << 14) &&
624 copy_depth <= (1 << 11) &&
625 copy_width_aligned % 8 == 0 &&
626 copy_height_aligned % 8 == 0 &&
627 /* HW limitation - GFX7: */
628 (sctx->chip_class != GFX7 ||
629 (copy_width_aligned < (1 << 14) &&
630 copy_height_aligned < (1 << 14) &&
631 copy_depth < (1 << 11))) &&
632 /* HW limitation - some GFX7 parts: */
633 ((sctx->family != CHIP_BONAIRE &&
634 sctx->family != CHIP_KAVERI &&
635 sctx->family != CHIP_KABINI) ||
636 (srcx + copy_width_aligned != (1 << 14) &&
637 srcy + copy_height_aligned != (1 << 14) &&
638 dstx + copy_width != (1 << 14)))) {
639 struct radeon_cmdbuf *cs = sctx->sdma_cs;
640
641 si_need_dma_space(sctx, 15, &sdst->buffer, &ssrc->buffer);
642
643 radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
644 CIK_SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW, 0));
645 radeon_emit(cs, src_address);
646 radeon_emit(cs, src_address >> 32);
647 radeon_emit(cs, srcx | (srcy << 16));
648 radeon_emit(cs, srcz | (src_pitch_tile_max << 16));
649 radeon_emit(cs, src_slice_tile_max);
650 radeon_emit(cs, encode_tile_info(sctx, ssrc, src_level, true));
651 radeon_emit(cs, dst_address);
652 radeon_emit(cs, dst_address >> 32);
653 radeon_emit(cs, dstx | (dsty << 16));
654 radeon_emit(cs, dstz | (dst_pitch_tile_max << 16));
655 radeon_emit(cs, dst_slice_tile_max);
656 radeon_emit(cs, encode_tile_info(sctx, sdst, dst_level, false));
657 if (sctx->chip_class == GFX7) {
658 radeon_emit(cs, copy_width_aligned |
659 (copy_height_aligned << 16));
660 radeon_emit(cs, copy_depth);
661 } else {
662 radeon_emit(cs, (copy_width_aligned - 8) |
663 ((copy_height_aligned - 8) << 16));
664 radeon_emit(cs, (copy_depth - 1));
665 }
666 return true;
667 }
668 }
669
670 return false;
671 }
672
673 static void cik_sdma_copy(struct pipe_context *ctx,
674 struct pipe_resource *dst,
675 unsigned dst_level,
676 unsigned dstx, unsigned dsty, unsigned dstz,
677 struct pipe_resource *src,
678 unsigned src_level,
679 const struct pipe_box *src_box)
680 {
681 struct si_context *sctx = (struct si_context *)ctx;
682
683 if (!sctx->sdma_cs ||
684 src->flags & PIPE_RESOURCE_FLAG_SPARSE ||
685 dst->flags & PIPE_RESOURCE_FLAG_SPARSE)
686 goto fallback;
687
688 /* If src is a buffer and dst is a texture, we are uploading metadata. */
689 if (src->target == PIPE_BUFFER) {
690 cik_sdma_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width);
691 return;
692 }
693
694 /* SDMA causes corruption. See:
695 * https://bugs.freedesktop.org/show_bug.cgi?id=110575
696 * https://bugs.freedesktop.org/show_bug.cgi?id=110635
697 *
698 * Keep SDMA enabled on APUs.
699 */
700 if (sctx->screen->debug_flags & DBG(FORCE_SDMA) ||
701 (!sctx->screen->info.has_dedicated_vram &&
702 !(sctx->screen->debug_flags & DBG(NO_SDMA_COPY_IMAGE)))) {
703 if ((sctx->chip_class == GFX7 || sctx->chip_class == GFX8) &&
704 cik_sdma_copy_texture(sctx, dst, dst_level, dstx, dsty, dstz,
705 src, src_level, src_box))
706 return;
707 else if (sctx->chip_class == GFX9 &&
708 si_sdma_v4_copy_texture(sctx, dst, dst_level, dstx, dsty, dstz,
709 src, src_level, src_box))
710 return;
711 }
712
713 fallback:
714 si_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
715 src, src_level, src_box);
716 }
717
718 void cik_init_sdma_functions(struct si_context *sctx)
719 {
720 sctx->dma_copy = cik_sdma_copy;
721 }