src/gallium/drivers/radeonsi/evergreen_hw_context.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #include "r600.h"
  27 #include "r600_hw_context_priv.h"
  28 #include "radeonsi_pipe.h"
  29 #include "sid.h"
  30 #include "util/u_memory.h"
  31 #include <errno.h>
  32
  33 int si_context_init(struct r600_context *ctx)
  34 {
  35         int r;
  36
  37         LIST_INITHEAD(&ctx->active_query_list);
  38
  39         ctx->cs = ctx->ws->cs_create(ctx->ws);
  40
  41         r600_init_cs(ctx);
  42         ctx->max_db = 8;
  43         return 0;
  44 }
  45
  46 static inline void evergreen_context_ps_partial_flush(struct r600_context *ctx)
  47 {
  48         struct radeon_winsys_cs *cs = ctx->cs;
  49
  50         if (!(ctx->flags & R600_CONTEXT_DRAW_PENDING))
  51                 return;
  52
  53         cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
  54         cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
  55
  56         ctx->flags &= ~R600_CONTEXT_DRAW_PENDING;
  57 }
  58
  59 void si_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
  60 {
  61         struct radeon_winsys_cs *cs = ctx->cs;
  62         unsigned ndwords = 7;
  63         uint32_t *pm4;
  64         uint64_t va;
  65
  66         if (draw->indices) {
  67                 ndwords = 12;
  68         }
  69         if (ctx->num_cs_dw_queries_suspend)
  70                 ndwords += 6;
  71
  72         /* when increasing ndwords, bump the max limit too */
  73         assert(ndwords <= SI_MAX_DRAW_CS_DWORDS);
  74
  75         /* queries need some special values
  76          * (this is non-zero if any query is active) */
  77         if (ctx->num_cs_dw_queries_suspend) {
  78                 pm4 = &cs->buf[cs->cdw];
  79                 pm4[0] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
  80                 pm4[1] = (R_028004_DB_COUNT_CONTROL - SI_CONTEXT_REG_OFFSET) >> 2;
  81                 pm4[2] = S_028004_PERFECT_ZPASS_COUNTS(1);
  82                 pm4[3] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
  83                 pm4[4] = (R_02800C_DB_RENDER_OVERRIDE - SI_CONTEXT_REG_OFFSET) >> 2;
  84                 pm4[5] = draw->db_render_override | S_02800C_NOOP_CULL_DISABLE(1);
  85                 cs->cdw += 6;
  86                 ndwords -= 6;
  87         }
  88
  89         /* draw packet */
  90         pm4 = &cs->buf[cs->cdw];
  91         pm4[0] = PKT3(PKT3_INDEX_TYPE, 0, ctx->predicate_drawing);
  92         pm4[1] = draw->vgt_index_type;
  93         pm4[2] = PKT3(PKT3_NUM_INSTANCES, 0, ctx->predicate_drawing);
  94         pm4[3] = draw->vgt_num_instances;
  95         if (draw->indices) {
  96                 va = r600_resource_va(&ctx->screen->screen, (void*)draw->indices);
  97                 va += draw->indices_bo_offset;
  98                 pm4[4] = PKT3(PKT3_DRAW_INDEX_2, 4, ctx->predicate_drawing);
  99                 pm4[5] = (draw->indices->b.b.width0 - draw->indices_bo_offset) /
 100                         ctx->index_buffer.index_size;
 101                 pm4[6] = va;
 102                 pm4[7] = (va >> 32UL) & 0xFF;
 103                 pm4[8] = draw->vgt_num_indices;
 104                 pm4[9] = draw->vgt_draw_initiator;
 105                 pm4[10] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing);
 106                 pm4[11] = r600_context_bo_reloc(ctx, draw->indices, RADEON_USAGE_READ);
 107         } else {
 108                 pm4[4] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, ctx->predicate_drawing);
 109                 pm4[5] = draw->vgt_num_indices;
 110                 pm4[6] = draw->vgt_draw_initiator;
 111         }
 112         cs->cdw += ndwords;
 113 }
 114
 115 void evergreen_flush_vgt_streamout(struct r600_context *ctx)
 116 {
 117         struct radeon_winsys_cs *cs = ctx->cs;
 118
 119         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, 1, 0);
 120         cs->buf[cs->cdw++] = (R_0084FC_CP_STRMOUT_CNTL - SI_CONFIG_REG_OFFSET) >> 2;
 121         cs->buf[cs->cdw++] = 0;
 122
 123         cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
 124         cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0);
 125
 126         cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0);
 127         cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */
 128         cs->buf[cs->cdw++] = R_0084FC_CP_STRMOUT_CNTL >> 2;  /* register */
 129         cs->buf[cs->cdw++] = 0;
 130         cs->buf[cs->cdw++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* reference value */
 131         cs->buf[cs->cdw++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* mask */
 132         cs->buf[cs->cdw++] = 4; /* poll interval */
 133 }
 134
 135 void evergreen_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit)
 136 {
 137         struct radeon_winsys_cs *cs = ctx->cs;
 138
 139         if (buffer_enable_bit) {
 140                 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
 141                 cs->buf[cs->cdw++] = (R_028B94_VGT_STRMOUT_CONFIG - SI_CONTEXT_REG_OFFSET) >> 2;
 142                 cs->buf[cs->cdw++] = S_028B94_STREAMOUT_0_EN(1);
 143
 144                 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
 145                 cs->buf[cs->cdw++] = (R_028B98_VGT_STRMOUT_BUFFER_CONFIG - SI_CONTEXT_REG_OFFSET) >> 2;
 146                 cs->buf[cs->cdw++] = S_028B98_STREAM_0_BUFFER_EN(buffer_enable_bit);
 147         } else {
 148                 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
 149                 cs->buf[cs->cdw++] = (R_028B94_VGT_STRMOUT_CONFIG - SI_CONTEXT_REG_OFFSET) >> 2;
 150                 cs->buf[cs->cdw++] = S_028B94_STREAMOUT_0_EN(0);
 151         }
 152 }