src/gallium/drivers/radeonsi/evergreen_hw_context.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #include "r600.h"
  27 #include "r600_hw_context_priv.h"
  28 #include "radeonsi_pipe.h"
  29 #include "sid.h"
  30 #include "util/u_memory.h"
  31 #include <errno.h>
  32
  33 #define GROUP_FORCE_NEW_BLOCK   0
  34
  35 static const struct r600_reg si_config_reg_list[] = {
  36         {R_0088B0_VGT_VTX_VECT_EJECT_REG, REG_FLAG_FLUSH_CHANGE},
  37         {R_0088C8_VGT_ESGS_RING_SIZE, REG_FLAG_FLUSH_CHANGE},
  38         {R_0088CC_VGT_GSVS_RING_SIZE, REG_FLAG_FLUSH_CHANGE},
  39         {R_008958_VGT_PRIMITIVE_TYPE, 0},
  40         {R_008A14_PA_CL_ENHANCE, REG_FLAG_FLUSH_CHANGE},
  41         {R_009100_SPI_CONFIG_CNTL, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE},
  42         {R_00913C_SPI_CONFIG_CNTL_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE},
  43 };
  44
  45 static const struct r600_reg si_context_reg_list[] = {
  46         {R_028000_DB_RENDER_CONTROL, 0},
  47         {R_028004_DB_COUNT_CONTROL, 0},
  48         {R_028008_DB_DEPTH_VIEW, 0},
  49         {R_02800C_DB_RENDER_OVERRIDE, 0},
  50         {R_028010_DB_RENDER_OVERRIDE2, 0},
  51         {GROUP_FORCE_NEW_BLOCK, 0},
  52         {R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO},
  53         {GROUP_FORCE_NEW_BLOCK, 0},
  54         {R_028020_DB_DEPTH_BOUNDS_MIN, 0},
  55         {R_028024_DB_DEPTH_BOUNDS_MAX, 0},
  56         {R_028028_DB_STENCIL_CLEAR, 0},
  57         {R_02802C_DB_DEPTH_CLEAR, 0},
  58         {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0},
  59         {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0},
  60         {GROUP_FORCE_NEW_BLOCK, 0},
  61         {R_02803C_DB_DEPTH_INFO, 0},
  62         {GROUP_FORCE_NEW_BLOCK, 0},
  63         {R_028040_DB_Z_INFO, 0},
  64         {GROUP_FORCE_NEW_BLOCK, 0},
  65         {R_028044_DB_STENCIL_INFO, 0},
  66         {GROUP_FORCE_NEW_BLOCK, 0},
  67         {R_028048_DB_Z_READ_BASE, REG_FLAG_NEED_BO},
  68         {GROUP_FORCE_NEW_BLOCK, 0},
  69         {R_02804C_DB_STENCIL_READ_BASE, REG_FLAG_NEED_BO},
  70         {GROUP_FORCE_NEW_BLOCK, 0},
  71         {R_028050_DB_Z_WRITE_BASE, REG_FLAG_NEED_BO},
  72         {GROUP_FORCE_NEW_BLOCK, 0},
  73         {R_028054_DB_STENCIL_WRITE_BASE, REG_FLAG_NEED_BO},
  74         {GROUP_FORCE_NEW_BLOCK, 0},
  75         {R_028058_DB_DEPTH_SIZE, 0},
  76         {R_02805C_DB_DEPTH_SLICE, 0},
  77         {GROUP_FORCE_NEW_BLOCK, 0},
  78         {R_028080_TA_BC_BASE_ADDR, REG_FLAG_NEED_BO},
  79         {GROUP_FORCE_NEW_BLOCK, 0},
  80         {R_028200_PA_SC_WINDOW_OFFSET, 0},
  81         {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0},
  82         {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0},
  83         {R_02820C_PA_SC_CLIPRECT_RULE, 0},
  84         {R_028230_PA_SC_EDGERULE, 0},
  85         {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0},
  86         {R_028238_CB_TARGET_MASK, 0},
  87         {R_02823C_CB_SHADER_MASK, 0},
  88         {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0},
  89         {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0},
  90         {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0},
  91         {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0},
  92         {GROUP_FORCE_NEW_BLOCK, 0},
  93         {R_028400_VGT_MAX_VTX_INDX, 0},
  94         {R_028404_VGT_MIN_VTX_INDX, 0},
  95         {R_028408_VGT_INDX_OFFSET, 0},
  96         {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0},
  97         {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0},
  98         {GROUP_FORCE_NEW_BLOCK, 0},
  99         {R_028430_DB_STENCILREFMASK, 0},
 100         {R_028434_DB_STENCILREFMASK_BF, 0},
 101         {R_028644_SPI_PS_INPUT_CNTL_0, 0},
 102         {R_028648_SPI_PS_INPUT_CNTL_1, 0},
 103         {R_02864C_SPI_PS_INPUT_CNTL_2, 0},
 104         {R_028650_SPI_PS_INPUT_CNTL_3, 0},
 105         {R_028654_SPI_PS_INPUT_CNTL_4, 0},
 106         {R_028658_SPI_PS_INPUT_CNTL_5, 0},
 107         {R_02865C_SPI_PS_INPUT_CNTL_6, 0},
 108         {R_028660_SPI_PS_INPUT_CNTL_7, 0},
 109         {R_028664_SPI_PS_INPUT_CNTL_8, 0},
 110         {R_028668_SPI_PS_INPUT_CNTL_9, 0},
 111         {R_02866C_SPI_PS_INPUT_CNTL_10, 0},
 112         {R_028670_SPI_PS_INPUT_CNTL_11, 0},
 113         {R_028674_SPI_PS_INPUT_CNTL_12, 0},
 114         {R_028678_SPI_PS_INPUT_CNTL_13, 0},
 115         {R_02867C_SPI_PS_INPUT_CNTL_14, 0},
 116         {R_028680_SPI_PS_INPUT_CNTL_15, 0},
 117         {R_028684_SPI_PS_INPUT_CNTL_16, 0},
 118         {R_028688_SPI_PS_INPUT_CNTL_17, 0},
 119         {R_02868C_SPI_PS_INPUT_CNTL_18, 0},
 120         {R_028690_SPI_PS_INPUT_CNTL_19, 0},
 121         {R_028694_SPI_PS_INPUT_CNTL_20, 0},
 122         {R_028698_SPI_PS_INPUT_CNTL_21, 0},
 123         {R_02869C_SPI_PS_INPUT_CNTL_22, 0},
 124         {R_0286A0_SPI_PS_INPUT_CNTL_23, 0},
 125         {R_0286A4_SPI_PS_INPUT_CNTL_24, 0},
 126         {R_0286A8_SPI_PS_INPUT_CNTL_25, 0},
 127         {R_0286AC_SPI_PS_INPUT_CNTL_26, 0},
 128         {R_0286B0_SPI_PS_INPUT_CNTL_27, 0},
 129         {R_0286B4_SPI_PS_INPUT_CNTL_28, 0},
 130         {R_0286B8_SPI_PS_INPUT_CNTL_29, 0},
 131         {R_0286BC_SPI_PS_INPUT_CNTL_30, 0},
 132         {R_0286C0_SPI_PS_INPUT_CNTL_31, 0},
 133         {R_0286C4_SPI_VS_OUT_CONFIG, 0},
 134         {R_0286CC_SPI_PS_INPUT_ENA, 0},
 135         {R_0286D0_SPI_PS_INPUT_ADDR, 0},
 136         {R_0286D4_SPI_INTERP_CONTROL_0, 0},
 137         {R_0286D8_SPI_PS_IN_CONTROL, 0},
 138         {R_0286E0_SPI_BARYC_CNTL, 0},
 139         {R_02870C_SPI_SHADER_POS_FORMAT, 0},
 140         {R_028710_SPI_SHADER_Z_FORMAT, 0},
 141         {R_028714_SPI_SHADER_COL_FORMAT, 0},
 142         {R_0287D4_PA_CL_POINT_X_RAD, 0},
 143         {R_0287D8_PA_CL_POINT_Y_RAD, 0},
 144         {R_0287DC_PA_CL_POINT_SIZE, 0},
 145         {R_0287E0_PA_CL_POINT_CULL_RAD, 0},
 146         {R_028800_DB_DEPTH_CONTROL, 0},
 147         {R_028804_DB_EQAA, 0},
 148         {R_02880C_DB_SHADER_CONTROL, 0},
 149         {R_028810_PA_CL_CLIP_CNTL, 0},
 150         {R_028814_PA_SU_SC_MODE_CNTL, 0},
 151         {R_02881C_PA_CL_VS_OUT_CNTL, 0},
 152         {R_028820_PA_CL_NANINF_CNTL, 0},
 153         {R_028824_PA_SU_LINE_STIPPLE_CNTL, 0},
 154         {R_028828_PA_SU_LINE_STIPPLE_SCALE, 0},
 155         {R_02882C_PA_SU_PRIM_FILTER_CNTL, 0},
 156         {R_028A00_PA_SU_POINT_SIZE, 0},
 157         {R_028A04_PA_SU_POINT_MINMAX, 0},
 158         {R_028A08_PA_SU_LINE_CNTL, 0},
 159         {R_028A0C_PA_SC_LINE_STIPPLE, 0},
 160         {R_028A10_VGT_OUTPUT_PATH_CNTL, 0},
 161         {R_028A14_VGT_HOS_CNTL, 0},
 162         {R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0},
 163         {R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0},
 164         {R_028A20_VGT_HOS_REUSE_DEPTH, 0},
 165         {R_028A24_VGT_GROUP_PRIM_TYPE, 0},
 166         {R_028A28_VGT_GROUP_FIRST_DECR, 0},
 167         {R_028A2C_VGT_GROUP_DECR, 0},
 168         {R_028A30_VGT_GROUP_VECT_0_CNTL, 0},
 169         {R_028A34_VGT_GROUP_VECT_1_CNTL, 0},
 170         {R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0},
 171         {R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0},
 172         {R_028A40_VGT_GS_MODE, 0},
 173         {R_028A48_PA_SC_MODE_CNTL_0, 0},
 174         {R_028A4C_PA_SC_MODE_CNTL_1, 0},
 175         {R_028A50_VGT_ENHANCE, 0},
 176         {R_028A54_VGT_GS_PER_ES, 0},
 177         {R_028A58_VGT_ES_PER_GS, 0},
 178         {R_028A5C_VGT_GS_PER_VS, 0},
 179         {R_028A60_VGT_GSVS_RING_OFFSET_1, 0},
 180         {R_028A64_VGT_GSVS_RING_OFFSET_2, 0},
 181         {R_028A68_VGT_GSVS_RING_OFFSET_3, 0},
 182         {R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0},
 183         {R_028A70_IA_ENHANCE, 0},
 184         {R_028A84_VGT_PRIMITIVEID_EN, 0},
 185         {R_028A8C_VGT_PRIMITIVEID_RESET, 0},
 186         {R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0},
 187         {R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0},
 188         {R_028AA8_IA_MULTI_VGT_PARAM, 0},
 189         {R_028AAC_VGT_ESGS_RING_ITEMSIZE, 0},
 190         {R_028AB0_VGT_GSVS_RING_ITEMSIZE, 0},
 191         {R_028AB4_VGT_REUSE_OFF, 0},
 192         {R_028AB8_VGT_VTX_CNT_EN, 0},
 193         {R_028ABC_DB_HTILE_SURFACE, 0},
 194         {R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0},
 195         {R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0},
 196         {R_028AC8_DB_PRELOAD_CONTROL, 0},
 197         {R_028B54_VGT_SHADER_STAGES_EN, 0},
 198         {R_028B70_DB_ALPHA_TO_MASK, 0},
 199         {R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0},
 200         {R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0},
 201         {R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0},
 202         {R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0},
 203         {R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0},
 204         {R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0},
 205         {R_028B94_VGT_STRMOUT_CONFIG, 0},
 206         {R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0},
 207         {R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0},
 208         {R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0},
 209         {R_028BDC_PA_SC_LINE_CNTL, 0},
 210         {R_028BE0_PA_SC_AA_CONFIG, 0},
 211         {R_028BE4_PA_SU_VTX_CNTL, 0},
 212         {R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0},
 213         {R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0},
 214         {R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0},
 215         {R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0},
 216         {R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0},
 217         {R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, 0},
 218         {R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0},
 219         {R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, 0},
 220         {R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0},
 221         {R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, 0},
 222         {R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, 0},
 223         {R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, 0},
 224         {R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0},
 225         {R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, 0},
 226         {R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, 0},
 227         {R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, 0},
 228         {R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0},
 229         {R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, 0},
 230         {R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, 0},
 231         {R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, 0},
 232         {GROUP_FORCE_NEW_BLOCK, 0},
 233         {R_028C60_CB_COLOR0_BASE, REG_FLAG_NEED_BO},
 234         {R_028C64_CB_COLOR0_PITCH, 0},
 235         {R_028C68_CB_COLOR0_SLICE, 0},
 236         {R_028C6C_CB_COLOR0_VIEW, 0},
 237         {R_028C70_CB_COLOR0_INFO, REG_FLAG_NEED_BO},
 238         {R_028C74_CB_COLOR0_ATTRIB, REG_FLAG_NEED_BO},
 239         {GROUP_FORCE_NEW_BLOCK, 0},
 240         {R_028C9C_CB_COLOR1_BASE, REG_FLAG_NEED_BO},
 241         {R_028CA0_CB_COLOR1_PITCH, 0},
 242         {R_028CA4_CB_COLOR1_SLICE, 0},
 243         {R_028CA8_CB_COLOR1_VIEW, 0},
 244         {R_028CAC_CB_COLOR1_INFO, REG_FLAG_NEED_BO},
 245         {R_028CB0_CB_COLOR1_ATTRIB, REG_FLAG_NEED_BO},
 246         {GROUP_FORCE_NEW_BLOCK, 0},
 247         {R_028CD8_CB_COLOR2_BASE, REG_FLAG_NEED_BO},
 248         {R_028CDC_CB_COLOR2_PITCH, 0},
 249         {R_028CE0_CB_COLOR2_SLICE, 0},
 250         {R_028CE4_CB_COLOR2_VIEW, 0},
 251         {R_028CE8_CB_COLOR2_INFO, REG_FLAG_NEED_BO},
 252         {R_028CEC_CB_COLOR2_ATTRIB, REG_FLAG_NEED_BO},
 253         {GROUP_FORCE_NEW_BLOCK, 0},
 254         {R_028D14_CB_COLOR3_BASE, REG_FLAG_NEED_BO},
 255         {R_028D18_CB_COLOR3_PITCH, 0},
 256         {R_028D1C_CB_COLOR3_SLICE, 0},
 257         {R_028D20_CB_COLOR3_VIEW, 0},
 258         {R_028D24_CB_COLOR3_INFO, REG_FLAG_NEED_BO},
 259         {R_028D28_CB_COLOR3_ATTRIB, REG_FLAG_NEED_BO},
 260         {GROUP_FORCE_NEW_BLOCK, 0},
 261         {R_028D50_CB_COLOR4_BASE, REG_FLAG_NEED_BO},
 262         {R_028D54_CB_COLOR4_PITCH, 0},
 263         {R_028D58_CB_COLOR4_SLICE, 0},
 264         {R_028D5C_CB_COLOR4_VIEW, 0},
 265         {R_028D60_CB_COLOR4_INFO, REG_FLAG_NEED_BO},
 266         {R_028D64_CB_COLOR4_ATTRIB, REG_FLAG_NEED_BO},
 267         {GROUP_FORCE_NEW_BLOCK, 0},
 268         {R_028D8C_CB_COLOR5_BASE, REG_FLAG_NEED_BO},
 269         {R_028D90_CB_COLOR5_PITCH, 0},
 270         {R_028D94_CB_COLOR5_SLICE, 0},
 271         {R_028D98_CB_COLOR5_VIEW, 0},
 272         {R_028D9C_CB_COLOR5_INFO, REG_FLAG_NEED_BO},
 273         {R_028DA0_CB_COLOR5_ATTRIB, REG_FLAG_NEED_BO},
 274         {GROUP_FORCE_NEW_BLOCK, 0},
 275         {R_028DC8_CB_COLOR6_BASE, REG_FLAG_NEED_BO},
 276         {R_028DCC_CB_COLOR6_PITCH, 0},
 277         {R_028DD0_CB_COLOR6_SLICE, 0},
 278         {R_028DD4_CB_COLOR6_VIEW, 0},
 279         {R_028DD8_CB_COLOR6_INFO, REG_FLAG_NEED_BO},
 280         {R_028DDC_CB_COLOR6_ATTRIB, REG_FLAG_NEED_BO},
 281         {GROUP_FORCE_NEW_BLOCK, 0},
 282         {R_028E04_CB_COLOR7_BASE, REG_FLAG_NEED_BO},
 283         {R_028E08_CB_COLOR7_PITCH, 0},
 284         {R_028E0C_CB_COLOR7_SLICE, 0},
 285         {R_028E10_CB_COLOR7_VIEW, 0},
 286         {R_028E14_CB_COLOR7_INFO, REG_FLAG_NEED_BO},
 287         {R_028E18_CB_COLOR7_ATTRIB, REG_FLAG_NEED_BO},
 288 };
 289
 290 static const struct r600_reg si_sh_reg_list[] = {
 291         {R_00B020_SPI_SHADER_PGM_LO_PS, REG_FLAG_NEED_BO},
 292         {R_00B024_SPI_SHADER_PGM_HI_PS, REG_FLAG_NEED_BO},
 293         {R_00B028_SPI_SHADER_PGM_RSRC1_PS, 0},
 294         {R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 0},
 295         {GROUP_FORCE_NEW_BLOCK, 0},
 296         {R_00B030_SPI_SHADER_USER_DATA_PS_0, REG_FLAG_NEED_BO},
 297         {R_00B034_SPI_SHADER_USER_DATA_PS_1, 0},
 298         {GROUP_FORCE_NEW_BLOCK, 0},
 299         {R_00B038_SPI_SHADER_USER_DATA_PS_2, REG_FLAG_NEED_BO},
 300         {R_00B03C_SPI_SHADER_USER_DATA_PS_3, 0},
 301         {GROUP_FORCE_NEW_BLOCK, 0},
 302         {R_00B040_SPI_SHADER_USER_DATA_PS_4, REG_FLAG_NEED_BO},
 303         {R_00B044_SPI_SHADER_USER_DATA_PS_5, 0},
 304         {GROUP_FORCE_NEW_BLOCK, 0},
 305         {R_00B048_SPI_SHADER_USER_DATA_PS_6, REG_FLAG_NEED_BO},
 306         {R_00B04C_SPI_SHADER_USER_DATA_PS_7, 0},
 307         {GROUP_FORCE_NEW_BLOCK, 0},
 308         {R_00B050_SPI_SHADER_USER_DATA_PS_8, REG_FLAG_NEED_BO},
 309         {R_00B054_SPI_SHADER_USER_DATA_PS_9, 0},
 310         {GROUP_FORCE_NEW_BLOCK, 0},
 311         {R_00B058_SPI_SHADER_USER_DATA_PS_10, REG_FLAG_NEED_BO},
 312         {R_00B05C_SPI_SHADER_USER_DATA_PS_11, 0},
 313         {GROUP_FORCE_NEW_BLOCK, 0},
 314         {R_00B060_SPI_SHADER_USER_DATA_PS_12, REG_FLAG_NEED_BO},
 315         {R_00B064_SPI_SHADER_USER_DATA_PS_13, 0},
 316         {GROUP_FORCE_NEW_BLOCK, 0},
 317         {R_00B068_SPI_SHADER_USER_DATA_PS_14, REG_FLAG_NEED_BO},
 318         {R_00B06C_SPI_SHADER_USER_DATA_PS_15, 0},
 319         {GROUP_FORCE_NEW_BLOCK, 0},
 320         {R_00B120_SPI_SHADER_PGM_LO_VS, REG_FLAG_NEED_BO},
 321         {R_00B124_SPI_SHADER_PGM_HI_VS, REG_FLAG_NEED_BO},
 322         {R_00B128_SPI_SHADER_PGM_RSRC1_VS, 0},
 323         {R_00B12C_SPI_SHADER_PGM_RSRC2_VS, 0},
 324         {GROUP_FORCE_NEW_BLOCK, 0},
 325         {R_00B130_SPI_SHADER_USER_DATA_VS_0, REG_FLAG_NEED_BO},
 326         {R_00B134_SPI_SHADER_USER_DATA_VS_1, 0},
 327         {GROUP_FORCE_NEW_BLOCK, 0},
 328         {R_00B138_SPI_SHADER_USER_DATA_VS_2, REG_FLAG_NEED_BO},
 329         {R_00B13C_SPI_SHADER_USER_DATA_VS_3, 0},
 330         {GROUP_FORCE_NEW_BLOCK, 0},
 331         {R_00B140_SPI_SHADER_USER_DATA_VS_4, REG_FLAG_NEED_BO},
 332         {R_00B144_SPI_SHADER_USER_DATA_VS_5, 0},
 333         {GROUP_FORCE_NEW_BLOCK, 0},
 334         {R_00B148_SPI_SHADER_USER_DATA_VS_6, REG_FLAG_NEED_BO},
 335         {R_00B14C_SPI_SHADER_USER_DATA_VS_7, 0},
 336         {GROUP_FORCE_NEW_BLOCK, 0},
 337         {R_00B150_SPI_SHADER_USER_DATA_VS_8, REG_FLAG_NEED_BO},
 338         {R_00B154_SPI_SHADER_USER_DATA_VS_9, 0},
 339         {GROUP_FORCE_NEW_BLOCK, 0},
 340         {R_00B158_SPI_SHADER_USER_DATA_VS_10, REG_FLAG_NEED_BO},
 341         {R_00B15C_SPI_SHADER_USER_DATA_VS_11, 0},
 342         {GROUP_FORCE_NEW_BLOCK, 0},
 343         {R_00B160_SPI_SHADER_USER_DATA_VS_12, REG_FLAG_NEED_BO},
 344         {R_00B164_SPI_SHADER_USER_DATA_VS_13, 0},
 345         {GROUP_FORCE_NEW_BLOCK, 0},
 346         {R_00B168_SPI_SHADER_USER_DATA_VS_14, REG_FLAG_NEED_BO},
 347         {R_00B16C_SPI_SHADER_USER_DATA_VS_15, 0},
 348 };
 349
 350 int si_context_init(struct r600_context *ctx)
 351 {
 352         int r;
 353
 354         LIST_INITHEAD(&ctx->active_query_list);
 355
 356         /* init dirty list */
 357         LIST_INITHEAD(&ctx->dirty);
 358         LIST_INITHEAD(&ctx->enable_list);
 359
 360         ctx->range = calloc(NUM_RANGES, sizeof(struct r600_range));
 361         if (!ctx->range) {
 362                 r = -ENOMEM;
 363                 goto out_err;
 364         }
 365
 366         /* add blocks */
 367         r = r600_context_add_block(ctx, si_config_reg_list,
 368                                    Elements(si_config_reg_list), PKT3_SET_CONFIG_REG, SI_CONFIG_REG_OFFSET);
 369         if (r)
 370                 goto out_err;
 371         r = r600_context_add_block(ctx, si_context_reg_list,
 372                                    Elements(si_context_reg_list), PKT3_SET_CONTEXT_REG, SI_CONTEXT_REG_OFFSET);
 373         if (r)
 374                 goto out_err;
 375         r = r600_context_add_block(ctx, si_sh_reg_list,
 376                                    Elements(si_sh_reg_list), PKT3_SET_SH_REG, SI_SH_REG_OFFSET);
 377         if (r)
 378                 goto out_err;
 379
 380
 381         /* PS SAMPLER */
 382         /* VS SAMPLER */
 383
 384         /* PS SAMPLER BORDER */
 385         /* VS SAMPLER BORDER */
 386
 387         /* PS RESOURCES */
 388         /* VS RESOURCES */
 389
 390         ctx->cs = ctx->ws->cs_create(ctx->ws);
 391
 392         r600_init_cs(ctx);
 393         ctx->max_db = 8;
 394         return 0;
 395 out_err:
 396         r600_context_fini(ctx);
 397         return r;
 398 }
 399
 400 static inline void evergreen_context_ps_partial_flush(struct r600_context *ctx)
 401 {
 402         struct radeon_winsys_cs *cs = ctx->cs;
 403
 404         if (!(ctx->flags & R600_CONTEXT_DRAW_PENDING))
 405                 return;
 406
 407         cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
 408         cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
 409
 410         ctx->flags &= ~R600_CONTEXT_DRAW_PENDING;
 411 }
 412
 413 void si_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
 414 {
 415         struct radeon_winsys_cs *cs = ctx->cs;
 416         unsigned ndwords = 7;
 417         uint32_t *pm4;
 418         uint64_t va;
 419
 420         if (draw->indices) {
 421                 ndwords = 12;
 422         }
 423         if (ctx->num_cs_dw_queries_suspend)
 424                 ndwords += 6;
 425
 426         /* when increasing ndwords, bump the max limit too */
 427         assert(ndwords <= SI_MAX_DRAW_CS_DWORDS);
 428
 429         /* queries need some special values
 430          * (this is non-zero if any query is active) */
 431         if (ctx->num_cs_dw_queries_suspend) {
 432                 pm4 = &cs->buf[cs->cdw];
 433                 pm4[0] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
 434                 pm4[1] = (R_028004_DB_COUNT_CONTROL - SI_CONTEXT_REG_OFFSET) >> 2;
 435                 pm4[2] = S_028004_PERFECT_ZPASS_COUNTS(1);
 436                 pm4[3] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
 437                 pm4[4] = (R_02800C_DB_RENDER_OVERRIDE - SI_CONTEXT_REG_OFFSET) >> 2;
 438                 pm4[5] = draw->db_render_override | S_02800C_NOOP_CULL_DISABLE(1);
 439                 cs->cdw += 6;
 440                 ndwords -= 6;
 441         }
 442
 443         /* draw packet */
 444         pm4 = &cs->buf[cs->cdw];
 445         pm4[0] = PKT3(PKT3_INDEX_TYPE, 0, ctx->predicate_drawing);
 446         pm4[1] = draw->vgt_index_type;
 447         pm4[2] = PKT3(PKT3_NUM_INSTANCES, 0, ctx->predicate_drawing);
 448         pm4[3] = draw->vgt_num_instances;
 449         if (draw->indices) {
 450                 va = r600_resource_va(&ctx->screen->screen, (void*)draw->indices);
 451                 va += draw->indices_bo_offset;
 452                 pm4[4] = PKT3(PKT3_DRAW_INDEX_2, 4, ctx->predicate_drawing);
 453                 pm4[5] = (draw->indices->b.b.width0 - draw->indices_bo_offset) /
 454                         ctx->index_buffer.index_size;
 455                 pm4[6] = va;
 456                 pm4[7] = (va >> 32UL) & 0xFF;
 457                 pm4[8] = draw->vgt_num_indices;
 458                 pm4[9] = draw->vgt_draw_initiator;
 459                 pm4[10] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing);
 460                 pm4[11] = r600_context_bo_reloc(ctx, draw->indices, RADEON_USAGE_READ);
 461         } else {
 462                 pm4[4] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, ctx->predicate_drawing);
 463                 pm4[5] = draw->vgt_num_indices;
 464                 pm4[6] = draw->vgt_draw_initiator;
 465         }
 466         cs->cdw += ndwords;
 467 }
 468
 469 void evergreen_flush_vgt_streamout(struct r600_context *ctx)
 470 {
 471         struct radeon_winsys_cs *cs = ctx->cs;
 472
 473         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, 1, 0);
 474         cs->buf[cs->cdw++] = (R_0084FC_CP_STRMOUT_CNTL - SI_CONFIG_REG_OFFSET) >> 2;
 475         cs->buf[cs->cdw++] = 0;
 476
 477         cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
 478         cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0);
 479
 480         cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0);
 481         cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */
 482         cs->buf[cs->cdw++] = R_0084FC_CP_STRMOUT_CNTL >> 2;  /* register */
 483         cs->buf[cs->cdw++] = 0;
 484         cs->buf[cs->cdw++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* reference value */
 485         cs->buf[cs->cdw++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* mask */
 486         cs->buf[cs->cdw++] = 4; /* poll interval */
 487 }
 488
 489 void evergreen_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit)
 490 {
 491         struct radeon_winsys_cs *cs = ctx->cs;
 492
 493         if (buffer_enable_bit) {
 494                 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
 495                 cs->buf[cs->cdw++] = (R_028B94_VGT_STRMOUT_CONFIG - SI_CONTEXT_REG_OFFSET) >> 2;
 496                 cs->buf[cs->cdw++] = S_028B94_STREAMOUT_0_EN(1);
 497
 498                 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
 499                 cs->buf[cs->cdw++] = (R_028B98_VGT_STRMOUT_BUFFER_CONFIG - SI_CONTEXT_REG_OFFSET) >> 2;
 500                 cs->buf[cs->cdw++] = S_028B98_STREAM_0_BUFFER_EN(buffer_enable_bit);
 501         } else {
 502                 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
 503                 cs->buf[cs->cdw++] = (R_028B94_VGT_STRMOUT_CONFIG - SI_CONTEXT_REG_OFFSET) >> 2;
 504                 cs->buf[cs->cdw++] = S_028B94_STREAMOUT_0_EN(0);
 505         }
 506 }