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radeonsi: move clip state to new handling
[mesa.git] / src / gallium / drivers / radeonsi / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include "pipe/p_defines.h"
30 #include "pipe/p_state.h"
31 #include "pipe/p_context.h"
32 #include "tgsi/tgsi_scan.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_util.h"
35 #include "util/u_blitter.h"
36 #include "util/u_double_list.h"
37 #include "util/u_transfer.h"
38 #include "util/u_surface.h"
39 #include "util/u_pack_color.h"
40 #include "util/u_memory.h"
41 #include "util/u_inlines.h"
42 #include "util/u_framebuffer.h"
43 #include "pipebuffer/pb_buffer.h"
44 #include "r600.h"
45 #include "sid.h"
46 #include "r600_resource.h"
47 #include "radeonsi_pipe.h"
48 #include "si_state.h"
49
50 #if 0
51 static uint32_t r600_translate_stencil_op(int s_op)
52 {
53 switch (s_op) {
54 case PIPE_STENCIL_OP_KEEP:
55 return V_028800_STENCIL_KEEP;
56 case PIPE_STENCIL_OP_ZERO:
57 return V_028800_STENCIL_ZERO;
58 case PIPE_STENCIL_OP_REPLACE:
59 return V_028800_STENCIL_REPLACE;
60 case PIPE_STENCIL_OP_INCR:
61 return V_028800_STENCIL_INCR;
62 case PIPE_STENCIL_OP_DECR:
63 return V_028800_STENCIL_DECR;
64 case PIPE_STENCIL_OP_INCR_WRAP:
65 return V_028800_STENCIL_INCR_WRAP;
66 case PIPE_STENCIL_OP_DECR_WRAP:
67 return V_028800_STENCIL_DECR_WRAP;
68 case PIPE_STENCIL_OP_INVERT:
69 return V_028800_STENCIL_INVERT;
70 default:
71 R600_ERR("Unknown stencil op %d", s_op);
72 assert(0);
73 break;
74 }
75 return 0;
76 }
77 #endif
78
79 static uint32_t si_translate_fill(uint32_t func)
80 {
81 switch(func) {
82 case PIPE_POLYGON_MODE_FILL:
83 return V_028814_X_DRAW_TRIANGLES;
84 case PIPE_POLYGON_MODE_LINE:
85 return V_028814_X_DRAW_LINES;
86 case PIPE_POLYGON_MODE_POINT:
87 return V_028814_X_DRAW_POINTS;
88 default:
89 assert(0);
90 return V_028814_X_DRAW_POINTS;
91 }
92 }
93
94 /* translates straight */
95 static uint32_t si_translate_ds_func(int func)
96 {
97 return func;
98 }
99
100 static unsigned si_tex_wrap(unsigned wrap)
101 {
102 switch (wrap) {
103 default:
104 case PIPE_TEX_WRAP_REPEAT:
105 return V_008F30_SQ_TEX_WRAP;
106 case PIPE_TEX_WRAP_CLAMP:
107 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
108 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
109 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
110 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
111 return V_008F30_SQ_TEX_CLAMP_BORDER;
112 case PIPE_TEX_WRAP_MIRROR_REPEAT:
113 return V_008F30_SQ_TEX_MIRROR;
114 case PIPE_TEX_WRAP_MIRROR_CLAMP:
115 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
116 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
117 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
118 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
119 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
120 }
121 }
122
123 static unsigned si_tex_filter(unsigned filter)
124 {
125 switch (filter) {
126 default:
127 case PIPE_TEX_FILTER_NEAREST:
128 return V_008F38_SQ_TEX_XY_FILTER_POINT;
129 case PIPE_TEX_FILTER_LINEAR:
130 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
131 }
132 }
133
134 static unsigned si_tex_mipfilter(unsigned filter)
135 {
136 switch (filter) {
137 case PIPE_TEX_MIPFILTER_NEAREST:
138 return V_008F38_SQ_TEX_Z_FILTER_POINT;
139 case PIPE_TEX_MIPFILTER_LINEAR:
140 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
141 default:
142 case PIPE_TEX_MIPFILTER_NONE:
143 return V_008F38_SQ_TEX_Z_FILTER_NONE;
144 }
145 }
146
147 static unsigned si_tex_compare(unsigned compare)
148 {
149 switch (compare) {
150 default:
151 case PIPE_FUNC_NEVER:
152 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
153 case PIPE_FUNC_LESS:
154 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
155 case PIPE_FUNC_EQUAL:
156 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
157 case PIPE_FUNC_LEQUAL:
158 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
159 case PIPE_FUNC_GREATER:
160 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
161 case PIPE_FUNC_NOTEQUAL:
162 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
163 case PIPE_FUNC_GEQUAL:
164 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
165 case PIPE_FUNC_ALWAYS:
166 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
167 }
168 }
169
170 static unsigned si_tex_dim(unsigned dim)
171 {
172 switch (dim) {
173 default:
174 case PIPE_TEXTURE_1D:
175 return V_008F1C_SQ_RSRC_IMG_1D;
176 case PIPE_TEXTURE_1D_ARRAY:
177 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
178 case PIPE_TEXTURE_2D:
179 case PIPE_TEXTURE_RECT:
180 return V_008F1C_SQ_RSRC_IMG_2D;
181 case PIPE_TEXTURE_2D_ARRAY:
182 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
183 case PIPE_TEXTURE_3D:
184 return V_008F1C_SQ_RSRC_IMG_3D;
185 case PIPE_TEXTURE_CUBE:
186 return V_008F1C_SQ_RSRC_IMG_CUBE;
187 }
188 }
189
190 static uint32_t si_translate_dbformat(enum pipe_format format)
191 {
192 switch (format) {
193 case PIPE_FORMAT_Z16_UNORM:
194 return V_028040_Z_16;
195 case PIPE_FORMAT_Z24X8_UNORM:
196 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
197 return V_028040_Z_24; /* XXX no longer supported on SI */
198 case PIPE_FORMAT_Z32_FLOAT:
199 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
200 return V_028040_Z_32_FLOAT;
201 default:
202 return ~0U;
203 }
204 }
205
206 static uint32_t si_translate_colorswap(enum pipe_format format)
207 {
208 switch (format) {
209 /* 8-bit buffers. */
210 case PIPE_FORMAT_L4A4_UNORM:
211 case PIPE_FORMAT_A4R4_UNORM:
212 return V_028C70_SWAP_ALT;
213
214 case PIPE_FORMAT_A8_UNORM:
215 case PIPE_FORMAT_A8_UINT:
216 case PIPE_FORMAT_A8_SINT:
217 case PIPE_FORMAT_R4A4_UNORM:
218 return V_028C70_SWAP_ALT_REV;
219 case PIPE_FORMAT_I8_UNORM:
220 case PIPE_FORMAT_L8_UNORM:
221 case PIPE_FORMAT_I8_UINT:
222 case PIPE_FORMAT_I8_SINT:
223 case PIPE_FORMAT_L8_UINT:
224 case PIPE_FORMAT_L8_SINT:
225 case PIPE_FORMAT_L8_SRGB:
226 case PIPE_FORMAT_R8_UNORM:
227 case PIPE_FORMAT_R8_SNORM:
228 case PIPE_FORMAT_R8_UINT:
229 case PIPE_FORMAT_R8_SINT:
230 return V_028C70_SWAP_STD;
231
232 /* 16-bit buffers. */
233 case PIPE_FORMAT_B5G6R5_UNORM:
234 return V_028C70_SWAP_STD_REV;
235
236 case PIPE_FORMAT_B5G5R5A1_UNORM:
237 case PIPE_FORMAT_B5G5R5X1_UNORM:
238 return V_028C70_SWAP_ALT;
239
240 case PIPE_FORMAT_B4G4R4A4_UNORM:
241 case PIPE_FORMAT_B4G4R4X4_UNORM:
242 return V_028C70_SWAP_ALT;
243
244 case PIPE_FORMAT_Z16_UNORM:
245 return V_028C70_SWAP_STD;
246
247 case PIPE_FORMAT_L8A8_UNORM:
248 case PIPE_FORMAT_L8A8_UINT:
249 case PIPE_FORMAT_L8A8_SINT:
250 case PIPE_FORMAT_L8A8_SRGB:
251 return V_028C70_SWAP_ALT;
252 case PIPE_FORMAT_R8G8_UNORM:
253 case PIPE_FORMAT_R8G8_UINT:
254 case PIPE_FORMAT_R8G8_SINT:
255 return V_028C70_SWAP_STD;
256
257 case PIPE_FORMAT_R16_UNORM:
258 case PIPE_FORMAT_R16_UINT:
259 case PIPE_FORMAT_R16_SINT:
260 case PIPE_FORMAT_R16_FLOAT:
261 return V_028C70_SWAP_STD;
262
263 /* 32-bit buffers. */
264 case PIPE_FORMAT_A8B8G8R8_SRGB:
265 return V_028C70_SWAP_STD_REV;
266 case PIPE_FORMAT_B8G8R8A8_SRGB:
267 return V_028C70_SWAP_ALT;
268
269 case PIPE_FORMAT_B8G8R8A8_UNORM:
270 case PIPE_FORMAT_B8G8R8X8_UNORM:
271 return V_028C70_SWAP_ALT;
272
273 case PIPE_FORMAT_A8R8G8B8_UNORM:
274 case PIPE_FORMAT_X8R8G8B8_UNORM:
275 return V_028C70_SWAP_ALT_REV;
276 case PIPE_FORMAT_R8G8B8A8_SNORM:
277 case PIPE_FORMAT_R8G8B8A8_UNORM:
278 case PIPE_FORMAT_R8G8B8A8_SSCALED:
279 case PIPE_FORMAT_R8G8B8A8_USCALED:
280 case PIPE_FORMAT_R8G8B8A8_SINT:
281 case PIPE_FORMAT_R8G8B8A8_UINT:
282 case PIPE_FORMAT_R8G8B8X8_UNORM:
283 return V_028C70_SWAP_STD;
284
285 case PIPE_FORMAT_A8B8G8R8_UNORM:
286 case PIPE_FORMAT_X8B8G8R8_UNORM:
287 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
288 return V_028C70_SWAP_STD_REV;
289
290 case PIPE_FORMAT_Z24X8_UNORM:
291 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
292 return V_028C70_SWAP_STD;
293
294 case PIPE_FORMAT_X8Z24_UNORM:
295 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
296 return V_028C70_SWAP_STD;
297
298 case PIPE_FORMAT_R10G10B10A2_UNORM:
299 case PIPE_FORMAT_R10G10B10X2_SNORM:
300 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
301 return V_028C70_SWAP_STD;
302
303 case PIPE_FORMAT_B10G10R10A2_UNORM:
304 case PIPE_FORMAT_B10G10R10A2_UINT:
305 return V_028C70_SWAP_ALT;
306
307 case PIPE_FORMAT_R11G11B10_FLOAT:
308 case PIPE_FORMAT_R32_FLOAT:
309 case PIPE_FORMAT_R32_UINT:
310 case PIPE_FORMAT_R32_SINT:
311 case PIPE_FORMAT_Z32_FLOAT:
312 case PIPE_FORMAT_R16G16_FLOAT:
313 case PIPE_FORMAT_R16G16_UNORM:
314 case PIPE_FORMAT_R16G16_UINT:
315 case PIPE_FORMAT_R16G16_SINT:
316 return V_028C70_SWAP_STD;
317
318 /* 64-bit buffers. */
319 case PIPE_FORMAT_R32G32_FLOAT:
320 case PIPE_FORMAT_R32G32_UINT:
321 case PIPE_FORMAT_R32G32_SINT:
322 case PIPE_FORMAT_R16G16B16A16_UNORM:
323 case PIPE_FORMAT_R16G16B16A16_SNORM:
324 case PIPE_FORMAT_R16G16B16A16_USCALED:
325 case PIPE_FORMAT_R16G16B16A16_SSCALED:
326 case PIPE_FORMAT_R16G16B16A16_UINT:
327 case PIPE_FORMAT_R16G16B16A16_SINT:
328 case PIPE_FORMAT_R16G16B16A16_FLOAT:
329 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
330
331 /* 128-bit buffers. */
332 case PIPE_FORMAT_R32G32B32A32_FLOAT:
333 case PIPE_FORMAT_R32G32B32A32_SNORM:
334 case PIPE_FORMAT_R32G32B32A32_UNORM:
335 case PIPE_FORMAT_R32G32B32A32_SSCALED:
336 case PIPE_FORMAT_R32G32B32A32_USCALED:
337 case PIPE_FORMAT_R32G32B32A32_SINT:
338 case PIPE_FORMAT_R32G32B32A32_UINT:
339 return V_028C70_SWAP_STD;
340 default:
341 R600_ERR("unsupported colorswap format %d\n", format);
342 return ~0U;
343 }
344 return ~0U;
345 }
346
347 static uint32_t si_translate_colorformat(enum pipe_format format)
348 {
349 switch (format) {
350 /* 8-bit buffers. */
351 case PIPE_FORMAT_A8_UNORM:
352 case PIPE_FORMAT_A8_UINT:
353 case PIPE_FORMAT_A8_SINT:
354 case PIPE_FORMAT_I8_UNORM:
355 case PIPE_FORMAT_I8_UINT:
356 case PIPE_FORMAT_I8_SINT:
357 case PIPE_FORMAT_L8_UNORM:
358 case PIPE_FORMAT_L8_UINT:
359 case PIPE_FORMAT_L8_SINT:
360 case PIPE_FORMAT_L8_SRGB:
361 case PIPE_FORMAT_R8_UNORM:
362 case PIPE_FORMAT_R8_SNORM:
363 case PIPE_FORMAT_R8_UINT:
364 case PIPE_FORMAT_R8_SINT:
365 return V_028C70_COLOR_8;
366
367 /* 16-bit buffers. */
368 case PIPE_FORMAT_B5G6R5_UNORM:
369 return V_028C70_COLOR_5_6_5;
370
371 case PIPE_FORMAT_B5G5R5A1_UNORM:
372 case PIPE_FORMAT_B5G5R5X1_UNORM:
373 return V_028C70_COLOR_1_5_5_5;
374
375 case PIPE_FORMAT_B4G4R4A4_UNORM:
376 case PIPE_FORMAT_B4G4R4X4_UNORM:
377 return V_028C70_COLOR_4_4_4_4;
378
379 case PIPE_FORMAT_L8A8_UNORM:
380 case PIPE_FORMAT_L8A8_UINT:
381 case PIPE_FORMAT_L8A8_SINT:
382 case PIPE_FORMAT_L8A8_SRGB:
383 case PIPE_FORMAT_R8G8_UNORM:
384 case PIPE_FORMAT_R8G8_UINT:
385 case PIPE_FORMAT_R8G8_SINT:
386 return V_028C70_COLOR_8_8;
387
388 case PIPE_FORMAT_Z16_UNORM:
389 case PIPE_FORMAT_R16_UNORM:
390 case PIPE_FORMAT_R16_UINT:
391 case PIPE_FORMAT_R16_SINT:
392 case PIPE_FORMAT_R16_FLOAT:
393 case PIPE_FORMAT_R16G16_FLOAT:
394 return V_028C70_COLOR_16;
395
396 /* 32-bit buffers. */
397 case PIPE_FORMAT_A8B8G8R8_SRGB:
398 case PIPE_FORMAT_A8B8G8R8_UNORM:
399 case PIPE_FORMAT_A8R8G8B8_UNORM:
400 case PIPE_FORMAT_B8G8R8A8_SRGB:
401 case PIPE_FORMAT_B8G8R8A8_UNORM:
402 case PIPE_FORMAT_B8G8R8X8_UNORM:
403 case PIPE_FORMAT_R8G8B8A8_SNORM:
404 case PIPE_FORMAT_R8G8B8A8_UNORM:
405 case PIPE_FORMAT_R8G8B8X8_UNORM:
406 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
407 case PIPE_FORMAT_X8B8G8R8_UNORM:
408 case PIPE_FORMAT_X8R8G8B8_UNORM:
409 case PIPE_FORMAT_R8G8B8_UNORM:
410 case PIPE_FORMAT_R8G8B8A8_SSCALED:
411 case PIPE_FORMAT_R8G8B8A8_USCALED:
412 case PIPE_FORMAT_R8G8B8A8_SINT:
413 case PIPE_FORMAT_R8G8B8A8_UINT:
414 return V_028C70_COLOR_8_8_8_8;
415
416 case PIPE_FORMAT_R10G10B10A2_UNORM:
417 case PIPE_FORMAT_R10G10B10X2_SNORM:
418 case PIPE_FORMAT_B10G10R10A2_UNORM:
419 case PIPE_FORMAT_B10G10R10A2_UINT:
420 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
421 return V_028C70_COLOR_2_10_10_10;
422
423 case PIPE_FORMAT_Z24X8_UNORM:
424 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
425 return V_028C70_COLOR_8_24;
426
427 case PIPE_FORMAT_X8Z24_UNORM:
428 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
429 return V_028C70_COLOR_24_8;
430
431 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
432 return V_028C70_COLOR_X24_8_32_FLOAT;
433
434 case PIPE_FORMAT_R32_FLOAT:
435 case PIPE_FORMAT_Z32_FLOAT:
436 return V_028C70_COLOR_32;
437
438 case PIPE_FORMAT_R16G16_SSCALED:
439 case PIPE_FORMAT_R16G16_UNORM:
440 case PIPE_FORMAT_R16G16_UINT:
441 case PIPE_FORMAT_R16G16_SINT:
442 return V_028C70_COLOR_16_16;
443
444 case PIPE_FORMAT_R11G11B10_FLOAT:
445 return V_028C70_COLOR_10_11_11;
446
447 /* 64-bit buffers. */
448 case PIPE_FORMAT_R16G16B16_USCALED:
449 case PIPE_FORMAT_R16G16B16_SSCALED:
450 case PIPE_FORMAT_R16G16B16A16_UINT:
451 case PIPE_FORMAT_R16G16B16A16_SINT:
452 case PIPE_FORMAT_R16G16B16A16_USCALED:
453 case PIPE_FORMAT_R16G16B16A16_SSCALED:
454 case PIPE_FORMAT_R16G16B16A16_UNORM:
455 case PIPE_FORMAT_R16G16B16A16_SNORM:
456 case PIPE_FORMAT_R16G16B16_FLOAT:
457 case PIPE_FORMAT_R16G16B16A16_FLOAT:
458 return V_028C70_COLOR_16_16_16_16;
459
460 case PIPE_FORMAT_R32G32_FLOAT:
461 case PIPE_FORMAT_R32G32_USCALED:
462 case PIPE_FORMAT_R32G32_SSCALED:
463 case PIPE_FORMAT_R32G32_SINT:
464 case PIPE_FORMAT_R32G32_UINT:
465 return V_028C70_COLOR_32_32;
466
467 /* 128-bit buffers. */
468 case PIPE_FORMAT_R32G32B32A32_SNORM:
469 case PIPE_FORMAT_R32G32B32A32_UNORM:
470 case PIPE_FORMAT_R32G32B32A32_SSCALED:
471 case PIPE_FORMAT_R32G32B32A32_USCALED:
472 case PIPE_FORMAT_R32G32B32A32_SINT:
473 case PIPE_FORMAT_R32G32B32A32_UINT:
474 case PIPE_FORMAT_R32G32B32A32_FLOAT:
475 return V_028C70_COLOR_32_32_32_32;
476
477 /* YUV buffers. */
478 case PIPE_FORMAT_UYVY:
479 case PIPE_FORMAT_YUYV:
480 /* 96-bit buffers. */
481 case PIPE_FORMAT_R32G32B32_FLOAT:
482 /* 8-bit buffers. */
483 case PIPE_FORMAT_L4A4_UNORM:
484 case PIPE_FORMAT_R4A4_UNORM:
485 case PIPE_FORMAT_A4R4_UNORM:
486 default:
487 return ~0U; /* Unsupported. */
488 }
489 }
490
491 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
492 {
493 if (R600_BIG_ENDIAN) {
494 switch(colorformat) {
495 /* 8-bit buffers. */
496 case V_028C70_COLOR_8:
497 return V_028C70_ENDIAN_NONE;
498
499 /* 16-bit buffers. */
500 case V_028C70_COLOR_5_6_5:
501 case V_028C70_COLOR_1_5_5_5:
502 case V_028C70_COLOR_4_4_4_4:
503 case V_028C70_COLOR_16:
504 case V_028C70_COLOR_8_8:
505 return V_028C70_ENDIAN_8IN16;
506
507 /* 32-bit buffers. */
508 case V_028C70_COLOR_8_8_8_8:
509 case V_028C70_COLOR_2_10_10_10:
510 case V_028C70_COLOR_8_24:
511 case V_028C70_COLOR_24_8:
512 case V_028C70_COLOR_16_16:
513 return V_028C70_ENDIAN_8IN32;
514
515 /* 64-bit buffers. */
516 case V_028C70_COLOR_16_16_16_16:
517 return V_028C70_ENDIAN_8IN16;
518
519 case V_028C70_COLOR_32_32:
520 return V_028C70_ENDIAN_8IN32;
521
522 /* 128-bit buffers. */
523 case V_028C70_COLOR_32_32_32_32:
524 return V_028C70_ENDIAN_8IN32;
525 default:
526 return V_028C70_ENDIAN_NONE; /* Unsupported. */
527 }
528 } else {
529 return V_028C70_ENDIAN_NONE;
530 }
531 }
532
533 static uint32_t si_translate_texformat(struct pipe_screen *screen,
534 enum pipe_format format,
535 const struct util_format_description *desc,
536 int first_non_void)
537 {
538 boolean uniform = TRUE;
539 int i;
540
541 /* Colorspace (return non-RGB formats directly). */
542 switch (desc->colorspace) {
543 /* Depth stencil formats */
544 case UTIL_FORMAT_COLORSPACE_ZS:
545 switch (format) {
546 case PIPE_FORMAT_Z16_UNORM:
547 return V_008F14_IMG_DATA_FORMAT_16;
548 case PIPE_FORMAT_X24S8_UINT:
549 case PIPE_FORMAT_Z24X8_UNORM:
550 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
551 return V_008F14_IMG_DATA_FORMAT_24_8;
552 case PIPE_FORMAT_S8X24_UINT:
553 case PIPE_FORMAT_X8Z24_UNORM:
554 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
555 return V_008F14_IMG_DATA_FORMAT_8_24;
556 case PIPE_FORMAT_S8_UINT:
557 return V_008F14_IMG_DATA_FORMAT_8;
558 case PIPE_FORMAT_Z32_FLOAT:
559 return V_008F14_IMG_DATA_FORMAT_32;
560 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
561 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
562 default:
563 goto out_unknown;
564 }
565
566 case UTIL_FORMAT_COLORSPACE_YUV:
567 goto out_unknown; /* TODO */
568
569 case UTIL_FORMAT_COLORSPACE_SRGB:
570 break;
571
572 default:
573 break;
574 }
575
576 /* TODO compressed formats */
577
578 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
579 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
580 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
581 return V_008F14_IMG_DATA_FORMAT_10_11_11;
582 }
583
584 /* R8G8Bx_SNORM - TODO CxV8U8 */
585
586 /* See whether the components are of the same size. */
587 for (i = 1; i < desc->nr_channels; i++) {
588 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
589 }
590
591 /* Non-uniform formats. */
592 if (!uniform) {
593 switch(desc->nr_channels) {
594 case 3:
595 if (desc->channel[0].size == 5 &&
596 desc->channel[1].size == 6 &&
597 desc->channel[2].size == 5) {
598 return V_008F14_IMG_DATA_FORMAT_5_6_5;
599 }
600 goto out_unknown;
601 case 4:
602 if (desc->channel[0].size == 5 &&
603 desc->channel[1].size == 5 &&
604 desc->channel[2].size == 5 &&
605 desc->channel[3].size == 1) {
606 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
607 }
608 if (desc->channel[0].size == 10 &&
609 desc->channel[1].size == 10 &&
610 desc->channel[2].size == 10 &&
611 desc->channel[3].size == 2) {
612 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
613 }
614 goto out_unknown;
615 }
616 goto out_unknown;
617 }
618
619 if (first_non_void < 0 || first_non_void > 3)
620 goto out_unknown;
621
622 /* uniform formats */
623 switch (desc->channel[first_non_void].size) {
624 case 4:
625 switch (desc->nr_channels) {
626 case 2:
627 return V_008F14_IMG_DATA_FORMAT_4_4;
628 case 4:
629 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
630 }
631 break;
632 case 8:
633 switch (desc->nr_channels) {
634 case 1:
635 return V_008F14_IMG_DATA_FORMAT_8;
636 case 2:
637 return V_008F14_IMG_DATA_FORMAT_8_8;
638 case 4:
639 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
640 }
641 break;
642 case 16:
643 switch (desc->nr_channels) {
644 case 1:
645 return V_008F14_IMG_DATA_FORMAT_16;
646 case 2:
647 return V_008F14_IMG_DATA_FORMAT_16_16;
648 case 4:
649 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
650 }
651 break;
652 case 32:
653 switch (desc->nr_channels) {
654 case 1:
655 return V_008F14_IMG_DATA_FORMAT_32;
656 case 2:
657 return V_008F14_IMG_DATA_FORMAT_32_32;
658 case 3:
659 return V_008F14_IMG_DATA_FORMAT_32_32_32;
660 case 4:
661 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
662 }
663 }
664
665 out_unknown:
666 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
667 return ~0;
668 }
669
670 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
671 {
672 return si_translate_texformat(screen, format, util_format_description(format),
673 util_format_get_first_non_void_channel(format)) != ~0U;
674 }
675
676 uint32_t si_translate_vertexformat(struct pipe_screen *screen,
677 enum pipe_format format,
678 const struct util_format_description *desc,
679 int first_non_void)
680 {
681 uint32_t result;
682
683 if (desc->channel[first_non_void].type == UTIL_FORMAT_TYPE_FIXED)
684 return ~0;
685
686 result = si_translate_texformat(screen, format, desc, first_non_void);
687 if (result == V_008F0C_BUF_DATA_FORMAT_INVALID ||
688 result > V_008F0C_BUF_DATA_FORMAT_32_32_32_32)
689 result = ~0;
690
691 return result;
692 }
693
694 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
695 {
696 return si_translate_vertexformat(screen, format, util_format_description(format),
697 util_format_get_first_non_void_channel(format)) != ~0U;
698 }
699
700 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
701 {
702 return si_translate_colorformat(format) != ~0U &&
703 si_translate_colorswap(format) != ~0U;
704 }
705
706 static bool r600_is_zs_format_supported(enum pipe_format format)
707 {
708 return si_translate_dbformat(format) != ~0U;
709 }
710
711 boolean si_is_format_supported(struct pipe_screen *screen,
712 enum pipe_format format,
713 enum pipe_texture_target target,
714 unsigned sample_count,
715 unsigned usage)
716 {
717 unsigned retval = 0;
718
719 if (target >= PIPE_MAX_TEXTURE_TYPES) {
720 R600_ERR("r600: unsupported texture type %d\n", target);
721 return FALSE;
722 }
723
724 if (!util_format_is_supported(format, usage))
725 return FALSE;
726
727 /* Multisample */
728 if (sample_count > 1)
729 return FALSE;
730
731 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
732 si_is_sampler_format_supported(screen, format)) {
733 retval |= PIPE_BIND_SAMPLER_VIEW;
734 }
735
736 if ((usage & (PIPE_BIND_RENDER_TARGET |
737 PIPE_BIND_DISPLAY_TARGET |
738 PIPE_BIND_SCANOUT |
739 PIPE_BIND_SHARED)) &&
740 r600_is_colorbuffer_format_supported(format)) {
741 retval |= usage &
742 (PIPE_BIND_RENDER_TARGET |
743 PIPE_BIND_DISPLAY_TARGET |
744 PIPE_BIND_SCANOUT |
745 PIPE_BIND_SHARED);
746 }
747
748 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
749 r600_is_zs_format_supported(format)) {
750 retval |= PIPE_BIND_DEPTH_STENCIL;
751 }
752
753 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
754 si_is_vertex_format_supported(screen, format)) {
755 retval |= PIPE_BIND_VERTEX_BUFFER;
756 }
757
758 if (usage & PIPE_BIND_TRANSFER_READ)
759 retval |= PIPE_BIND_TRANSFER_READ;
760 if (usage & PIPE_BIND_TRANSFER_WRITE)
761 retval |= PIPE_BIND_TRANSFER_WRITE;
762
763 return retval == usage;
764 }
765
766 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
767 const struct pipe_depth_stencil_alpha_state *state)
768 {
769 struct r600_context *rctx = (struct r600_context *)ctx;
770 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
771 unsigned db_depth_control, alpha_test_control, alpha_ref;
772 unsigned db_render_override, db_render_control;
773 struct r600_pipe_state *rstate;
774
775 if (dsa == NULL) {
776 return NULL;
777 }
778
779 dsa->valuemask[0] = state->stencil[0].valuemask;
780 dsa->valuemask[1] = state->stencil[1].valuemask;
781 dsa->writemask[0] = state->stencil[0].writemask;
782 dsa->writemask[1] = state->stencil[1].writemask;
783
784 rstate = &dsa->rstate;
785
786 rstate->id = R600_PIPE_STATE_DSA;
787 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
788 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
789 S_028800_ZFUNC(state->depth.func);
790
791 /* stencil */
792 if (state->stencil[0].enabled) {
793 db_depth_control |= S_028800_STENCIL_ENABLE(1);
794 db_depth_control |= S_028800_STENCILFUNC(si_translate_ds_func(state->stencil[0].func));
795 //db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
796 //db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
797 //db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
798
799 if (state->stencil[1].enabled) {
800 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
801 db_depth_control |= S_028800_STENCILFUNC_BF(si_translate_ds_func(state->stencil[1].func));
802 //db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
803 //db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
804 //db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
805 }
806 }
807
808 /* alpha */
809 alpha_test_control = 0;
810 alpha_ref = 0;
811 if (state->alpha.enabled) {
812 //alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
813 //alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
814 alpha_ref = fui(state->alpha.ref_value);
815 }
816 dsa->alpha_ref = alpha_ref;
817
818 /* misc */
819 db_render_control = 0;
820 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
821 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
822 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
823 /* TODO db_render_override depends on query */
824 r600_pipe_state_add_reg(rstate, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000, NULL, 0);
825 r600_pipe_state_add_reg(rstate, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000, NULL, 0);
826 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, NULL, 0);
827 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, NULL, 0);
828 //r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, NULL, 0);
829 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, NULL, 0);
830 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, NULL, 0);
831 r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, NULL, 0);
832 r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, NULL, 0);
833 r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, NULL, 0);
834 r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, NULL, 0);
835 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, NULL, 0);
836 dsa->db_render_override = db_render_override;
837
838 return rstate;
839 }
840
841 static void *evergreen_create_rs_state(struct pipe_context *ctx,
842 const struct pipe_rasterizer_state *state)
843 {
844 struct r600_context *rctx = (struct r600_context *)ctx;
845 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
846 struct r600_pipe_state *rstate;
847 unsigned tmp;
848 unsigned prov_vtx = 1, polygon_dual_mode;
849 unsigned clip_rule;
850 float psize_min, psize_max;
851
852 if (rs == NULL) {
853 return NULL;
854 }
855
856 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
857 state->fill_back != PIPE_POLYGON_MODE_FILL);
858
859 if (state->flatshade_first)
860 prov_vtx = 0;
861
862 rstate = &rs->rstate;
863 rs->flatshade = state->flatshade;
864 rs->sprite_coord_enable = state->sprite_coord_enable;
865 rs->pa_sc_line_stipple = state->line_stipple_enable ?
866 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
867 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
868 rs->pa_su_sc_mode_cntl =
869 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
870 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
871 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
872 S_028814_FACE(!state->front_ccw) |
873 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
874 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
875 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
876 S_028814_POLY_MODE(polygon_dual_mode) |
877 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
878 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
879 rs->pa_cl_clip_cntl =
880 S_028810_PS_UCP_MODE(3) |
881 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
882 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
883 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
884 rs->pa_cl_vs_out_cntl =
885 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
886 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
887
888 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
889
890 /* offset */
891 rs->offset_units = state->offset_units;
892 rs->offset_scale = state->offset_scale * 12.0f;
893
894 rstate->id = R600_PIPE_STATE_RASTERIZER;
895 /* XXX: Flat shading hangs the GPU */
896 tmp = S_0286D4_FLAT_SHADE_ENA(0);
897 if (state->sprite_coord_enable) {
898 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
899 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
900 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
901 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
902 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
903 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
904 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
905 }
906 }
907 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, NULL, 0);
908
909 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, NULL, 0);
910 /* point size 12.4 fixed point */
911 tmp = (unsigned)(state->point_size * 8.0);
912 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), NULL, 0);
913
914 if (state->point_size_per_vertex) {
915 psize_min = util_get_min_point_size(state);
916 psize_max = 8192;
917 } else {
918 /* Force the point size to be as if the vertex output was disabled. */
919 psize_min = state->point_size;
920 psize_max = state->point_size;
921 }
922 /* Divide by two, because 0.5 = 1 pixel. */
923 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
924 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
925 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)),
926 NULL, 0);
927
928 tmp = (unsigned)state->line_width * 8;
929 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), NULL, 0);
930 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
931 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable),
932 NULL, 0);
933
934 r600_pipe_state_add_reg(rstate, R_028BDC_PA_SC_LINE_CNTL, 0x00000400, NULL, 0);
935 r600_pipe_state_add_reg(rstate, R_028BE4_PA_SU_VTX_CNTL,
936 S_028BE4_PIX_CENTER(state->gl_rasterization_rules),
937 NULL, 0);
938 r600_pipe_state_add_reg(rstate, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, NULL, 0);
939 r600_pipe_state_add_reg(rstate, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, NULL, 0);
940 r600_pipe_state_add_reg(rstate, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, NULL, 0);
941 r600_pipe_state_add_reg(rstate, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, NULL, 0);
942
943 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), NULL, 0);
944 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, NULL, 0);
945 return rstate;
946 }
947
948 static void *si_create_sampler_state(struct pipe_context *ctx,
949 const struct pipe_sampler_state *state)
950 {
951 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
952 union util_color uc;
953 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
954 unsigned border_color_type;
955
956 if (rstate == NULL) {
957 return NULL;
958 }
959
960 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
961 switch (uc.ui) {
962 case 0x000000FF:
963 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
964 break;
965 case 0x00000000:
966 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
967 break;
968 case 0xFFFFFFFF:
969 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
970 break;
971 default: /* Use border color pointer */
972 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
973 }
974
975 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
976 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
977 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
978 (state->max_anisotropy & 0x7) << 9 | /* XXX */
979 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
980 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
981 aniso_flag_offset << 16 | /* XXX */
982 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
983 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
984 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
985 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
986 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
987 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
988 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
989 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
990
991 #if 0
992 if (border_color_type == 3) {
993 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0);
994 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0);
995 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0);
996 r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0);
997 }
998 #endif
999 return rstate;
1000 }
1001
1002 static void si_delete_sampler_state(struct pipe_context *ctx,
1003 void *state)
1004 {
1005 free(state);
1006 }
1007
1008 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
1009 struct pipe_resource *texture,
1010 const struct pipe_sampler_view *state)
1011 {
1012 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
1013 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
1014 const struct util_format_description *desc = util_format_description(state->format);
1015 unsigned blocksize = util_format_get_blocksize(tmp->real_format);
1016 unsigned format, num_format, endian, tiling_index;
1017 uint32_t pitch = 0;
1018 unsigned char state_swizzle[4], swizzle[4];
1019 unsigned height, depth, width;
1020 int first_non_void;
1021 uint64_t va;
1022
1023 if (view == NULL)
1024 return NULL;
1025
1026 /* initialize base object */
1027 view->base = *state;
1028 view->base.texture = NULL;
1029 pipe_reference(NULL, &texture->reference);
1030 view->base.texture = texture;
1031 view->base.reference.count = 1;
1032 view->base.context = ctx;
1033
1034 state_swizzle[0] = state->swizzle_r;
1035 state_swizzle[1] = state->swizzle_g;
1036 state_swizzle[2] = state->swizzle_b;
1037 state_swizzle[3] = state->swizzle_a;
1038 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
1039
1040 first_non_void = util_format_get_first_non_void_channel(state->format);
1041 switch (desc->channel[first_non_void].type) {
1042 case UTIL_FORMAT_TYPE_FLOAT:
1043 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
1044 break;
1045 case UTIL_FORMAT_TYPE_SIGNED:
1046 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
1047 break;
1048 case UTIL_FORMAT_TYPE_UNSIGNED:
1049 default:
1050 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
1051 }
1052
1053 format = si_translate_texformat(ctx->screen, state->format, desc, first_non_void);
1054 if (format == ~0) {
1055 format = 0;
1056 }
1057
1058 if (tmp->depth && !tmp->is_flushing_texture) {
1059 r600_texture_depth_flush(ctx, texture, TRUE);
1060 tmp = tmp->flushed_depth_texture;
1061 }
1062
1063 endian = si_colorformat_endian_swap(format);
1064
1065 height = texture->height0;
1066 depth = texture->depth0;
1067 width = texture->width0;
1068 pitch = align(tmp->pitch_in_blocks[0] *
1069 util_format_get_blockwidth(state->format), 8);
1070
1071 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1072 height = 1;
1073 depth = texture->array_size;
1074 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1075 depth = texture->array_size;
1076 }
1077
1078 tiling_index = 8;
1079 switch (tmp->surface.level[state->u.tex.first_level].mode) {
1080 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1081 tiling_index = 8;
1082 break;
1083 case RADEON_SURF_MODE_1D:
1084 tiling_index = 9;
1085 break;
1086 case RADEON_SURF_MODE_2D:
1087 if (tmp->resource.b.b.bind & PIPE_BIND_SCANOUT) {
1088 switch (blocksize) {
1089 case 1:
1090 tiling_index = 10;
1091 break;
1092 case 2:
1093 tiling_index = 11;
1094 break;
1095 case 4:
1096 tiling_index = 12;
1097 break;
1098 }
1099 break;
1100 } else switch (blocksize) {
1101 case 1:
1102 tiling_index = 14;
1103 break;
1104 case 2:
1105 tiling_index = 15;
1106 break;
1107 case 4:
1108 tiling_index = 16;
1109 break;
1110 case 8:
1111 tiling_index = 17;
1112 break;
1113 default:
1114 tiling_index = 13;
1115 }
1116 break;
1117 }
1118
1119 va = r600_resource_va(ctx->screen, texture);
1120 if (state->u.tex.last_level) {
1121 view->state[0] = (va + tmp->offset[1]) >> 8;
1122 } else {
1123 view->state[0] = (va + tmp->offset[0]) >> 8;
1124 }
1125 view->state[1] = (S_008F14_BASE_ADDRESS_HI((va + tmp->offset[0]) >> 40) |
1126 S_008F14_DATA_FORMAT(format) |
1127 S_008F14_NUM_FORMAT(num_format));
1128 view->state[2] = (S_008F18_WIDTH(width - 1) |
1129 S_008F18_HEIGHT(height - 1));
1130 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
1131 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
1132 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
1133 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
1134 S_008F1C_BASE_LEVEL(state->u.tex.first_level) |
1135 S_008F1C_LAST_LEVEL(state->u.tex.last_level) |
1136 S_008F1C_TILING_INDEX(tiling_index) |
1137 S_008F1C_TYPE(si_tex_dim(texture->target)));
1138 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
1139 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
1140 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
1141 view->state[6] = 0;
1142 view->state[7] = 0;
1143
1144 return &view->base;
1145 }
1146
1147 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1148 struct pipe_sampler_view **views)
1149 {
1150 }
1151
1152 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1153 struct pipe_sampler_view **views)
1154 {
1155 struct r600_context *rctx = (struct r600_context *)ctx;
1156 struct si_pipe_sampler_view **resource = (struct si_pipe_sampler_view **)views;
1157 struct r600_pipe_state *rstate = &rctx->ps_samplers.views_state;
1158 struct r600_resource *bo;
1159 int i;
1160 int has_depth = 0;
1161 uint64_t va;
1162 char *ptr;
1163
1164 if (!count)
1165 goto out;
1166
1167 r600_inval_texture_cache(rctx);
1168
1169 bo = (struct r600_resource*)
1170 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
1171 count * sizeof(resource[0]->state));
1172 ptr = rctx->ws->buffer_map(bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
1173
1174 for (i = 0; i < count; i++, ptr += sizeof(resource[0]->state)) {
1175 pipe_sampler_view_reference(
1176 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
1177 views[i]);
1178
1179 if (resource[i]) {
1180 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1181 has_depth = 1;
1182
1183 memcpy(ptr, resource[i]->state, sizeof(resource[0]->state));
1184 } else
1185 memset(ptr, 0, sizeof(resource[0]->state));
1186 }
1187
1188 rctx->ws->buffer_unmap(bo->cs_buf);
1189
1190 for (i = count; i < NUM_TEX_UNITS; i++) {
1191 if (rctx->ps_samplers.views[i])
1192 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
1193 }
1194
1195 rstate->nregs = 0;
1196 va = r600_resource_va(ctx->screen, (void *)bo);
1197 r600_pipe_state_add_reg(rstate, R_00B040_SPI_SHADER_USER_DATA_PS_4, va, bo, RADEON_USAGE_READ);
1198 r600_pipe_state_add_reg(rstate, R_00B044_SPI_SHADER_USER_DATA_PS_5, va >> 32, NULL, 0);
1199 r600_context_pipe_state_set(rctx, rstate);
1200
1201 out:
1202 rctx->have_depth_texture = has_depth;
1203 rctx->ps_samplers.n_views = count;
1204 }
1205
1206 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1207 {
1208 struct r600_context *rctx = (struct r600_context *)ctx;
1209 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
1210 struct r600_pipe_state *rstate = &rctx->ps_samplers.samplers_state;
1211 struct r600_resource *bo;
1212 uint64_t va;
1213 char *ptr;
1214 int i;
1215
1216 if (!count)
1217 goto out;
1218
1219 r600_inval_texture_cache(rctx);
1220
1221 bo = (struct r600_resource*)
1222 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
1223 count * sizeof(rstates[0]->val));
1224 ptr = rctx->ws->buffer_map(bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
1225
1226 for (i = 0; i < count; i++, ptr += sizeof(rstates[0]->val)) {
1227 memcpy(ptr, rstates[i]->val, sizeof(rstates[0]->val));
1228 }
1229
1230 rctx->ws->buffer_unmap(bo->cs_buf);
1231
1232 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
1233
1234 rstate->nregs = 0;
1235 va = r600_resource_va(ctx->screen, (void *)bo);
1236 r600_pipe_state_add_reg(rstate, R_00B038_SPI_SHADER_USER_DATA_PS_2, va, bo, RADEON_USAGE_READ);
1237 r600_pipe_state_add_reg(rstate, R_00B03C_SPI_SHADER_USER_DATA_PS_3, va >> 32, NULL, 0);
1238 r600_context_pipe_state_set(rctx, rstate);
1239
1240 out:
1241 rctx->ps_samplers.n_samplers = count;
1242 }
1243
1244 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1245 {
1246 }
1247
1248 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1249 const struct pipe_poly_stipple *state)
1250 {
1251 }
1252
1253 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1254 {
1255 }
1256
1257 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1258 const struct pipe_scissor_state *state)
1259 {
1260 struct r600_context *rctx = (struct r600_context *)ctx;
1261 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1262 uint32_t tl, br;
1263
1264 if (rstate == NULL)
1265 return;
1266
1267 rstate->id = R600_PIPE_STATE_SCISSOR;
1268 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
1269 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1270 r600_pipe_state_add_reg(rstate,
1271 R_028210_PA_SC_CLIPRECT_0_TL, tl,
1272 NULL, 0);
1273 r600_pipe_state_add_reg(rstate,
1274 R_028214_PA_SC_CLIPRECT_0_BR, br,
1275 NULL, 0);
1276 r600_pipe_state_add_reg(rstate,
1277 R_028218_PA_SC_CLIPRECT_1_TL, tl,
1278 NULL, 0);
1279 r600_pipe_state_add_reg(rstate,
1280 R_02821C_PA_SC_CLIPRECT_1_BR, br,
1281 NULL, 0);
1282 r600_pipe_state_add_reg(rstate,
1283 R_028220_PA_SC_CLIPRECT_2_TL, tl,
1284 NULL, 0);
1285 r600_pipe_state_add_reg(rstate,
1286 R_028224_PA_SC_CLIPRECT_2_BR, br,
1287 NULL, 0);
1288 r600_pipe_state_add_reg(rstate,
1289 R_028228_PA_SC_CLIPRECT_3_TL, tl,
1290 NULL, 0);
1291 r600_pipe_state_add_reg(rstate,
1292 R_02822C_PA_SC_CLIPRECT_3_BR, br,
1293 NULL, 0);
1294
1295 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1296 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1297 r600_context_pipe_state_set(rctx, rstate);
1298 }
1299
1300 static void evergreen_set_viewport_state(struct pipe_context *ctx,
1301 const struct pipe_viewport_state *state)
1302 {
1303 struct r600_context *rctx = (struct r600_context *)ctx;
1304 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1305
1306 if (rstate == NULL)
1307 return;
1308
1309 rctx->viewport = *state;
1310 rstate->id = R600_PIPE_STATE_VIEWPORT;
1311 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, NULL, 0);
1312 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, NULL, 0);
1313 r600_pipe_state_add_reg(rstate, R_028350_PA_SC_RASTER_CONFIG, 0x00000000, NULL, 0);
1314 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), NULL, 0);
1315 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), NULL, 0);
1316 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), NULL, 0);
1317 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), NULL, 0);
1318 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), NULL, 0);
1319 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), NULL, 0);
1320 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, NULL, 0);
1321
1322 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1323 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1324 r600_context_pipe_state_set(rctx, rstate);
1325 }
1326
1327 static void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
1328 const struct pipe_framebuffer_state *state, int cb)
1329 {
1330 struct r600_resource_texture *rtex;
1331 struct r600_surface *surf;
1332 unsigned level = state->cbufs[cb]->u.tex.level;
1333 unsigned pitch, slice;
1334 unsigned color_info, color_attrib;
1335 unsigned format, swap, ntype, endian;
1336 uint64_t offset;
1337 unsigned blocksize;
1338 const struct util_format_description *desc;
1339 int i;
1340 unsigned blend_clamp = 0, blend_bypass = 0;
1341
1342 surf = (struct r600_surface *)state->cbufs[cb];
1343 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1344 blocksize = util_format_get_blocksize(rtex->real_format);
1345
1346 if (rtex->depth)
1347 rctx->have_depth_fb = TRUE;
1348
1349 if (rtex->depth && !rtex->is_flushing_texture) {
1350 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1351 rtex = rtex->flushed_depth_texture;
1352 }
1353
1354 offset = rtex->surface.level[level].offset;
1355 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1356 offset += rtex->surface.level[level].slice_size *
1357 state->cbufs[cb]->u.tex.first_layer;
1358 }
1359 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1360 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1361 if (slice) {
1362 slice = slice - 1;
1363 }
1364
1365 color_attrib = S_028C74_TILE_MODE_INDEX(8);
1366 switch (rtex->surface.level[level].mode) {
1367 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1368 color_attrib = S_028C74_TILE_MODE_INDEX(8);
1369 break;
1370 case RADEON_SURF_MODE_1D:
1371 color_attrib = S_028C74_TILE_MODE_INDEX(9);
1372 break;
1373 case RADEON_SURF_MODE_2D:
1374 if (rtex->resource.b.b.bind & PIPE_BIND_SCANOUT) {
1375 switch (blocksize) {
1376 case 1:
1377 color_attrib = S_028C74_TILE_MODE_INDEX(10);
1378 break;
1379 case 2:
1380 color_attrib = S_028C74_TILE_MODE_INDEX(11);
1381 break;
1382 case 4:
1383 color_attrib = S_028C74_TILE_MODE_INDEX(12);
1384 break;
1385 }
1386 break;
1387 } else switch (blocksize) {
1388 case 1:
1389 color_attrib = S_028C74_TILE_MODE_INDEX(14);
1390 break;
1391 case 2:
1392 color_attrib = S_028C74_TILE_MODE_INDEX(15);
1393 break;
1394 case 4:
1395 color_attrib = S_028C74_TILE_MODE_INDEX(16);
1396 break;
1397 case 8:
1398 color_attrib = S_028C74_TILE_MODE_INDEX(17);
1399 break;
1400 default:
1401 color_attrib = S_028C74_TILE_MODE_INDEX(13);
1402 }
1403 break;
1404 }
1405
1406 desc = util_format_description(surf->base.format);
1407 for (i = 0; i < 4; i++) {
1408 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1409 break;
1410 }
1411 }
1412 if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1413 ntype = V_028C70_NUMBER_FLOAT;
1414 } else {
1415 ntype = V_028C70_NUMBER_UNORM;
1416 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1417 ntype = V_028C70_NUMBER_SRGB;
1418 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1419 if (desc->channel[i].normalized)
1420 ntype = V_028C70_NUMBER_SNORM;
1421 else if (desc->channel[i].pure_integer)
1422 ntype = V_028C70_NUMBER_SINT;
1423 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1424 if (desc->channel[i].normalized)
1425 ntype = V_028C70_NUMBER_UNORM;
1426 else if (desc->channel[i].pure_integer)
1427 ntype = V_028C70_NUMBER_UINT;
1428 }
1429 }
1430
1431 format = si_translate_colorformat(surf->base.format);
1432 swap = si_translate_colorswap(surf->base.format);
1433 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1434 endian = V_028C70_ENDIAN_NONE;
1435 } else {
1436 endian = si_colorformat_endian_swap(format);
1437 }
1438
1439 /* blend clamp should be set for all NORM/SRGB types */
1440 if (ntype == V_028C70_NUMBER_UNORM ||
1441 ntype == V_028C70_NUMBER_SNORM ||
1442 ntype == V_028C70_NUMBER_SRGB)
1443 blend_clamp = 1;
1444
1445 /* set blend bypass according to docs if SINT/UINT or
1446 8/24 COLOR variants */
1447 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1448 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1449 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1450 blend_clamp = 0;
1451 blend_bypass = 1;
1452 }
1453
1454 color_info = S_028C70_FORMAT(format) |
1455 S_028C70_COMP_SWAP(swap) |
1456 S_028C70_BLEND_CLAMP(blend_clamp) |
1457 S_028C70_BLEND_BYPASS(blend_bypass) |
1458 S_028C70_NUMBER_TYPE(ntype) |
1459 S_028C70_ENDIAN(endian);
1460
1461 rctx->alpha_ref_dirty = true;
1462
1463 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1464 offset >>= 8;
1465
1466 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1467 r600_pipe_state_add_reg(rstate,
1468 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
1469 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1470 r600_pipe_state_add_reg(rstate,
1471 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
1472 S_028C64_TILE_MAX(pitch),
1473 NULL, 0);
1474 r600_pipe_state_add_reg(rstate,
1475 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
1476 S_028C68_TILE_MAX(slice),
1477 NULL, 0);
1478 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1479 r600_pipe_state_add_reg(rstate,
1480 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1481 0x00000000, NULL, 0);
1482 } else {
1483 r600_pipe_state_add_reg(rstate,
1484 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1485 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1486 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer),
1487 NULL, 0);
1488 }
1489 r600_pipe_state_add_reg(rstate,
1490 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
1491 color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1492 r600_pipe_state_add_reg(rstate,
1493 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
1494 color_attrib,
1495 &rtex->resource, RADEON_USAGE_READWRITE);
1496 }
1497
1498 static void si_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
1499 const struct pipe_framebuffer_state *state)
1500 {
1501 struct r600_resource_texture *rtex;
1502 struct r600_surface *surf;
1503 unsigned level, first_layer, pitch, slice, format;
1504 uint32_t db_z_info, stencil_info;
1505 uint64_t offset;
1506
1507 if (state->zsbuf == NULL) {
1508 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO, 0, NULL, 0);
1509 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO, 0, NULL, 0);
1510 return;
1511 }
1512
1513 surf = (struct r600_surface *)state->zsbuf;
1514 level = surf->base.u.tex.level;
1515 rtex = (struct r600_resource_texture*)surf->base.texture;
1516
1517 first_layer = surf->base.u.tex.first_layer;
1518 format = si_translate_dbformat(rtex->real_format);
1519
1520 offset = r600_resource_va(rctx->context.screen, surf->base.texture);
1521 offset += rtex->surface.level[level].offset;
1522 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1523 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1524 if (slice) {
1525 slice = slice - 1;
1526 }
1527 offset >>= 8;
1528
1529 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
1530 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1531 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
1532 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1533 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1534 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1535 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer),
1536 NULL, 0);
1537
1538 db_z_info = S_028040_FORMAT(format);
1539 stencil_info = S_028044_FORMAT(rtex->stencil != 0);
1540
1541 switch (format) {
1542 case V_028040_Z_16:
1543 db_z_info |= S_028040_TILE_MODE_INDEX(5);
1544 stencil_info |= S_028044_TILE_MODE_INDEX(5);
1545 break;
1546 case V_028040_Z_24:
1547 case V_028040_Z_32_FLOAT:
1548 db_z_info |= S_028040_TILE_MODE_INDEX(6);
1549 stencil_info |= S_028044_TILE_MODE_INDEX(6);
1550 break;
1551 default:
1552 db_z_info |= S_028040_TILE_MODE_INDEX(7);
1553 stencil_info |= S_028044_TILE_MODE_INDEX(7);
1554 }
1555
1556 if (rtex->stencil) {
1557 uint64_t stencil_offset =
1558 r600_texture_get_offset(rtex->stencil, level, first_layer);
1559
1560 stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil);
1561 stencil_offset >>= 8;
1562
1563 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1564 stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1565 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1566 stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1567 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1568 stencil_info, NULL, 0);
1569 } else {
1570 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1571 0, NULL, 0);
1572 }
1573
1574 if (format != ~0U) {
1575 r600_pipe_state_add_reg(rstate, R_02803C_DB_DEPTH_INFO, 0x1, NULL, 0);
1576 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO, db_z_info, NULL, 0);
1577 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
1578 S_028058_PITCH_TILE_MAX(pitch),
1579 NULL, 0);
1580 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
1581 S_02805C_SLICE_TILE_MAX(slice),
1582 NULL, 0);
1583
1584 } else {
1585 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO, 0, NULL, 0);
1586 }
1587 }
1588
1589 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1590 const struct pipe_framebuffer_state *state)
1591 {
1592 struct r600_context *rctx = (struct r600_context *)ctx;
1593 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1594 uint32_t shader_mask, tl, br;
1595 int tl_x, tl_y, br_x, br_y;
1596
1597 if (rstate == NULL)
1598 return;
1599
1600 r600_flush_framebuffer(rctx, false);
1601
1602 /* unreference old buffer and reference new one */
1603 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1604
1605 util_copy_framebuffer_state(&rctx->framebuffer, state);
1606
1607 /* build states */
1608 rctx->have_depth_fb = 0;
1609 rctx->nr_cbufs = state->nr_cbufs;
1610 for (int i = 0; i < state->nr_cbufs; i++) {
1611 evergreen_cb(rctx, rstate, state, i);
1612 }
1613 si_db(rctx, rstate, state);
1614
1615 shader_mask = 0;
1616 for (int i = 0; i < state->nr_cbufs; i++) {
1617 shader_mask |= 0xf << (i * 4);
1618 }
1619 tl_x = 0;
1620 tl_y = 0;
1621 br_x = state->width;
1622 br_y = state->height;
1623 #if 0 /* These shouldn't be necessary on SI, see PA_SC_ENHANCE register */
1624 /* EG hw workaround */
1625 if (br_x == 0)
1626 tl_x = 1;
1627 if (br_y == 0)
1628 tl_y = 1;
1629 /* cayman hw workaround */
1630 if (rctx->chip_class == CAYMAN) {
1631 if (br_x == 1 && br_y == 1)
1632 br_x = 2;
1633 }
1634 #endif
1635 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1636 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1637
1638 r600_pipe_state_add_reg(rstate,
1639 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1640 NULL, 0);
1641 r600_pipe_state_add_reg(rstate,
1642 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1643 NULL, 0);
1644 r600_pipe_state_add_reg(rstate,
1645 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1646 NULL, 0);
1647 r600_pipe_state_add_reg(rstate,
1648 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1649 NULL, 0);
1650 r600_pipe_state_add_reg(rstate,
1651 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1652 NULL, 0);
1653 r600_pipe_state_add_reg(rstate,
1654 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1655 NULL, 0);
1656 r600_pipe_state_add_reg(rstate,
1657 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1658 NULL, 0);
1659 r600_pipe_state_add_reg(rstate,
1660 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1661 NULL, 0);
1662 r600_pipe_state_add_reg(rstate,
1663 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1664 NULL, 0);
1665 r600_pipe_state_add_reg(rstate,
1666 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1667 NULL, 0);
1668
1669 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1670 shader_mask, NULL, 0);
1671
1672 r600_pipe_state_add_reg(rstate, R_028BE0_PA_SC_AA_CONFIG,
1673 0x00000000, NULL, 0);
1674
1675 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1676 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1677 r600_context_pipe_state_set(rctx, rstate);
1678
1679 if (state->zsbuf) {
1680 cayman_polygon_offset_update(rctx);
1681 }
1682 }
1683
1684 void cayman_init_state_functions(struct r600_context *rctx)
1685 {
1686 si_init_state_functions(rctx);
1687 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1688 rctx->context.create_fs_state = si_create_shader_state;
1689 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1690 rctx->context.create_sampler_state = si_create_sampler_state;
1691 rctx->context.create_sampler_view = evergreen_create_sampler_view;
1692 rctx->context.create_vertex_elements_state = si_create_vertex_elements;
1693 rctx->context.create_vs_state = si_create_shader_state;
1694 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1695 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1696 rctx->context.bind_fs_state = r600_bind_ps_shader;
1697 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1698 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1699 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1700 rctx->context.bind_vs_state = r600_bind_vs_shader;
1701 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1702 rctx->context.delete_fs_state = r600_delete_ps_shader;
1703 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1704 rctx->context.delete_sampler_state = si_delete_sampler_state;
1705 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1706 rctx->context.delete_vs_state = r600_delete_vs_shader;
1707 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1708 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1709 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1710 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1711 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1712 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1713 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1714 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1715 rctx->context.set_index_buffer = r600_set_index_buffer;
1716 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1717 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1718 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1719 rctx->context.texture_barrier = r600_texture_barrier;
1720 rctx->context.create_stream_output_target = r600_create_so_target;
1721 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1722 rctx->context.set_stream_output_targets = r600_set_so_targets;
1723 }
1724
1725 void si_init_config(struct r600_context *rctx)
1726 {
1727 struct r600_pipe_state *rstate = &rctx->config;
1728 unsigned tmp;
1729
1730 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, NULL, 0);
1731
1732 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, NULL, 0);
1733 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, NULL, 0);
1734 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, NULL, 0);
1735 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, NULL, 0);
1736 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, NULL, 0);
1737 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, NULL, 0);
1738 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, NULL, 0);
1739 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, NULL, 0);
1740 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, NULL, 0);
1741 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, NULL, 0);
1742 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, NULL, 0);
1743 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, NULL, 0);
1744 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, NULL, 0);
1745 r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x0, NULL, 0);
1746 r600_pipe_state_add_reg(rstate, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0, NULL, 0);
1747 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, NULL, 0);
1748 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, NULL, 0);
1749 r600_pipe_state_add_reg(rstate, R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63), NULL, 0);
1750 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, NULL, 0);
1751 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, NULL, 0);
1752 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, NULL, 0);
1753
1754 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, NULL, 0);
1755
1756 r600_pipe_state_add_reg(rstate, R_028B54_VGT_SHADER_STAGES_EN, 0, NULL, 0);
1757 r600_pipe_state_add_reg(rstate, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210, NULL, 0);
1758 r600_pipe_state_add_reg(rstate, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98, NULL, 0);
1759
1760 r600_pipe_state_add_reg(rstate, R_028804_DB_EQAA, 0x110000, NULL, 0);
1761 r600_context_pipe_state_set(rctx, rstate);
1762 }
1763
1764 void cayman_polygon_offset_update(struct r600_context *rctx)
1765 {
1766 struct r600_pipe_state state;
1767
1768 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
1769 state.nregs = 0;
1770 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
1771 float offset_units = rctx->rasterizer->offset_units;
1772 unsigned offset_db_fmt_cntl = 0, depth;
1773
1774 switch (rctx->framebuffer.zsbuf->texture->format) {
1775 case PIPE_FORMAT_Z24X8_UNORM:
1776 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1777 depth = -24;
1778 offset_units *= 2.0f;
1779 break;
1780 case PIPE_FORMAT_Z32_FLOAT:
1781 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1782 depth = -23;
1783 offset_units *= 1.0f;
1784 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1785 break;
1786 case PIPE_FORMAT_Z16_UNORM:
1787 depth = -16;
1788 offset_units *= 4.0f;
1789 break;
1790 default:
1791 return;
1792 }
1793 /* FIXME some of those reg can be computed with cso */
1794 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
1795 r600_pipe_state_add_reg(&state,
1796 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1797 fui(rctx->rasterizer->offset_scale), NULL, 0);
1798 r600_pipe_state_add_reg(&state,
1799 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1800 fui(offset_units), NULL, 0);
1801 r600_pipe_state_add_reg(&state,
1802 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1803 fui(rctx->rasterizer->offset_scale), NULL, 0);
1804 r600_pipe_state_add_reg(&state,
1805 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1806 fui(offset_units), NULL, 0);
1807 r600_pipe_state_add_reg(&state,
1808 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1809 offset_db_fmt_cntl, NULL, 0);
1810 r600_context_pipe_state_set(rctx, &state);
1811 }
1812 }
1813
1814 void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader)
1815 {
1816 struct r600_context *rctx = (struct r600_context *)ctx;
1817 struct r600_pipe_state *rstate = &shader->rstate;
1818 struct r600_shader *rshader = &shader->shader;
1819 unsigned i, exports_ps, num_cout, spi_ps_in_control, db_shader_control;
1820 unsigned num_sgprs, num_user_sgprs;
1821 int pos_index = -1, face_index = -1;
1822 int ninterp = 0;
1823 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
1824 unsigned spi_baryc_cntl;
1825 uint64_t va;
1826
1827 if (si_pipe_shader_create(ctx, shader))
1828 return;
1829
1830 rstate->nregs = 0;
1831
1832 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
1833 for (i = 0; i < rshader->ninput; i++) {
1834 ninterp++;
1835 /* XXX: Flat shading hangs the GPU */
1836 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
1837 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
1838 rctx->rasterizer->flatshade))
1839 have_linear = TRUE;
1840 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
1841 have_linear = TRUE;
1842 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
1843 have_perspective = TRUE;
1844 if (rshader->input[i].centroid)
1845 have_centroid = TRUE;
1846 }
1847
1848 for (i = 0; i < rshader->noutput; i++) {
1849 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1850 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
1851 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1852 db_shader_control |= 0; // XXX OP_VAL or TEST_VAL?
1853 }
1854 if (rshader->uses_kill)
1855 db_shader_control |= S_02880C_KILL_ENABLE(1);
1856
1857 exports_ps = 0;
1858 num_cout = 0;
1859 for (i = 0; i < rshader->noutput; i++) {
1860 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
1861 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1862 exports_ps |= 1;
1863 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
1864 if (rshader->fs_write_all)
1865 num_cout = rshader->nr_cbufs;
1866 else
1867 num_cout++;
1868 }
1869 }
1870 if (!exports_ps) {
1871 /* always at least export 1 component per pixel */
1872 exports_ps = 2;
1873 }
1874
1875 spi_ps_in_control = S_0286D8_NUM_INTERP(ninterp);
1876
1877 spi_baryc_cntl = 0;
1878 if (have_perspective)
1879 spi_baryc_cntl |= have_centroid ?
1880 S_0286E0_PERSP_CENTROID_CNTL(1) : S_0286E0_PERSP_CENTER_CNTL(1);
1881 if (have_linear)
1882 spi_baryc_cntl |= have_centroid ?
1883 S_0286E0_LINEAR_CENTROID_CNTL(1) : S_0286E0_LINEAR_CENTER_CNTL(1);
1884
1885 r600_pipe_state_add_reg(rstate,
1886 R_0286E0_SPI_BARYC_CNTL,
1887 spi_baryc_cntl,
1888 NULL, 0);
1889
1890 r600_pipe_state_add_reg(rstate,
1891 R_0286CC_SPI_PS_INPUT_ENA,
1892 shader->spi_ps_input_ena,
1893 NULL, 0);
1894
1895 r600_pipe_state_add_reg(rstate,
1896 R_0286D0_SPI_PS_INPUT_ADDR,
1897 shader->spi_ps_input_ena,
1898 NULL, 0);
1899
1900 r600_pipe_state_add_reg(rstate,
1901 R_0286D8_SPI_PS_IN_CONTROL,
1902 spi_ps_in_control,
1903 NULL, 0);
1904
1905 /* XXX: Depends on Z buffer format? */
1906 r600_pipe_state_add_reg(rstate,
1907 R_028710_SPI_SHADER_Z_FORMAT,
1908 0,
1909 NULL, 0);
1910
1911 /* XXX: Depends on color buffer format? */
1912 r600_pipe_state_add_reg(rstate,
1913 R_028714_SPI_SHADER_COL_FORMAT,
1914 S_028714_COL0_EXPORT_FORMAT(V_028714_SPI_SHADER_32_ABGR),
1915 NULL, 0);
1916
1917 va = r600_resource_va(ctx->screen, (void *)shader->bo);
1918 r600_pipe_state_add_reg(rstate,
1919 R_00B020_SPI_SHADER_PGM_LO_PS,
1920 va >> 8,
1921 shader->bo, RADEON_USAGE_READ);
1922 r600_pipe_state_add_reg(rstate,
1923 R_00B024_SPI_SHADER_PGM_HI_PS,
1924 va >> 40,
1925 shader->bo, RADEON_USAGE_READ);
1926
1927 num_user_sgprs = 6;
1928 num_sgprs = shader->num_sgprs;
1929 if (num_user_sgprs > num_sgprs)
1930 num_sgprs = num_user_sgprs;
1931 /* Last 2 reserved SGPRs are used for VCC */
1932 num_sgprs += 2;
1933 assert(num_sgprs <= 104);
1934
1935 r600_pipe_state_add_reg(rstate,
1936 R_00B028_SPI_SHADER_PGM_RSRC1_PS,
1937 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
1938 S_00B028_SGPRS((num_sgprs - 1) / 8),
1939 NULL, 0);
1940 r600_pipe_state_add_reg(rstate,
1941 R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1942 S_00B02C_USER_SGPR(num_user_sgprs),
1943 NULL, 0);
1944
1945 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
1946 db_shader_control,
1947 NULL, 0);
1948
1949 shader->sprite_coord_enable = rctx->sprite_coord_enable;
1950 }
1951
1952 void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader)
1953 {
1954 struct r600_context *rctx = (struct r600_context *)ctx;
1955 struct r600_pipe_state *rstate = &shader->rstate;
1956 struct r600_shader *rshader = &shader->shader;
1957 unsigned num_sgprs, num_user_sgprs;
1958 unsigned nparams, i;
1959 uint64_t va;
1960
1961 if (si_pipe_shader_create(ctx, shader))
1962 return;
1963
1964 /* clear previous register */
1965 rstate->nregs = 0;
1966
1967 /* Certain attributes (position, psize, etc.) don't count as params.
1968 * VS is required to export at least one param and r600_shader_from_tgsi()
1969 * takes care of adding a dummy export.
1970 */
1971 for (nparams = 0, i = 0 ; i < rshader->noutput; i++) {
1972 if (rshader->output[i].name != TGSI_SEMANTIC_POSITION)
1973 nparams++;
1974 }
1975 if (nparams < 1)
1976 nparams = 1;
1977
1978 r600_pipe_state_add_reg(rstate,
1979 R_0286C4_SPI_VS_OUT_CONFIG,
1980 S_0286C4_VS_EXPORT_COUNT(nparams - 1),
1981 NULL, 0);
1982
1983 r600_pipe_state_add_reg(rstate,
1984 R_02870C_SPI_SHADER_POS_FORMAT,
1985 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1986 S_02870C_POS1_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE) |
1987 S_02870C_POS2_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE) |
1988 S_02870C_POS3_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE),
1989 NULL, 0);
1990
1991 va = r600_resource_va(ctx->screen, (void *)shader->bo);
1992 r600_pipe_state_add_reg(rstate,
1993 R_00B120_SPI_SHADER_PGM_LO_VS,
1994 va >> 8,
1995 shader->bo, RADEON_USAGE_READ);
1996 r600_pipe_state_add_reg(rstate,
1997 R_00B124_SPI_SHADER_PGM_HI_VS,
1998 va >> 40,
1999 shader->bo, RADEON_USAGE_READ);
2000
2001 num_user_sgprs = 8;
2002 num_sgprs = shader->num_sgprs;
2003 if (num_user_sgprs > num_sgprs)
2004 num_sgprs = num_user_sgprs;
2005 /* Last 2 reserved SGPRs are used for VCC */
2006 num_sgprs += 2;
2007 assert(num_sgprs <= 104);
2008
2009 r600_pipe_state_add_reg(rstate,
2010 R_00B128_SPI_SHADER_PGM_RSRC1_VS,
2011 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
2012 S_00B128_SGPRS((num_sgprs - 1) / 8),
2013 NULL, 0);
2014 r600_pipe_state_add_reg(rstate,
2015 R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
2016 S_00B12C_USER_SGPR(num_user_sgprs),
2017 NULL, 0);
2018 }
2019
2020 void si_update_spi_map(struct r600_context *rctx)
2021 {
2022 struct r600_shader *ps = &rctx->ps_shader->shader;
2023 struct r600_shader *vs = &rctx->vs_shader->shader;
2024 struct r600_pipe_state *rstate = &rctx->spi;
2025 unsigned i, j, tmp;
2026
2027 rstate->nregs = 0;
2028
2029 for (i = 0; i < ps->ninput; i++) {
2030 tmp = 0;
2031
2032 #if 0
2033 /* XXX: Flat shading hangs the GPU */
2034 if (ps->input[i].name == TGSI_SEMANTIC_POSITION ||
2035 ps->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2036 (ps->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2037 rctx->rasterizer && rctx->rasterizer->flatshade)) {
2038 tmp |= S_028644_FLAT_SHADE(1);
2039 }
2040 #endif
2041
2042 if (ps->input[i].name == TGSI_SEMANTIC_GENERIC &&
2043 rctx->sprite_coord_enable & (1 << ps->input[i].sid)) {
2044 tmp |= S_028644_PT_SPRITE_TEX(1);
2045 }
2046
2047 for (j = 0; j < vs->noutput; j++) {
2048 if (ps->input[i].name == vs->output[j].name &&
2049 ps->input[i].sid == vs->output[j].sid) {
2050 tmp |= S_028644_OFFSET(vs->output[j].param_offset);
2051 break;
2052 }
2053 }
2054
2055 if (j == vs->noutput) {
2056 /* No corresponding output found, load defaults into input */
2057 tmp |= S_028644_OFFSET(0x20);
2058 }
2059
2060 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2061 tmp, NULL, 0);
2062 }
2063
2064 if (rstate->nregs > 0)
2065 r600_context_pipe_state_set(rctx, rstate);
2066 }
2067
2068 void *cayman_create_db_flush_dsa(struct r600_context *rctx)
2069 {
2070 struct pipe_depth_stencil_alpha_state dsa;
2071 struct r600_pipe_state *rstate;
2072
2073 memset(&dsa, 0, sizeof(dsa));
2074
2075 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2076 r600_pipe_state_add_reg(rstate,
2077 R_028000_DB_RENDER_CONTROL,
2078 S_028000_DEPTH_COPY(1) |
2079 S_028000_STENCIL_COPY(1) |
2080 S_028000_COPY_CENTROID(1),
2081 NULL, 0);
2082 return rstate;
2083 }