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gallium: add void *user_buffer in pipe_index_buffer
[mesa.git] / src / gallium / drivers / radeonsi / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include "pipe/p_defines.h"
30 #include "pipe/p_state.h"
31 #include "pipe/p_context.h"
32 #include "tgsi/tgsi_scan.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_util.h"
35 #include "util/u_blitter.h"
36 #include "util/u_double_list.h"
37 #include "util/u_transfer.h"
38 #include "util/u_surface.h"
39 #include "util/u_pack_color.h"
40 #include "util/u_memory.h"
41 #include "util/u_inlines.h"
42 #include "util/u_framebuffer.h"
43 #include "pipebuffer/pb_buffer.h"
44 #include "r600.h"
45 #include "sid.h"
46 #include "r600_resource.h"
47 #include "radeonsi_pipe.h"
48
49 static uint32_t si_translate_blend_function(int blend_func)
50 {
51 switch (blend_func) {
52 case PIPE_BLEND_ADD:
53 return V_028780_COMB_DST_PLUS_SRC;
54 case PIPE_BLEND_SUBTRACT:
55 return V_028780_COMB_SRC_MINUS_DST;
56 case PIPE_BLEND_REVERSE_SUBTRACT:
57 return V_028780_COMB_DST_MINUS_SRC;
58 case PIPE_BLEND_MIN:
59 return V_028780_COMB_MIN_DST_SRC;
60 case PIPE_BLEND_MAX:
61 return V_028780_COMB_MAX_DST_SRC;
62 default:
63 R600_ERR("Unknown blend function %d\n", blend_func);
64 assert(0);
65 break;
66 }
67 return 0;
68 }
69
70 static uint32_t si_translate_blend_factor(int blend_fact)
71 {
72 switch (blend_fact) {
73 case PIPE_BLENDFACTOR_ONE:
74 return V_028780_BLEND_ONE;
75 case PIPE_BLENDFACTOR_SRC_COLOR:
76 return V_028780_BLEND_SRC_COLOR;
77 case PIPE_BLENDFACTOR_SRC_ALPHA:
78 return V_028780_BLEND_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_DST_ALPHA:
80 return V_028780_BLEND_DST_ALPHA;
81 case PIPE_BLENDFACTOR_DST_COLOR:
82 return V_028780_BLEND_DST_COLOR;
83 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
84 return V_028780_BLEND_SRC_ALPHA_SATURATE;
85 case PIPE_BLENDFACTOR_CONST_COLOR:
86 return V_028780_BLEND_CONSTANT_COLOR;
87 case PIPE_BLENDFACTOR_CONST_ALPHA:
88 return V_028780_BLEND_CONSTANT_ALPHA;
89 case PIPE_BLENDFACTOR_ZERO:
90 return V_028780_BLEND_ZERO;
91 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
92 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
94 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
95 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
96 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
97 case PIPE_BLENDFACTOR_INV_DST_COLOR:
98 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
99 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
100 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
101 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
102 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
103 case PIPE_BLENDFACTOR_SRC1_COLOR:
104 return V_028780_BLEND_SRC1_COLOR;
105 case PIPE_BLENDFACTOR_SRC1_ALPHA:
106 return V_028780_BLEND_SRC1_ALPHA;
107 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
108 return V_028780_BLEND_INV_SRC1_COLOR;
109 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
110 return V_028780_BLEND_INV_SRC1_ALPHA;
111 default:
112 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
113 assert(0);
114 break;
115 }
116 return 0;
117 }
118
119 #if 0
120 static uint32_t r600_translate_stencil_op(int s_op)
121 {
122 switch (s_op) {
123 case PIPE_STENCIL_OP_KEEP:
124 return V_028800_STENCIL_KEEP;
125 case PIPE_STENCIL_OP_ZERO:
126 return V_028800_STENCIL_ZERO;
127 case PIPE_STENCIL_OP_REPLACE:
128 return V_028800_STENCIL_REPLACE;
129 case PIPE_STENCIL_OP_INCR:
130 return V_028800_STENCIL_INCR;
131 case PIPE_STENCIL_OP_DECR:
132 return V_028800_STENCIL_DECR;
133 case PIPE_STENCIL_OP_INCR_WRAP:
134 return V_028800_STENCIL_INCR_WRAP;
135 case PIPE_STENCIL_OP_DECR_WRAP:
136 return V_028800_STENCIL_DECR_WRAP;
137 case PIPE_STENCIL_OP_INVERT:
138 return V_028800_STENCIL_INVERT;
139 default:
140 R600_ERR("Unknown stencil op %d", s_op);
141 assert(0);
142 break;
143 }
144 return 0;
145 }
146 #endif
147
148 static uint32_t si_translate_fill(uint32_t func)
149 {
150 switch(func) {
151 case PIPE_POLYGON_MODE_FILL:
152 return V_028814_X_DRAW_TRIANGLES;
153 case PIPE_POLYGON_MODE_LINE:
154 return V_028814_X_DRAW_LINES;
155 case PIPE_POLYGON_MODE_POINT:
156 return V_028814_X_DRAW_POINTS;
157 default:
158 assert(0);
159 return V_028814_X_DRAW_POINTS;
160 }
161 }
162
163 /* translates straight */
164 static uint32_t si_translate_ds_func(int func)
165 {
166 return func;
167 }
168
169 static unsigned si_tex_wrap(unsigned wrap)
170 {
171 switch (wrap) {
172 default:
173 case PIPE_TEX_WRAP_REPEAT:
174 return V_008F30_SQ_TEX_WRAP;
175 case PIPE_TEX_WRAP_CLAMP:
176 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
177 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
178 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
179 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
180 return V_008F30_SQ_TEX_CLAMP_BORDER;
181 case PIPE_TEX_WRAP_MIRROR_REPEAT:
182 return V_008F30_SQ_TEX_MIRROR;
183 case PIPE_TEX_WRAP_MIRROR_CLAMP:
184 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
185 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
186 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
187 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
188 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
189 }
190 }
191
192 static unsigned si_tex_filter(unsigned filter)
193 {
194 switch (filter) {
195 default:
196 case PIPE_TEX_FILTER_NEAREST:
197 return V_008F38_SQ_TEX_XY_FILTER_POINT;
198 case PIPE_TEX_FILTER_LINEAR:
199 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
200 }
201 }
202
203 static unsigned si_tex_mipfilter(unsigned filter)
204 {
205 switch (filter) {
206 case PIPE_TEX_MIPFILTER_NEAREST:
207 return V_008F38_SQ_TEX_Z_FILTER_POINT;
208 case PIPE_TEX_MIPFILTER_LINEAR:
209 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
210 default:
211 case PIPE_TEX_MIPFILTER_NONE:
212 return V_008F38_SQ_TEX_Z_FILTER_NONE;
213 }
214 }
215
216 static unsigned si_tex_compare(unsigned compare)
217 {
218 switch (compare) {
219 default:
220 case PIPE_FUNC_NEVER:
221 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
222 case PIPE_FUNC_LESS:
223 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
224 case PIPE_FUNC_EQUAL:
225 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
226 case PIPE_FUNC_LEQUAL:
227 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
228 case PIPE_FUNC_GREATER:
229 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
230 case PIPE_FUNC_NOTEQUAL:
231 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
232 case PIPE_FUNC_GEQUAL:
233 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
234 case PIPE_FUNC_ALWAYS:
235 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
236 }
237 }
238
239 static unsigned si_tex_dim(unsigned dim)
240 {
241 switch (dim) {
242 default:
243 case PIPE_TEXTURE_1D:
244 return V_008F1C_SQ_RSRC_IMG_1D;
245 case PIPE_TEXTURE_1D_ARRAY:
246 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
247 case PIPE_TEXTURE_2D:
248 case PIPE_TEXTURE_RECT:
249 return V_008F1C_SQ_RSRC_IMG_2D;
250 case PIPE_TEXTURE_2D_ARRAY:
251 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
252 case PIPE_TEXTURE_3D:
253 return V_008F1C_SQ_RSRC_IMG_3D;
254 case PIPE_TEXTURE_CUBE:
255 return V_008F1C_SQ_RSRC_IMG_CUBE;
256 }
257 }
258
259 static uint32_t si_translate_dbformat(enum pipe_format format)
260 {
261 switch (format) {
262 case PIPE_FORMAT_Z16_UNORM:
263 return V_028040_Z_16;
264 case PIPE_FORMAT_Z24X8_UNORM:
265 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
266 return V_028040_Z_24; /* XXX no longer supported on SI */
267 case PIPE_FORMAT_Z32_FLOAT:
268 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
269 return V_028040_Z_32_FLOAT;
270 default:
271 return ~0U;
272 }
273 }
274
275 static uint32_t si_translate_colorswap(enum pipe_format format)
276 {
277 switch (format) {
278 /* 8-bit buffers. */
279 case PIPE_FORMAT_L4A4_UNORM:
280 case PIPE_FORMAT_A4R4_UNORM:
281 return V_028C70_SWAP_ALT;
282
283 case PIPE_FORMAT_A8_UNORM:
284 case PIPE_FORMAT_A8_UINT:
285 case PIPE_FORMAT_A8_SINT:
286 case PIPE_FORMAT_R4A4_UNORM:
287 return V_028C70_SWAP_ALT_REV;
288 case PIPE_FORMAT_I8_UNORM:
289 case PIPE_FORMAT_L8_UNORM:
290 case PIPE_FORMAT_I8_UINT:
291 case PIPE_FORMAT_I8_SINT:
292 case PIPE_FORMAT_L8_UINT:
293 case PIPE_FORMAT_L8_SINT:
294 case PIPE_FORMAT_L8_SRGB:
295 case PIPE_FORMAT_R8_UNORM:
296 case PIPE_FORMAT_R8_SNORM:
297 case PIPE_FORMAT_R8_UINT:
298 case PIPE_FORMAT_R8_SINT:
299 return V_028C70_SWAP_STD;
300
301 /* 16-bit buffers. */
302 case PIPE_FORMAT_B5G6R5_UNORM:
303 return V_028C70_SWAP_STD_REV;
304
305 case PIPE_FORMAT_B5G5R5A1_UNORM:
306 case PIPE_FORMAT_B5G5R5X1_UNORM:
307 return V_028C70_SWAP_ALT;
308
309 case PIPE_FORMAT_B4G4R4A4_UNORM:
310 case PIPE_FORMAT_B4G4R4X4_UNORM:
311 return V_028C70_SWAP_ALT;
312
313 case PIPE_FORMAT_Z16_UNORM:
314 return V_028C70_SWAP_STD;
315
316 case PIPE_FORMAT_L8A8_UNORM:
317 case PIPE_FORMAT_L8A8_UINT:
318 case PIPE_FORMAT_L8A8_SINT:
319 case PIPE_FORMAT_L8A8_SRGB:
320 return V_028C70_SWAP_ALT;
321 case PIPE_FORMAT_R8G8_UNORM:
322 case PIPE_FORMAT_R8G8_UINT:
323 case PIPE_FORMAT_R8G8_SINT:
324 return V_028C70_SWAP_STD;
325
326 case PIPE_FORMAT_R16_UNORM:
327 case PIPE_FORMAT_R16_UINT:
328 case PIPE_FORMAT_R16_SINT:
329 case PIPE_FORMAT_R16_FLOAT:
330 return V_028C70_SWAP_STD;
331
332 /* 32-bit buffers. */
333 case PIPE_FORMAT_A8B8G8R8_SRGB:
334 return V_028C70_SWAP_STD_REV;
335 case PIPE_FORMAT_B8G8R8A8_SRGB:
336 return V_028C70_SWAP_ALT;
337
338 case PIPE_FORMAT_B8G8R8A8_UNORM:
339 case PIPE_FORMAT_B8G8R8X8_UNORM:
340 return V_028C70_SWAP_ALT;
341
342 case PIPE_FORMAT_A8R8G8B8_UNORM:
343 case PIPE_FORMAT_X8R8G8B8_UNORM:
344 return V_028C70_SWAP_ALT_REV;
345 case PIPE_FORMAT_R8G8B8A8_SNORM:
346 case PIPE_FORMAT_R8G8B8A8_UNORM:
347 case PIPE_FORMAT_R8G8B8A8_SSCALED:
348 case PIPE_FORMAT_R8G8B8A8_USCALED:
349 case PIPE_FORMAT_R8G8B8A8_SINT:
350 case PIPE_FORMAT_R8G8B8A8_UINT:
351 case PIPE_FORMAT_R8G8B8X8_UNORM:
352 return V_028C70_SWAP_STD;
353
354 case PIPE_FORMAT_A8B8G8R8_UNORM:
355 case PIPE_FORMAT_X8B8G8R8_UNORM:
356 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
357 return V_028C70_SWAP_STD_REV;
358
359 case PIPE_FORMAT_Z24X8_UNORM:
360 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
361 return V_028C70_SWAP_STD;
362
363 case PIPE_FORMAT_X8Z24_UNORM:
364 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
365 return V_028C70_SWAP_STD;
366
367 case PIPE_FORMAT_R10G10B10A2_UNORM:
368 case PIPE_FORMAT_R10G10B10X2_SNORM:
369 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
370 return V_028C70_SWAP_STD;
371
372 case PIPE_FORMAT_B10G10R10A2_UNORM:
373 case PIPE_FORMAT_B10G10R10A2_UINT:
374 return V_028C70_SWAP_ALT;
375
376 case PIPE_FORMAT_R11G11B10_FLOAT:
377 case PIPE_FORMAT_R32_FLOAT:
378 case PIPE_FORMAT_R32_UINT:
379 case PIPE_FORMAT_R32_SINT:
380 case PIPE_FORMAT_Z32_FLOAT:
381 case PIPE_FORMAT_R16G16_FLOAT:
382 case PIPE_FORMAT_R16G16_UNORM:
383 case PIPE_FORMAT_R16G16_UINT:
384 case PIPE_FORMAT_R16G16_SINT:
385 return V_028C70_SWAP_STD;
386
387 /* 64-bit buffers. */
388 case PIPE_FORMAT_R32G32_FLOAT:
389 case PIPE_FORMAT_R32G32_UINT:
390 case PIPE_FORMAT_R32G32_SINT:
391 case PIPE_FORMAT_R16G16B16A16_UNORM:
392 case PIPE_FORMAT_R16G16B16A16_SNORM:
393 case PIPE_FORMAT_R16G16B16A16_USCALED:
394 case PIPE_FORMAT_R16G16B16A16_SSCALED:
395 case PIPE_FORMAT_R16G16B16A16_UINT:
396 case PIPE_FORMAT_R16G16B16A16_SINT:
397 case PIPE_FORMAT_R16G16B16A16_FLOAT:
398 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
399
400 /* 128-bit buffers. */
401 case PIPE_FORMAT_R32G32B32A32_FLOAT:
402 case PIPE_FORMAT_R32G32B32A32_SNORM:
403 case PIPE_FORMAT_R32G32B32A32_UNORM:
404 case PIPE_FORMAT_R32G32B32A32_SSCALED:
405 case PIPE_FORMAT_R32G32B32A32_USCALED:
406 case PIPE_FORMAT_R32G32B32A32_SINT:
407 case PIPE_FORMAT_R32G32B32A32_UINT:
408 return V_028C70_SWAP_STD;
409 default:
410 R600_ERR("unsupported colorswap format %d\n", format);
411 return ~0U;
412 }
413 return ~0U;
414 }
415
416 static uint32_t si_translate_colorformat(enum pipe_format format)
417 {
418 switch (format) {
419 /* 8-bit buffers. */
420 case PIPE_FORMAT_A8_UNORM:
421 case PIPE_FORMAT_A8_UINT:
422 case PIPE_FORMAT_A8_SINT:
423 case PIPE_FORMAT_I8_UNORM:
424 case PIPE_FORMAT_I8_UINT:
425 case PIPE_FORMAT_I8_SINT:
426 case PIPE_FORMAT_L8_UNORM:
427 case PIPE_FORMAT_L8_UINT:
428 case PIPE_FORMAT_L8_SINT:
429 case PIPE_FORMAT_L8_SRGB:
430 case PIPE_FORMAT_R8_UNORM:
431 case PIPE_FORMAT_R8_SNORM:
432 case PIPE_FORMAT_R8_UINT:
433 case PIPE_FORMAT_R8_SINT:
434 return V_028C70_COLOR_8;
435
436 /* 16-bit buffers. */
437 case PIPE_FORMAT_B5G6R5_UNORM:
438 return V_028C70_COLOR_5_6_5;
439
440 case PIPE_FORMAT_B5G5R5A1_UNORM:
441 case PIPE_FORMAT_B5G5R5X1_UNORM:
442 return V_028C70_COLOR_1_5_5_5;
443
444 case PIPE_FORMAT_B4G4R4A4_UNORM:
445 case PIPE_FORMAT_B4G4R4X4_UNORM:
446 return V_028C70_COLOR_4_4_4_4;
447
448 case PIPE_FORMAT_L8A8_UNORM:
449 case PIPE_FORMAT_L8A8_UINT:
450 case PIPE_FORMAT_L8A8_SINT:
451 case PIPE_FORMAT_L8A8_SRGB:
452 case PIPE_FORMAT_R8G8_UNORM:
453 case PIPE_FORMAT_R8G8_UINT:
454 case PIPE_FORMAT_R8G8_SINT:
455 return V_028C70_COLOR_8_8;
456
457 case PIPE_FORMAT_Z16_UNORM:
458 case PIPE_FORMAT_R16_UNORM:
459 case PIPE_FORMAT_R16_UINT:
460 case PIPE_FORMAT_R16_SINT:
461 case PIPE_FORMAT_R16_FLOAT:
462 case PIPE_FORMAT_R16G16_FLOAT:
463 return V_028C70_COLOR_16;
464
465 /* 32-bit buffers. */
466 case PIPE_FORMAT_A8B8G8R8_SRGB:
467 case PIPE_FORMAT_A8B8G8R8_UNORM:
468 case PIPE_FORMAT_A8R8G8B8_UNORM:
469 case PIPE_FORMAT_B8G8R8A8_SRGB:
470 case PIPE_FORMAT_B8G8R8A8_UNORM:
471 case PIPE_FORMAT_B8G8R8X8_UNORM:
472 case PIPE_FORMAT_R8G8B8A8_SNORM:
473 case PIPE_FORMAT_R8G8B8A8_UNORM:
474 case PIPE_FORMAT_R8G8B8X8_UNORM:
475 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
476 case PIPE_FORMAT_X8B8G8R8_UNORM:
477 case PIPE_FORMAT_X8R8G8B8_UNORM:
478 case PIPE_FORMAT_R8G8B8_UNORM:
479 case PIPE_FORMAT_R8G8B8A8_SSCALED:
480 case PIPE_FORMAT_R8G8B8A8_USCALED:
481 case PIPE_FORMAT_R8G8B8A8_SINT:
482 case PIPE_FORMAT_R8G8B8A8_UINT:
483 return V_028C70_COLOR_8_8_8_8;
484
485 case PIPE_FORMAT_R10G10B10A2_UNORM:
486 case PIPE_FORMAT_R10G10B10X2_SNORM:
487 case PIPE_FORMAT_B10G10R10A2_UNORM:
488 case PIPE_FORMAT_B10G10R10A2_UINT:
489 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
490 return V_028C70_COLOR_2_10_10_10;
491
492 case PIPE_FORMAT_Z24X8_UNORM:
493 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
494 return V_028C70_COLOR_8_24;
495
496 case PIPE_FORMAT_X8Z24_UNORM:
497 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
498 return V_028C70_COLOR_24_8;
499
500 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
501 return V_028C70_COLOR_X24_8_32_FLOAT;
502
503 case PIPE_FORMAT_R32_FLOAT:
504 case PIPE_FORMAT_Z32_FLOAT:
505 return V_028C70_COLOR_32;
506
507 case PIPE_FORMAT_R16G16_SSCALED:
508 case PIPE_FORMAT_R16G16_UNORM:
509 case PIPE_FORMAT_R16G16_UINT:
510 case PIPE_FORMAT_R16G16_SINT:
511 return V_028C70_COLOR_16_16;
512
513 case PIPE_FORMAT_R11G11B10_FLOAT:
514 return V_028C70_COLOR_10_11_11;
515
516 /* 64-bit buffers. */
517 case PIPE_FORMAT_R16G16B16_USCALED:
518 case PIPE_FORMAT_R16G16B16_SSCALED:
519 case PIPE_FORMAT_R16G16B16A16_UINT:
520 case PIPE_FORMAT_R16G16B16A16_SINT:
521 case PIPE_FORMAT_R16G16B16A16_USCALED:
522 case PIPE_FORMAT_R16G16B16A16_SSCALED:
523 case PIPE_FORMAT_R16G16B16A16_UNORM:
524 case PIPE_FORMAT_R16G16B16A16_SNORM:
525 case PIPE_FORMAT_R16G16B16_FLOAT:
526 case PIPE_FORMAT_R16G16B16A16_FLOAT:
527 return V_028C70_COLOR_16_16_16_16;
528
529 case PIPE_FORMAT_R32G32_FLOAT:
530 case PIPE_FORMAT_R32G32_USCALED:
531 case PIPE_FORMAT_R32G32_SSCALED:
532 case PIPE_FORMAT_R32G32_SINT:
533 case PIPE_FORMAT_R32G32_UINT:
534 return V_028C70_COLOR_32_32;
535
536 /* 128-bit buffers. */
537 case PIPE_FORMAT_R32G32B32A32_SNORM:
538 case PIPE_FORMAT_R32G32B32A32_UNORM:
539 case PIPE_FORMAT_R32G32B32A32_SSCALED:
540 case PIPE_FORMAT_R32G32B32A32_USCALED:
541 case PIPE_FORMAT_R32G32B32A32_SINT:
542 case PIPE_FORMAT_R32G32B32A32_UINT:
543 case PIPE_FORMAT_R32G32B32A32_FLOAT:
544 return V_028C70_COLOR_32_32_32_32;
545
546 /* YUV buffers. */
547 case PIPE_FORMAT_UYVY:
548 case PIPE_FORMAT_YUYV:
549 /* 96-bit buffers. */
550 case PIPE_FORMAT_R32G32B32_FLOAT:
551 /* 8-bit buffers. */
552 case PIPE_FORMAT_L4A4_UNORM:
553 case PIPE_FORMAT_R4A4_UNORM:
554 case PIPE_FORMAT_A4R4_UNORM:
555 default:
556 return ~0U; /* Unsupported. */
557 }
558 }
559
560 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
561 {
562 if (R600_BIG_ENDIAN) {
563 switch(colorformat) {
564 /* 8-bit buffers. */
565 case V_028C70_COLOR_8:
566 return V_028C70_ENDIAN_NONE;
567
568 /* 16-bit buffers. */
569 case V_028C70_COLOR_5_6_5:
570 case V_028C70_COLOR_1_5_5_5:
571 case V_028C70_COLOR_4_4_4_4:
572 case V_028C70_COLOR_16:
573 case V_028C70_COLOR_8_8:
574 return V_028C70_ENDIAN_8IN16;
575
576 /* 32-bit buffers. */
577 case V_028C70_COLOR_8_8_8_8:
578 case V_028C70_COLOR_2_10_10_10:
579 case V_028C70_COLOR_8_24:
580 case V_028C70_COLOR_24_8:
581 case V_028C70_COLOR_16_16:
582 return V_028C70_ENDIAN_8IN32;
583
584 /* 64-bit buffers. */
585 case V_028C70_COLOR_16_16_16_16:
586 return V_028C70_ENDIAN_8IN16;
587
588 case V_028C70_COLOR_32_32:
589 return V_028C70_ENDIAN_8IN32;
590
591 /* 128-bit buffers. */
592 case V_028C70_COLOR_32_32_32_32:
593 return V_028C70_ENDIAN_8IN32;
594 default:
595 return V_028C70_ENDIAN_NONE; /* Unsupported. */
596 }
597 } else {
598 return V_028C70_ENDIAN_NONE;
599 }
600 }
601
602 static uint32_t si_translate_texformat(struct pipe_screen *screen,
603 enum pipe_format format,
604 const struct util_format_description *desc,
605 int first_non_void)
606 {
607 boolean uniform = TRUE;
608 int i;
609
610 /* Colorspace (return non-RGB formats directly). */
611 switch (desc->colorspace) {
612 /* Depth stencil formats */
613 case UTIL_FORMAT_COLORSPACE_ZS:
614 switch (format) {
615 case PIPE_FORMAT_Z16_UNORM:
616 return V_008F14_IMG_DATA_FORMAT_16;
617 case PIPE_FORMAT_X24S8_UINT:
618 case PIPE_FORMAT_Z24X8_UNORM:
619 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
620 return V_008F14_IMG_DATA_FORMAT_24_8;
621 case PIPE_FORMAT_S8X24_UINT:
622 case PIPE_FORMAT_X8Z24_UNORM:
623 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
624 return V_008F14_IMG_DATA_FORMAT_8_24;
625 case PIPE_FORMAT_S8_UINT:
626 return V_008F14_IMG_DATA_FORMAT_8;
627 case PIPE_FORMAT_Z32_FLOAT:
628 return V_008F14_IMG_DATA_FORMAT_32;
629 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
630 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
631 default:
632 goto out_unknown;
633 }
634
635 case UTIL_FORMAT_COLORSPACE_YUV:
636 goto out_unknown; /* TODO */
637
638 case UTIL_FORMAT_COLORSPACE_SRGB:
639 break;
640
641 default:
642 break;
643 }
644
645 /* TODO compressed formats */
646
647 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
648 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
649 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
650 return V_008F14_IMG_DATA_FORMAT_10_11_11;
651 }
652
653 /* R8G8Bx_SNORM - TODO CxV8U8 */
654
655 /* See whether the components are of the same size. */
656 for (i = 1; i < desc->nr_channels; i++) {
657 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
658 }
659
660 /* Non-uniform formats. */
661 if (!uniform) {
662 switch(desc->nr_channels) {
663 case 3:
664 if (desc->channel[0].size == 5 &&
665 desc->channel[1].size == 6 &&
666 desc->channel[2].size == 5) {
667 return V_008F14_IMG_DATA_FORMAT_5_6_5;
668 }
669 goto out_unknown;
670 case 4:
671 if (desc->channel[0].size == 5 &&
672 desc->channel[1].size == 5 &&
673 desc->channel[2].size == 5 &&
674 desc->channel[3].size == 1) {
675 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
676 }
677 if (desc->channel[0].size == 10 &&
678 desc->channel[1].size == 10 &&
679 desc->channel[2].size == 10 &&
680 desc->channel[3].size == 2) {
681 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
682 }
683 goto out_unknown;
684 }
685 goto out_unknown;
686 }
687
688 if (first_non_void < 0 || first_non_void > 3)
689 goto out_unknown;
690
691 /* uniform formats */
692 switch (desc->channel[first_non_void].size) {
693 case 4:
694 switch (desc->nr_channels) {
695 case 2:
696 return V_008F14_IMG_DATA_FORMAT_4_4;
697 case 4:
698 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
699 }
700 break;
701 case 8:
702 switch (desc->nr_channels) {
703 case 1:
704 return V_008F14_IMG_DATA_FORMAT_8;
705 case 2:
706 return V_008F14_IMG_DATA_FORMAT_8_8;
707 case 4:
708 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
709 }
710 break;
711 case 16:
712 switch (desc->nr_channels) {
713 case 1:
714 return V_008F14_IMG_DATA_FORMAT_16;
715 case 2:
716 return V_008F14_IMG_DATA_FORMAT_16_16;
717 case 4:
718 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
719 }
720 break;
721 case 32:
722 switch (desc->nr_channels) {
723 case 1:
724 return V_008F14_IMG_DATA_FORMAT_32;
725 case 2:
726 return V_008F14_IMG_DATA_FORMAT_32_32;
727 case 3:
728 return V_008F14_IMG_DATA_FORMAT_32_32_32;
729 case 4:
730 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
731 }
732 }
733
734 out_unknown:
735 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
736 return ~0;
737 }
738
739 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
740 {
741 return si_translate_texformat(screen, format, util_format_description(format),
742 util_format_get_first_non_void_channel(format)) != ~0U;
743 }
744
745 uint32_t si_translate_vertexformat(struct pipe_screen *screen,
746 enum pipe_format format,
747 const struct util_format_description *desc,
748 int first_non_void)
749 {
750 uint32_t result = si_translate_texformat(screen, format, desc, first_non_void);
751
752 if (result == V_008F0C_BUF_DATA_FORMAT_INVALID ||
753 result > V_008F0C_BUF_DATA_FORMAT_32_32_32_32)
754 result = ~0;
755
756 return result;
757 }
758
759 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
760 {
761 return si_translate_vertexformat(screen, format, util_format_description(format),
762 util_format_get_first_non_void_channel(format)) != ~0U;
763 }
764
765 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
766 {
767 return si_translate_colorformat(format) != ~0U &&
768 si_translate_colorswap(format) != ~0U;
769 }
770
771 static bool r600_is_zs_format_supported(enum pipe_format format)
772 {
773 return si_translate_dbformat(format) != ~0U;
774 }
775
776 boolean si_is_format_supported(struct pipe_screen *screen,
777 enum pipe_format format,
778 enum pipe_texture_target target,
779 unsigned sample_count,
780 unsigned usage)
781 {
782 unsigned retval = 0;
783
784 if (target >= PIPE_MAX_TEXTURE_TYPES) {
785 R600_ERR("r600: unsupported texture type %d\n", target);
786 return FALSE;
787 }
788
789 if (!util_format_is_supported(format, usage))
790 return FALSE;
791
792 /* Multisample */
793 if (sample_count > 1)
794 return FALSE;
795
796 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
797 si_is_sampler_format_supported(screen, format)) {
798 retval |= PIPE_BIND_SAMPLER_VIEW;
799 }
800
801 if ((usage & (PIPE_BIND_RENDER_TARGET |
802 PIPE_BIND_DISPLAY_TARGET |
803 PIPE_BIND_SCANOUT |
804 PIPE_BIND_SHARED)) &&
805 r600_is_colorbuffer_format_supported(format)) {
806 retval |= usage &
807 (PIPE_BIND_RENDER_TARGET |
808 PIPE_BIND_DISPLAY_TARGET |
809 PIPE_BIND_SCANOUT |
810 PIPE_BIND_SHARED);
811 }
812
813 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
814 r600_is_zs_format_supported(format)) {
815 retval |= PIPE_BIND_DEPTH_STENCIL;
816 }
817
818 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
819 si_is_vertex_format_supported(screen, format)) {
820 retval |= PIPE_BIND_VERTEX_BUFFER;
821 }
822
823 if (usage & PIPE_BIND_TRANSFER_READ)
824 retval |= PIPE_BIND_TRANSFER_READ;
825 if (usage & PIPE_BIND_TRANSFER_WRITE)
826 retval |= PIPE_BIND_TRANSFER_WRITE;
827
828 return retval == usage;
829 }
830
831 static void evergreen_set_blend_color(struct pipe_context *ctx,
832 const struct pipe_blend_color *state)
833 {
834 struct r600_context *rctx = (struct r600_context *)ctx;
835 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
836
837 if (rstate == NULL)
838 return;
839
840 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
841 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), NULL, 0);
842 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), NULL, 0);
843 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), NULL, 0);
844 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), NULL, 0);
845
846 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
847 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
848 r600_context_pipe_state_set(rctx, rstate);
849 }
850
851 static void *evergreen_create_blend_state(struct pipe_context *ctx,
852 const struct pipe_blend_state *state)
853 {
854 struct r600_context *rctx = (struct r600_context *)ctx;
855 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
856 struct r600_pipe_state *rstate;
857 uint32_t color_control, target_mask;
858 /* FIXME there is more then 8 framebuffer */
859 unsigned blend_cntl[8];
860
861 if (blend == NULL) {
862 return NULL;
863 }
864
865 rstate = &blend->rstate;
866
867 rstate->id = R600_PIPE_STATE_BLEND;
868
869 target_mask = 0;
870 color_control = S_028808_MODE(V_028808_CB_NORMAL);
871 if (state->logicop_enable) {
872 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
873 } else {
874 color_control |= S_028808_ROP3(0xcc);
875 }
876 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
877 if (state->independent_blend_enable) {
878 for (int i = 0; i < 8; i++) {
879 target_mask |= (state->rt[i].colormask << (4 * i));
880 }
881 } else {
882 for (int i = 0; i < 8; i++) {
883 target_mask |= (state->rt[0].colormask << (4 * i));
884 }
885 }
886 blend->cb_target_mask = target_mask;
887
888 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
889 color_control, NULL, 0);
890
891 r600_pipe_state_add_reg(rstate, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, ~0, NULL, 0);
892 r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, ~0, NULL, 0);
893
894 for (int i = 0; i < 8; i++) {
895 /* state->rt entries > 0 only written if independent blending */
896 const int j = state->independent_blend_enable ? i : 0;
897
898 unsigned eqRGB = state->rt[j].rgb_func;
899 unsigned srcRGB = state->rt[j].rgb_src_factor;
900 unsigned dstRGB = state->rt[j].rgb_dst_factor;
901 unsigned eqA = state->rt[j].alpha_func;
902 unsigned srcA = state->rt[j].alpha_src_factor;
903 unsigned dstA = state->rt[j].alpha_dst_factor;
904
905 blend_cntl[i] = 0;
906 if (!state->rt[j].blend_enable)
907 continue;
908
909 blend_cntl[i] |= S_028780_ENABLE(1);
910 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
911 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
912 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
913
914 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
915 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
916 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
917 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
918 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
919 }
920 }
921 for (int i = 0; i < 8; i++) {
922 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], NULL, 0);
923 }
924
925 return rstate;
926 }
927
928 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
929 const struct pipe_depth_stencil_alpha_state *state)
930 {
931 struct r600_context *rctx = (struct r600_context *)ctx;
932 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
933 unsigned db_depth_control, alpha_test_control, alpha_ref;
934 unsigned db_render_override, db_render_control;
935 struct r600_pipe_state *rstate;
936
937 if (dsa == NULL) {
938 return NULL;
939 }
940
941 dsa->valuemask[0] = state->stencil[0].valuemask;
942 dsa->valuemask[1] = state->stencil[1].valuemask;
943 dsa->writemask[0] = state->stencil[0].writemask;
944 dsa->writemask[1] = state->stencil[1].writemask;
945
946 rstate = &dsa->rstate;
947
948 rstate->id = R600_PIPE_STATE_DSA;
949 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
950 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
951 S_028800_ZFUNC(state->depth.func);
952
953 /* stencil */
954 if (state->stencil[0].enabled) {
955 db_depth_control |= S_028800_STENCIL_ENABLE(1);
956 db_depth_control |= S_028800_STENCILFUNC(si_translate_ds_func(state->stencil[0].func));
957 //db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
958 //db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
959 //db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
960
961 if (state->stencil[1].enabled) {
962 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
963 db_depth_control |= S_028800_STENCILFUNC_BF(si_translate_ds_func(state->stencil[1].func));
964 //db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
965 //db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
966 //db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
967 }
968 }
969
970 /* alpha */
971 alpha_test_control = 0;
972 alpha_ref = 0;
973 if (state->alpha.enabled) {
974 //alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
975 //alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
976 alpha_ref = fui(state->alpha.ref_value);
977 }
978 dsa->alpha_ref = alpha_ref;
979
980 /* misc */
981 db_render_control = 0;
982 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
983 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
984 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
985 /* TODO db_render_override depends on query */
986 r600_pipe_state_add_reg(rstate, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000, NULL, 0);
987 r600_pipe_state_add_reg(rstate, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000, NULL, 0);
988 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, NULL, 0);
989 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, NULL, 0);
990 //r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, NULL, 0);
991 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, NULL, 0);
992 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, NULL, 0);
993 r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, NULL, 0);
994 r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, NULL, 0);
995 r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, NULL, 0);
996 r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, NULL, 0);
997 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, NULL, 0);
998 dsa->db_render_override = db_render_override;
999
1000 return rstate;
1001 }
1002
1003 static void *evergreen_create_rs_state(struct pipe_context *ctx,
1004 const struct pipe_rasterizer_state *state)
1005 {
1006 struct r600_context *rctx = (struct r600_context *)ctx;
1007 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
1008 struct r600_pipe_state *rstate;
1009 unsigned tmp;
1010 unsigned prov_vtx = 1, polygon_dual_mode;
1011 unsigned clip_rule;
1012 float psize_min, psize_max;
1013
1014 if (rs == NULL) {
1015 return NULL;
1016 }
1017
1018 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
1019 state->fill_back != PIPE_POLYGON_MODE_FILL);
1020
1021 if (state->flatshade_first)
1022 prov_vtx = 0;
1023
1024 rstate = &rs->rstate;
1025 rs->flatshade = state->flatshade;
1026 rs->sprite_coord_enable = state->sprite_coord_enable;
1027 rs->pa_sc_line_stipple = state->line_stipple_enable ?
1028 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
1029 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
1030 rs->pa_su_sc_mode_cntl =
1031 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
1032 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
1033 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
1034 S_028814_FACE(!state->front_ccw) |
1035 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
1036 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
1037 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
1038 S_028814_POLY_MODE(polygon_dual_mode) |
1039 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
1040 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
1041 rs->pa_cl_clip_cntl =
1042 S_028810_PS_UCP_MODE(3) |
1043 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
1044 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
1045 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1046 rs->pa_cl_vs_out_cntl =
1047 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
1048 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
1049
1050 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
1051
1052 /* offset */
1053 rs->offset_units = state->offset_units;
1054 rs->offset_scale = state->offset_scale * 12.0f;
1055
1056 rstate->id = R600_PIPE_STATE_RASTERIZER;
1057 tmp = S_0286D4_FLAT_SHADE_ENA(state->flatshade);
1058 if (state->sprite_coord_enable) {
1059 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
1060 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1061 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1062 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1063 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
1064 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
1065 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
1066 }
1067 }
1068 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, NULL, 0);
1069
1070 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, NULL, 0);
1071 /* point size 12.4 fixed point */
1072 tmp = (unsigned)(state->point_size * 8.0);
1073 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), NULL, 0);
1074
1075 if (state->point_size_per_vertex) {
1076 psize_min = util_get_min_point_size(state);
1077 psize_max = 8192;
1078 } else {
1079 /* Force the point size to be as if the vertex output was disabled. */
1080 psize_min = state->point_size;
1081 psize_max = state->point_size;
1082 }
1083 /* Divide by two, because 0.5 = 1 pixel. */
1084 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
1085 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
1086 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)),
1087 NULL, 0);
1088
1089 tmp = (unsigned)state->line_width * 8;
1090 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), NULL, 0);
1091 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
1092 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable),
1093 NULL, 0);
1094
1095 r600_pipe_state_add_reg(rstate, R_028BDC_PA_SC_LINE_CNTL, 0x00000400, NULL, 0);
1096 r600_pipe_state_add_reg(rstate, R_028BE4_PA_SU_VTX_CNTL,
1097 S_028BE4_PIX_CENTER(state->gl_rasterization_rules),
1098 NULL, 0);
1099 r600_pipe_state_add_reg(rstate, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, NULL, 0);
1100 r600_pipe_state_add_reg(rstate, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, NULL, 0);
1101 r600_pipe_state_add_reg(rstate, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, NULL, 0);
1102 r600_pipe_state_add_reg(rstate, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, NULL, 0);
1103
1104 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), NULL, 0);
1105 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, NULL, 0);
1106 return rstate;
1107 }
1108
1109 static void *si_create_sampler_state(struct pipe_context *ctx,
1110 const struct pipe_sampler_state *state)
1111 {
1112 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
1113 union util_color uc;
1114 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
1115 unsigned border_color_type;
1116
1117 if (rstate == NULL) {
1118 return NULL;
1119 }
1120
1121 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
1122 switch (uc.ui) {
1123 case 0x000000FF:
1124 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
1125 break;
1126 case 0x00000000:
1127 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
1128 break;
1129 case 0xFFFFFFFF:
1130 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
1131 break;
1132 default: /* Use border color pointer */
1133 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
1134 }
1135
1136 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
1137 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
1138 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
1139 (state->max_anisotropy & 0x7) << 9 | /* XXX */
1140 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
1141 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
1142 aniso_flag_offset << 16 | /* XXX */
1143 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
1144 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
1145 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
1146 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
1147 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
1148 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
1149 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
1150 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
1151
1152 #if 0
1153 if (border_color_type == 3) {
1154 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0);
1155 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0);
1156 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0);
1157 r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0);
1158 }
1159 #endif
1160 return rstate;
1161 }
1162
1163 static void si_delete_sampler_state(struct pipe_context *ctx,
1164 void *state)
1165 {
1166 free(state);
1167 }
1168
1169 static unsigned si_map_swizzle(unsigned swizzle)
1170 {
1171 switch (swizzle) {
1172 case UTIL_FORMAT_SWIZZLE_Y:
1173 return V_008F1C_SQ_SEL_Y;
1174 case UTIL_FORMAT_SWIZZLE_Z:
1175 return V_008F1C_SQ_SEL_Z;
1176 case UTIL_FORMAT_SWIZZLE_W:
1177 return V_008F1C_SQ_SEL_W;
1178 case UTIL_FORMAT_SWIZZLE_0:
1179 return V_008F1C_SQ_SEL_0;
1180 case UTIL_FORMAT_SWIZZLE_1:
1181 return V_008F1C_SQ_SEL_1;
1182 default: /* UTIL_FORMAT_SWIZZLE_X */
1183 return V_008F1C_SQ_SEL_X;
1184 }
1185 }
1186
1187 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
1188 struct pipe_resource *texture,
1189 const struct pipe_sampler_view *state)
1190 {
1191 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
1192 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
1193 const struct util_format_description *desc = util_format_description(state->format);
1194 unsigned format, num_format, endian;
1195 uint32_t pitch = 0;
1196 unsigned char state_swizzle[4], swizzle[4], array_mode = 0, tile_type = 0;
1197 unsigned height, depth;
1198 int first_non_void;
1199 uint64_t va;
1200
1201 if (view == NULL)
1202 return NULL;
1203
1204 /* initialize base object */
1205 view->base = *state;
1206 view->base.texture = NULL;
1207 pipe_reference(NULL, &texture->reference);
1208 view->base.texture = texture;
1209 view->base.reference.count = 1;
1210 view->base.context = ctx;
1211
1212 state_swizzle[0] = state->swizzle_r;
1213 state_swizzle[1] = state->swizzle_g;
1214 state_swizzle[2] = state->swizzle_b;
1215 state_swizzle[3] = state->swizzle_a;
1216 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
1217
1218 first_non_void = util_format_get_first_non_void_channel(state->format);
1219 switch (desc->channel[first_non_void].type) {
1220 case UTIL_FORMAT_TYPE_FLOAT:
1221 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
1222 break;
1223 case UTIL_FORMAT_TYPE_FIXED:
1224 num_format = V_008F14_IMG_NUM_FORMAT_USCALED; /* XXX */
1225 break;
1226 case UTIL_FORMAT_TYPE_SIGNED:
1227 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
1228 break;
1229 case UTIL_FORMAT_TYPE_UNSIGNED:
1230 default:
1231 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
1232 }
1233
1234 format = si_translate_texformat(ctx->screen, state->format, desc, first_non_void);
1235 if (format == ~0) {
1236 format = 0;
1237 }
1238
1239 if (tmp->depth && !tmp->is_flushing_texture) {
1240 r600_texture_depth_flush(ctx, texture, TRUE);
1241 tmp = tmp->flushed_depth_texture;
1242 }
1243
1244 endian = si_colorformat_endian_swap(format);
1245
1246 height = texture->height0;
1247 depth = texture->depth0;
1248
1249 pitch = tmp->pitch_in_blocks[0] * util_format_get_blockwidth(state->format);
1250 array_mode = tmp->array_mode[0];
1251 tile_type = tmp->tile_type;
1252
1253 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1254 height = 1;
1255 depth = texture->array_size;
1256 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1257 depth = texture->array_size;
1258 }
1259
1260 va = r600_resource_va(ctx->screen, texture);
1261 view->state[0] = (va + tmp->offset[0]) >> 8;
1262 view->state[1] = ((va + tmp->offset[0]) >> 40) & 0xff;
1263 view->state[1] |= (S_008F14_DATA_FORMAT(format) |
1264 S_008F14_NUM_FORMAT(num_format));
1265 view->state[2] = (S_008F18_WIDTH(texture->width0 - 1) |
1266 S_008F18_HEIGHT(height - 1));
1267 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
1268 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
1269 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
1270 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
1271 S_008F1C_BASE_LEVEL(state->u.tex.first_level) |
1272 S_008F1C_LAST_LEVEL(state->u.tex.last_level) |
1273 S_008F1C_TILING_INDEX(8) | /* XXX */
1274 S_008F1C_TYPE(si_tex_dim(texture->target)));
1275 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
1276 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
1277 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
1278 view->state[6] = 0;
1279 view->state[7] = 0;
1280
1281 return &view->base;
1282 }
1283
1284 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1285 struct pipe_sampler_view **views)
1286 {
1287 }
1288
1289 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1290 struct pipe_sampler_view **views)
1291 {
1292 struct r600_context *rctx = (struct r600_context *)ctx;
1293 struct si_pipe_sampler_view **resource = (struct si_pipe_sampler_view **)views;
1294 struct r600_pipe_state *rstate = &rctx->ps_samplers.rstate;
1295 struct r600_resource *bo;
1296 int i;
1297 int has_depth = 0;
1298 uint64_t va;
1299 char *ptr;
1300
1301 if (!count)
1302 goto out;
1303
1304 r600_inval_texture_cache(rctx);
1305
1306 bo = (struct r600_resource*)
1307 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
1308 count * sizeof(resource[0]->state));
1309 ptr = rctx->ws->buffer_map(bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
1310
1311 for (i = 0; i < count; i++, ptr += sizeof(resource[0]->state)) {
1312 pipe_sampler_view_reference(
1313 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
1314 views[i]);
1315
1316 if (resource[i]) {
1317 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1318 has_depth = 1;
1319
1320 memcpy(ptr, resource[i]->state, sizeof(resource[0]->state));
1321 } else
1322 memset(ptr, 0, sizeof(resource[0]->state));
1323 }
1324
1325 rctx->ws->buffer_unmap(bo->cs_buf);
1326
1327 for (i = count; i < NUM_TEX_UNITS; i++) {
1328 if (rctx->ps_samplers.views[i])
1329 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
1330 }
1331
1332 va = r600_resource_va(ctx->screen, (void *)bo);
1333 r600_pipe_state_add_reg(rstate, R_00B040_SPI_SHADER_USER_DATA_PS_4, va, bo, RADEON_USAGE_READ);
1334 r600_pipe_state_add_reg(rstate, R_00B044_SPI_SHADER_USER_DATA_PS_5, va >> 32, NULL, 0);
1335 r600_context_pipe_state_set(rctx, rstate);
1336
1337 out:
1338 rctx->have_depth_texture = has_depth;
1339 rctx->ps_samplers.n_views = count;
1340 }
1341
1342 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1343 {
1344 struct r600_context *rctx = (struct r600_context *)ctx;
1345 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
1346 struct r600_pipe_state *rstate = &rctx->ps_samplers.rstate;
1347 struct r600_resource *bo;
1348 uint64_t va;
1349 char *ptr;
1350 int i;
1351
1352 if (!count)
1353 goto out;
1354
1355 r600_inval_texture_cache(rctx);
1356
1357 bo = (struct r600_resource*)
1358 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
1359 count * sizeof(rstates[0]->val));
1360 ptr = rctx->ws->buffer_map(bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
1361
1362 for (i = 0; i < count; i++, ptr += sizeof(rstates[0]->val)) {
1363 memcpy(ptr, rstates[i]->val, sizeof(rstates[0]->val));
1364 }
1365
1366 rctx->ws->buffer_unmap(bo->cs_buf);
1367
1368 va = r600_resource_va(ctx->screen, (void *)bo);
1369 r600_pipe_state_add_reg(rstate, R_00B038_SPI_SHADER_USER_DATA_PS_2, va, bo, RADEON_USAGE_READ);
1370 r600_pipe_state_add_reg(rstate, R_00B03C_SPI_SHADER_USER_DATA_PS_3, va >> 32, NULL, 0);
1371 r600_context_pipe_state_set(rctx, rstate);
1372
1373 out:
1374 rctx->ps_samplers.n_samplers = count;
1375 }
1376
1377 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1378 {
1379 }
1380
1381 static void evergreen_set_clip_state(struct pipe_context *ctx,
1382 const struct pipe_clip_state *state)
1383 {
1384 struct r600_context *rctx = (struct r600_context *)ctx;
1385 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1386
1387 if (rstate == NULL)
1388 return;
1389
1390 rctx->clip = *state;
1391 rstate->id = R600_PIPE_STATE_CLIP;
1392 for (int i = 0; i < 6; i++) {
1393 r600_pipe_state_add_reg(rstate,
1394 R_0285BC_PA_CL_UCP_0_X + i * 16,
1395 fui(state->ucp[i][0]), NULL, 0);
1396 r600_pipe_state_add_reg(rstate,
1397 R_0285C0_PA_CL_UCP_0_Y + i * 16,
1398 fui(state->ucp[i][1]) , NULL, 0);
1399 r600_pipe_state_add_reg(rstate,
1400 R_0285C4_PA_CL_UCP_0_Z + i * 16,
1401 fui(state->ucp[i][2]), NULL, 0);
1402 r600_pipe_state_add_reg(rstate,
1403 R_0285C8_PA_CL_UCP_0_W + i * 16,
1404 fui(state->ucp[i][3]), NULL, 0);
1405 }
1406
1407 free(rctx->states[R600_PIPE_STATE_CLIP]);
1408 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1409 r600_context_pipe_state_set(rctx, rstate);
1410 }
1411
1412 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1413 const struct pipe_poly_stipple *state)
1414 {
1415 }
1416
1417 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1418 {
1419 }
1420
1421 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1422 const struct pipe_scissor_state *state)
1423 {
1424 struct r600_context *rctx = (struct r600_context *)ctx;
1425 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1426 uint32_t tl, br;
1427
1428 if (rstate == NULL)
1429 return;
1430
1431 rstate->id = R600_PIPE_STATE_SCISSOR;
1432 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
1433 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1434 r600_pipe_state_add_reg(rstate,
1435 R_028210_PA_SC_CLIPRECT_0_TL, tl,
1436 NULL, 0);
1437 r600_pipe_state_add_reg(rstate,
1438 R_028214_PA_SC_CLIPRECT_0_BR, br,
1439 NULL, 0);
1440 r600_pipe_state_add_reg(rstate,
1441 R_028218_PA_SC_CLIPRECT_1_TL, tl,
1442 NULL, 0);
1443 r600_pipe_state_add_reg(rstate,
1444 R_02821C_PA_SC_CLIPRECT_1_BR, br,
1445 NULL, 0);
1446 r600_pipe_state_add_reg(rstate,
1447 R_028220_PA_SC_CLIPRECT_2_TL, tl,
1448 NULL, 0);
1449 r600_pipe_state_add_reg(rstate,
1450 R_028224_PA_SC_CLIPRECT_2_BR, br,
1451 NULL, 0);
1452 r600_pipe_state_add_reg(rstate,
1453 R_028228_PA_SC_CLIPRECT_3_TL, tl,
1454 NULL, 0);
1455 r600_pipe_state_add_reg(rstate,
1456 R_02822C_PA_SC_CLIPRECT_3_BR, br,
1457 NULL, 0);
1458
1459 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1460 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1461 r600_context_pipe_state_set(rctx, rstate);
1462 }
1463
1464 static void evergreen_set_viewport_state(struct pipe_context *ctx,
1465 const struct pipe_viewport_state *state)
1466 {
1467 struct r600_context *rctx = (struct r600_context *)ctx;
1468 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1469
1470 if (rstate == NULL)
1471 return;
1472
1473 rctx->viewport = *state;
1474 rstate->id = R600_PIPE_STATE_VIEWPORT;
1475 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, NULL, 0);
1476 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, NULL, 0);
1477 r600_pipe_state_add_reg(rstate, R_028350_PA_SC_RASTER_CONFIG, 0x00000000, NULL, 0);
1478 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), NULL, 0);
1479 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), NULL, 0);
1480 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), NULL, 0);
1481 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), NULL, 0);
1482 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), NULL, 0);
1483 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), NULL, 0);
1484 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, NULL, 0);
1485
1486 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1487 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1488 r600_context_pipe_state_set(rctx, rstate);
1489 }
1490
1491 static void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
1492 const struct pipe_framebuffer_state *state, int cb)
1493 {
1494 struct r600_resource_texture *rtex;
1495 struct r600_surface *surf;
1496 unsigned level = state->cbufs[cb]->u.tex.level;
1497 unsigned pitch, slice;
1498 unsigned color_info;
1499 unsigned format, swap, ntype, endian;
1500 uint64_t offset;
1501 unsigned tile_type;
1502 const struct util_format_description *desc;
1503 int i;
1504 unsigned blend_clamp = 0, blend_bypass = 0;
1505
1506 surf = (struct r600_surface *)state->cbufs[cb];
1507 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1508
1509 if (rtex->depth)
1510 rctx->have_depth_fb = TRUE;
1511
1512 if (rtex->depth && !rtex->is_flushing_texture) {
1513 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1514 rtex = rtex->flushed_depth_texture;
1515 }
1516
1517 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1518 offset = r600_texture_get_offset(rtex,
1519 level, state->cbufs[cb]->u.tex.first_layer);
1520 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1521 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1522 desc = util_format_description(surf->base.format);
1523 for (i = 0; i < 4; i++) {
1524 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1525 break;
1526 }
1527 }
1528 if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1529 ntype = V_028C70_NUMBER_FLOAT;
1530 } else {
1531 ntype = V_028C70_NUMBER_UNORM;
1532 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1533 ntype = V_028C70_NUMBER_SRGB;
1534 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1535 if (desc->channel[i].normalized)
1536 ntype = V_028C70_NUMBER_SNORM;
1537 else if (desc->channel[i].pure_integer)
1538 ntype = V_028C70_NUMBER_SINT;
1539 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1540 if (desc->channel[i].normalized)
1541 ntype = V_028C70_NUMBER_UNORM;
1542 else if (desc->channel[i].pure_integer)
1543 ntype = V_028C70_NUMBER_UINT;
1544 }
1545 }
1546
1547 format = si_translate_colorformat(surf->base.format);
1548 swap = si_translate_colorswap(surf->base.format);
1549 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1550 endian = V_028C70_ENDIAN_NONE;
1551 } else {
1552 endian = si_colorformat_endian_swap(format);
1553 }
1554
1555 /* blend clamp should be set for all NORM/SRGB types */
1556 if (ntype == V_028C70_NUMBER_UNORM ||
1557 ntype == V_028C70_NUMBER_SNORM ||
1558 ntype == V_028C70_NUMBER_SRGB)
1559 blend_clamp = 1;
1560
1561 /* set blend bypass according to docs if SINT/UINT or
1562 8/24 COLOR variants */
1563 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1564 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1565 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1566 blend_clamp = 0;
1567 blend_bypass = 1;
1568 }
1569
1570 color_info = S_028C70_FORMAT(format) |
1571 S_028C70_COMP_SWAP(swap) |
1572 //S_028C70_ARRAY_MODE(rtex->array_mode[level]) |
1573 S_028C70_BLEND_CLAMP(blend_clamp) |
1574 S_028C70_BLEND_BYPASS(blend_bypass) |
1575 S_028C70_NUMBER_TYPE(ntype) |
1576 S_028C70_ENDIAN(endian);
1577
1578 color_info |= S_028C70_LINEAR_GENERAL(1);
1579
1580 rctx->alpha_ref_dirty = true;
1581
1582 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1583 offset >>= 8;
1584
1585 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1586 r600_pipe_state_add_reg(rstate,
1587 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
1588 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1589 r600_pipe_state_add_reg(rstate,
1590 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
1591 S_028C64_TILE_MAX(pitch),
1592 NULL, 0);
1593 r600_pipe_state_add_reg(rstate,
1594 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
1595 S_028C68_TILE_MAX(slice),
1596 NULL, 0);
1597 r600_pipe_state_add_reg(rstate,
1598 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1599 0x00000000, NULL, 0);
1600 r600_pipe_state_add_reg(rstate,
1601 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
1602 color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1603 r600_pipe_state_add_reg(rstate,
1604 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
1605 0,
1606 &rtex->resource, RADEON_USAGE_READWRITE);
1607 }
1608
1609 static void si_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
1610 const struct pipe_framebuffer_state *state)
1611 {
1612 struct r600_resource_texture *rtex;
1613 struct r600_surface *surf;
1614 unsigned level, first_layer, pitch, slice, format;
1615 uint32_t db_z_info, stencil_info;
1616 uint64_t offset;
1617
1618 if (state->zsbuf == NULL) {
1619 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO, 0, NULL, 0);
1620 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO, 0, NULL, 0);
1621 return;
1622 }
1623
1624 surf = (struct r600_surface *)state->zsbuf;
1625 level = surf->base.u.tex.level;
1626 rtex = (struct r600_resource_texture*)surf->base.texture;
1627
1628 first_layer = surf->base.u.tex.first_layer;
1629 offset = r600_texture_get_offset(rtex, level, first_layer);
1630 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1631 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1632 format = si_translate_dbformat(rtex->real_format);
1633
1634 offset += r600_resource_va(rctx->context.screen, surf->base.texture);
1635 offset >>= 8;
1636
1637 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
1638 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1639 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
1640 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1641 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, NULL, 0);
1642
1643 db_z_info = S_028040_FORMAT(format);
1644 stencil_info = S_028044_FORMAT(rtex->stencil != 0);
1645
1646 switch (format) {
1647 case V_028040_Z_16:
1648 db_z_info |= S_028040_TILE_MODE_INDEX(5);
1649 stencil_info |= S_028044_TILE_MODE_INDEX(5);
1650 break;
1651 case V_028040_Z_24:
1652 case V_028040_Z_32_FLOAT:
1653 db_z_info |= S_028040_TILE_MODE_INDEX(6);
1654 stencil_info |= S_028044_TILE_MODE_INDEX(6);
1655 break;
1656 default:
1657 db_z_info |= S_028040_TILE_MODE_INDEX(7);
1658 stencil_info |= S_028044_TILE_MODE_INDEX(7);
1659 }
1660
1661 if (rtex->stencil) {
1662 uint64_t stencil_offset =
1663 r600_texture_get_offset(rtex->stencil, level, first_layer);
1664
1665 stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil);
1666 stencil_offset >>= 8;
1667
1668 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1669 stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1670 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1671 stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1672 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1673 stencil_info, NULL, 0);
1674 } else {
1675 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1676 0, NULL, 0);
1677 }
1678
1679 if (format != ~0U) {
1680 r600_pipe_state_add_reg(rstate, R_02803C_DB_DEPTH_INFO, 0x1, NULL, 0);
1681 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO, db_z_info, NULL, 0);
1682 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
1683 S_028058_PITCH_TILE_MAX(pitch),
1684 NULL, 0);
1685 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
1686 S_02805C_SLICE_TILE_MAX(slice),
1687 NULL, 0);
1688
1689 } else {
1690 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO, 0, NULL, 0);
1691 }
1692 }
1693
1694 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1695 const struct pipe_framebuffer_state *state)
1696 {
1697 struct r600_context *rctx = (struct r600_context *)ctx;
1698 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1699 uint32_t shader_mask, tl, br;
1700 int tl_x, tl_y, br_x, br_y;
1701
1702 if (rstate == NULL)
1703 return;
1704
1705 r600_flush_framebuffer(rctx, false);
1706
1707 /* unreference old buffer and reference new one */
1708 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1709
1710 util_copy_framebuffer_state(&rctx->framebuffer, state);
1711
1712 /* build states */
1713 rctx->have_depth_fb = 0;
1714 rctx->nr_cbufs = state->nr_cbufs;
1715 for (int i = 0; i < state->nr_cbufs; i++) {
1716 evergreen_cb(rctx, rstate, state, i);
1717 }
1718 si_db(rctx, rstate, state);
1719
1720 shader_mask = 0;
1721 for (int i = 0; i < state->nr_cbufs; i++) {
1722 shader_mask |= 0xf << (i * 4);
1723 }
1724 tl_x = 0;
1725 tl_y = 0;
1726 br_x = state->width;
1727 br_y = state->height;
1728 #if 0 /* These shouldn't be necessary on SI, see PA_SC_ENHANCE register */
1729 /* EG hw workaround */
1730 if (br_x == 0)
1731 tl_x = 1;
1732 if (br_y == 0)
1733 tl_y = 1;
1734 /* cayman hw workaround */
1735 if (rctx->chip_class == CAYMAN) {
1736 if (br_x == 1 && br_y == 1)
1737 br_x = 2;
1738 }
1739 #endif
1740 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1741 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1742
1743 r600_pipe_state_add_reg(rstate,
1744 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1745 NULL, 0);
1746 r600_pipe_state_add_reg(rstate,
1747 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1748 NULL, 0);
1749 r600_pipe_state_add_reg(rstate,
1750 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1751 NULL, 0);
1752 r600_pipe_state_add_reg(rstate,
1753 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1754 NULL, 0);
1755 r600_pipe_state_add_reg(rstate,
1756 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1757 NULL, 0);
1758 r600_pipe_state_add_reg(rstate,
1759 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1760 NULL, 0);
1761 r600_pipe_state_add_reg(rstate,
1762 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1763 NULL, 0);
1764 r600_pipe_state_add_reg(rstate,
1765 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1766 NULL, 0);
1767 r600_pipe_state_add_reg(rstate,
1768 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1769 NULL, 0);
1770 r600_pipe_state_add_reg(rstate,
1771 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1772 NULL, 0);
1773
1774 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1775 shader_mask, NULL, 0);
1776
1777 r600_pipe_state_add_reg(rstate, R_028BE0_PA_SC_AA_CONFIG,
1778 0x00000000, NULL, 0);
1779
1780 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1781 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1782 r600_context_pipe_state_set(rctx, rstate);
1783
1784 if (state->zsbuf) {
1785 cayman_polygon_offset_update(rctx);
1786 }
1787 }
1788
1789 void cayman_init_state_functions(struct r600_context *rctx)
1790 {
1791 rctx->context.create_blend_state = evergreen_create_blend_state;
1792 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1793 rctx->context.create_fs_state = si_create_shader_state;
1794 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1795 rctx->context.create_sampler_state = si_create_sampler_state;
1796 rctx->context.create_sampler_view = evergreen_create_sampler_view;
1797 rctx->context.create_vertex_elements_state = si_create_vertex_elements;
1798 rctx->context.create_vs_state = si_create_shader_state;
1799 rctx->context.bind_blend_state = r600_bind_blend_state;
1800 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1801 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1802 rctx->context.bind_fs_state = r600_bind_ps_shader;
1803 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1804 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1805 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1806 rctx->context.bind_vs_state = r600_bind_vs_shader;
1807 rctx->context.delete_blend_state = r600_delete_state;
1808 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1809 rctx->context.delete_fs_state = r600_delete_ps_shader;
1810 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1811 rctx->context.delete_sampler_state = si_delete_sampler_state;
1812 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1813 rctx->context.delete_vs_state = r600_delete_vs_shader;
1814 rctx->context.set_blend_color = evergreen_set_blend_color;
1815 rctx->context.set_clip_state = evergreen_set_clip_state;
1816 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1817 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1818 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1819 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1820 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1821 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1822 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1823 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1824 rctx->context.set_index_buffer = r600_set_index_buffer;
1825 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1826 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1827 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1828 rctx->context.texture_barrier = r600_texture_barrier;
1829 rctx->context.create_stream_output_target = r600_create_so_target;
1830 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1831 rctx->context.set_stream_output_targets = r600_set_so_targets;
1832 }
1833
1834 void si_init_config(struct r600_context *rctx)
1835 {
1836 struct r600_pipe_state *rstate = &rctx->config;
1837 unsigned tmp;
1838
1839 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, NULL, 0);
1840
1841 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, NULL, 0);
1842 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, NULL, 0);
1843 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, NULL, 0);
1844 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, NULL, 0);
1845 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, NULL, 0);
1846 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, NULL, 0);
1847 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, NULL, 0);
1848 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, NULL, 0);
1849 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, NULL, 0);
1850 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, NULL, 0);
1851 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, NULL, 0);
1852 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, NULL, 0);
1853 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, NULL, 0);
1854 r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x0, NULL, 0);
1855 r600_pipe_state_add_reg(rstate, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0, NULL, 0);
1856 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, NULL, 0);
1857 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, NULL, 0);
1858 r600_pipe_state_add_reg(rstate, R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63), NULL, 0);
1859 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, NULL, 0);
1860 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, NULL, 0);
1861 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, NULL, 0);
1862
1863 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, NULL, 0);
1864
1865 r600_pipe_state_add_reg(rstate, R_028B54_VGT_SHADER_STAGES_EN, 0, NULL, 0);
1866 r600_pipe_state_add_reg(rstate, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210, NULL, 0);
1867 r600_pipe_state_add_reg(rstate, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98, NULL, 0);
1868
1869 r600_pipe_state_add_reg(rstate, R_028804_DB_EQAA, 0x110000, NULL, 0);
1870 r600_context_pipe_state_set(rctx, rstate);
1871 }
1872
1873 void cayman_polygon_offset_update(struct r600_context *rctx)
1874 {
1875 struct r600_pipe_state state;
1876
1877 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
1878 state.nregs = 0;
1879 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
1880 float offset_units = rctx->rasterizer->offset_units;
1881 unsigned offset_db_fmt_cntl = 0, depth;
1882
1883 switch (rctx->framebuffer.zsbuf->texture->format) {
1884 case PIPE_FORMAT_Z24X8_UNORM:
1885 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1886 depth = -24;
1887 offset_units *= 2.0f;
1888 break;
1889 case PIPE_FORMAT_Z32_FLOAT:
1890 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1891 depth = -23;
1892 offset_units *= 1.0f;
1893 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1894 break;
1895 case PIPE_FORMAT_Z16_UNORM:
1896 depth = -16;
1897 offset_units *= 4.0f;
1898 break;
1899 default:
1900 return;
1901 }
1902 /* FIXME some of those reg can be computed with cso */
1903 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
1904 r600_pipe_state_add_reg(&state,
1905 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1906 fui(rctx->rasterizer->offset_scale), NULL, 0);
1907 r600_pipe_state_add_reg(&state,
1908 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1909 fui(offset_units), NULL, 0);
1910 r600_pipe_state_add_reg(&state,
1911 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1912 fui(rctx->rasterizer->offset_scale), NULL, 0);
1913 r600_pipe_state_add_reg(&state,
1914 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1915 fui(offset_units), NULL, 0);
1916 r600_pipe_state_add_reg(&state,
1917 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1918 offset_db_fmt_cntl, NULL, 0);
1919 r600_context_pipe_state_set(rctx, &state);
1920 }
1921 }
1922
1923 void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader)
1924 {
1925 struct r600_context *rctx = (struct r600_context *)ctx;
1926 struct r600_pipe_state *rstate = &shader->rstate;
1927 struct r600_shader *rshader = &shader->shader;
1928 unsigned i, exports_ps, num_cout, spi_ps_in_control, db_shader_control;
1929 unsigned num_sgprs, num_user_sgprs;
1930 int pos_index = -1, face_index = -1;
1931 int ninterp = 0;
1932 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
1933 unsigned spi_baryc_cntl;
1934 uint64_t va;
1935
1936 if (si_pipe_shader_create(ctx, shader))
1937 return;
1938
1939 rstate->nregs = 0;
1940
1941 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
1942 for (i = 0; i < rshader->ninput; i++) {
1943 ninterp++;
1944 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
1945 have_linear = TRUE;
1946 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
1947 have_perspective = TRUE;
1948 if (rshader->input[i].centroid)
1949 have_centroid = TRUE;
1950 }
1951
1952 for (i = 0; i < rshader->noutput; i++) {
1953 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1954 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
1955 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1956 db_shader_control |= 0; // XXX OP_VAL or TEST_VAL?
1957 }
1958 if (rshader->uses_kill)
1959 db_shader_control |= S_02880C_KILL_ENABLE(1);
1960
1961 exports_ps = 0;
1962 num_cout = 0;
1963 for (i = 0; i < rshader->noutput; i++) {
1964 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
1965 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1966 exports_ps |= 1;
1967 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
1968 if (rshader->fs_write_all)
1969 num_cout = rshader->nr_cbufs;
1970 else
1971 num_cout++;
1972 }
1973 }
1974 if (!exports_ps) {
1975 /* always at least export 1 component per pixel */
1976 exports_ps = 2;
1977 }
1978
1979 spi_ps_in_control = S_0286D8_NUM_INTERP(ninterp);
1980
1981 spi_baryc_cntl = 0;
1982 if (have_perspective)
1983 spi_baryc_cntl |= have_centroid ?
1984 S_0286E0_PERSP_CENTROID_CNTL(1) : S_0286E0_PERSP_CENTER_CNTL(1);
1985 if (have_linear)
1986 spi_baryc_cntl |= have_centroid ?
1987 S_0286E0_LINEAR_CENTROID_CNTL(1) : S_0286E0_LINEAR_CENTER_CNTL(1);
1988
1989 r600_pipe_state_add_reg(rstate,
1990 R_0286E0_SPI_BARYC_CNTL,
1991 spi_baryc_cntl,
1992 NULL, 0);
1993
1994 r600_pipe_state_add_reg(rstate,
1995 R_0286CC_SPI_PS_INPUT_ENA,
1996 shader->spi_ps_input_ena,
1997 NULL, 0);
1998
1999 r600_pipe_state_add_reg(rstate,
2000 R_0286D0_SPI_PS_INPUT_ADDR,
2001 shader->spi_ps_input_ena,
2002 NULL, 0);
2003
2004 r600_pipe_state_add_reg(rstate,
2005 R_0286D8_SPI_PS_IN_CONTROL,
2006 spi_ps_in_control,
2007 NULL, 0);
2008
2009 /* XXX: Depends on Z buffer format? */
2010 r600_pipe_state_add_reg(rstate,
2011 R_028710_SPI_SHADER_Z_FORMAT,
2012 0,
2013 NULL, 0);
2014
2015 /* XXX: Depends on color buffer format? */
2016 r600_pipe_state_add_reg(rstate,
2017 R_028714_SPI_SHADER_COL_FORMAT,
2018 S_028714_COL0_EXPORT_FORMAT(V_028714_SPI_SHADER_32_ABGR),
2019 NULL, 0);
2020
2021 va = r600_resource_va(ctx->screen, (void *)shader->bo);
2022 r600_pipe_state_add_reg(rstate,
2023 R_00B020_SPI_SHADER_PGM_LO_PS,
2024 va >> 8,
2025 shader->bo, RADEON_USAGE_READ);
2026 r600_pipe_state_add_reg(rstate,
2027 R_00B024_SPI_SHADER_PGM_HI_PS,
2028 va >> 40,
2029 shader->bo, RADEON_USAGE_READ);
2030
2031 num_user_sgprs = 6;
2032 num_sgprs = shader->num_sgprs;
2033 if (num_user_sgprs > num_sgprs)
2034 num_sgprs = num_user_sgprs;
2035 /* Last 2 reserved SGPRs are used for VCC */
2036 num_sgprs += 2;
2037 assert(num_sgprs <= 104);
2038
2039 r600_pipe_state_add_reg(rstate,
2040 R_00B028_SPI_SHADER_PGM_RSRC1_PS,
2041 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
2042 S_00B028_SGPRS((num_sgprs - 1) / 8),
2043 NULL, 0);
2044 r600_pipe_state_add_reg(rstate,
2045 R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
2046 S_00B02C_USER_SGPR(num_user_sgprs),
2047 NULL, 0);
2048
2049 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
2050 db_shader_control,
2051 NULL, 0);
2052
2053 shader->sprite_coord_enable = rctx->sprite_coord_enable;
2054 }
2055
2056 void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader)
2057 {
2058 struct r600_context *rctx = (struct r600_context *)ctx;
2059 struct r600_pipe_state *rstate = &shader->rstate;
2060 struct r600_shader *rshader = &shader->shader;
2061 unsigned num_sgprs, num_user_sgprs;
2062 unsigned nparams, i;
2063 uint64_t va;
2064
2065 if (si_pipe_shader_create(ctx, shader))
2066 return;
2067
2068 /* clear previous register */
2069 rstate->nregs = 0;
2070
2071 /* Certain attributes (position, psize, etc.) don't count as params.
2072 * VS is required to export at least one param and r600_shader_from_tgsi()
2073 * takes care of adding a dummy export.
2074 */
2075 for (nparams = 0, i = 0 ; i < rshader->noutput; i++) {
2076 if (rshader->output[i].name != TGSI_SEMANTIC_POSITION)
2077 nparams++;
2078 }
2079 if (nparams < 1)
2080 nparams = 1;
2081
2082 r600_pipe_state_add_reg(rstate,
2083 R_0286C4_SPI_VS_OUT_CONFIG,
2084 S_0286C4_VS_EXPORT_COUNT(nparams - 1),
2085 NULL, 0);
2086
2087 r600_pipe_state_add_reg(rstate,
2088 R_02870C_SPI_SHADER_POS_FORMAT,
2089 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
2090 S_02870C_POS1_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
2091 S_02870C_POS2_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
2092 S_02870C_POS3_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP),
2093 NULL, 0);
2094
2095 va = r600_resource_va(ctx->screen, (void *)shader->bo);
2096 r600_pipe_state_add_reg(rstate,
2097 R_00B120_SPI_SHADER_PGM_LO_VS,
2098 va >> 8,
2099 shader->bo, RADEON_USAGE_READ);
2100 r600_pipe_state_add_reg(rstate,
2101 R_00B124_SPI_SHADER_PGM_HI_VS,
2102 va >> 40,
2103 shader->bo, RADEON_USAGE_READ);
2104
2105 num_user_sgprs = 8;
2106 num_sgprs = shader->num_sgprs;
2107 if (num_user_sgprs > num_sgprs)
2108 num_sgprs = num_user_sgprs;
2109 /* Last 2 reserved SGPRs are used for VCC */
2110 num_sgprs += 2;
2111 assert(num_sgprs <= 104);
2112
2113 r600_pipe_state_add_reg(rstate,
2114 R_00B128_SPI_SHADER_PGM_RSRC1_VS,
2115 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
2116 S_00B128_SGPRS((num_sgprs - 1) / 8),
2117 NULL, 0);
2118 r600_pipe_state_add_reg(rstate,
2119 R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
2120 S_00B12C_USER_SGPR(num_user_sgprs),
2121 NULL, 0);
2122 }
2123
2124 void si_update_spi_map(struct r600_context *rctx)
2125 {
2126 struct r600_shader *ps = &rctx->ps_shader->shader;
2127 struct r600_shader *vs = &rctx->vs_shader->shader;
2128 struct r600_pipe_state *rstate = &rctx->spi;
2129 unsigned i, j, tmp;
2130
2131 rstate->nregs = 0;
2132
2133 for (i = 0; i < ps->ninput; i++) {
2134 tmp = 0;
2135
2136 if (ps->input[i].name == TGSI_SEMANTIC_COLOR ||
2137 ps->input[i].name == TGSI_SEMANTIC_BCOLOR ||
2138 ps->input[i].name == TGSI_SEMANTIC_POSITION) {
2139 tmp |= S_028644_FLAT_SHADE(1);
2140 }
2141
2142 if (ps->input[i].name == TGSI_SEMANTIC_GENERIC &&
2143 rctx->sprite_coord_enable & (1 << ps->input[i].sid)) {
2144 tmp |= S_028644_PT_SPRITE_TEX(1);
2145 }
2146
2147 for (j = 0; j < vs->noutput; j++) {
2148 if (ps->input[i].name == vs->output[j].name &&
2149 ps->input[i].sid == vs->output[j].sid) {
2150 tmp |= S_028644_OFFSET(ps->input[i].sid);
2151 break;
2152 }
2153 }
2154
2155 if (j == vs->noutput) {
2156 /* No corresponding output found, load defaults into input */
2157 tmp |= S_028644_OFFSET(0x20);
2158 }
2159
2160 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2161 tmp, NULL, 0);
2162 }
2163
2164 if (rstate->nregs > 0)
2165 r600_context_pipe_state_set(rctx, rstate);
2166 }
2167
2168 void *cayman_create_db_flush_dsa(struct r600_context *rctx)
2169 {
2170 struct pipe_depth_stencil_alpha_state dsa;
2171 struct r600_pipe_state *rstate;
2172
2173 memset(&dsa, 0, sizeof(dsa));
2174
2175 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2176 r600_pipe_state_add_reg(rstate,
2177 R_028000_DB_RENDER_CONTROL,
2178 S_028000_DEPTH_COPY(1) |
2179 S_028000_STENCIL_COPY(1) |
2180 S_028000_COPY_CENTROID(1),
2181 NULL, 0);
2182 return rstate;
2183 }