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[mesa.git] / src / gallium / drivers / radeonsi / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include "pipe/p_defines.h"
30 #include "pipe/p_state.h"
31 #include "pipe/p_context.h"
32 #include "tgsi/tgsi_scan.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_util.h"
35 #include "util/u_blitter.h"
36 #include "util/u_double_list.h"
37 #include "util/u_transfer.h"
38 #include "util/u_surface.h"
39 #include "util/u_pack_color.h"
40 #include "util/u_memory.h"
41 #include "util/u_inlines.h"
42 #include "util/u_framebuffer.h"
43 #include "pipebuffer/pb_buffer.h"
44 #include "r600.h"
45 #include "sid.h"
46 #include "r600_resource.h"
47 #include "radeonsi_pipe.h"
48
49 static uint32_t si_translate_blend_function(int blend_func)
50 {
51 switch (blend_func) {
52 case PIPE_BLEND_ADD:
53 return V_028780_COMB_DST_PLUS_SRC;
54 case PIPE_BLEND_SUBTRACT:
55 return V_028780_COMB_SRC_MINUS_DST;
56 case PIPE_BLEND_REVERSE_SUBTRACT:
57 return V_028780_COMB_DST_MINUS_SRC;
58 case PIPE_BLEND_MIN:
59 return V_028780_COMB_MIN_DST_SRC;
60 case PIPE_BLEND_MAX:
61 return V_028780_COMB_MAX_DST_SRC;
62 default:
63 R600_ERR("Unknown blend function %d\n", blend_func);
64 assert(0);
65 break;
66 }
67 return 0;
68 }
69
70 static uint32_t si_translate_blend_factor(int blend_fact)
71 {
72 switch (blend_fact) {
73 case PIPE_BLENDFACTOR_ONE:
74 return V_028780_BLEND_ONE;
75 case PIPE_BLENDFACTOR_SRC_COLOR:
76 return V_028780_BLEND_SRC_COLOR;
77 case PIPE_BLENDFACTOR_SRC_ALPHA:
78 return V_028780_BLEND_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_DST_ALPHA:
80 return V_028780_BLEND_DST_ALPHA;
81 case PIPE_BLENDFACTOR_DST_COLOR:
82 return V_028780_BLEND_DST_COLOR;
83 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
84 return V_028780_BLEND_SRC_ALPHA_SATURATE;
85 case PIPE_BLENDFACTOR_CONST_COLOR:
86 return V_028780_BLEND_CONSTANT_COLOR;
87 case PIPE_BLENDFACTOR_CONST_ALPHA:
88 return V_028780_BLEND_CONSTANT_ALPHA;
89 case PIPE_BLENDFACTOR_ZERO:
90 return V_028780_BLEND_ZERO;
91 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
92 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
94 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
95 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
96 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
97 case PIPE_BLENDFACTOR_INV_DST_COLOR:
98 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
99 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
100 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
101 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
102 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
103 case PIPE_BLENDFACTOR_SRC1_COLOR:
104 return V_028780_BLEND_SRC1_COLOR;
105 case PIPE_BLENDFACTOR_SRC1_ALPHA:
106 return V_028780_BLEND_SRC1_ALPHA;
107 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
108 return V_028780_BLEND_INV_SRC1_COLOR;
109 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
110 return V_028780_BLEND_INV_SRC1_ALPHA;
111 default:
112 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
113 assert(0);
114 break;
115 }
116 return 0;
117 }
118
119 #if 0
120 static uint32_t r600_translate_stencil_op(int s_op)
121 {
122 switch (s_op) {
123 case PIPE_STENCIL_OP_KEEP:
124 return V_028800_STENCIL_KEEP;
125 case PIPE_STENCIL_OP_ZERO:
126 return V_028800_STENCIL_ZERO;
127 case PIPE_STENCIL_OP_REPLACE:
128 return V_028800_STENCIL_REPLACE;
129 case PIPE_STENCIL_OP_INCR:
130 return V_028800_STENCIL_INCR;
131 case PIPE_STENCIL_OP_DECR:
132 return V_028800_STENCIL_DECR;
133 case PIPE_STENCIL_OP_INCR_WRAP:
134 return V_028800_STENCIL_INCR_WRAP;
135 case PIPE_STENCIL_OP_DECR_WRAP:
136 return V_028800_STENCIL_DECR_WRAP;
137 case PIPE_STENCIL_OP_INVERT:
138 return V_028800_STENCIL_INVERT;
139 default:
140 R600_ERR("Unknown stencil op %d", s_op);
141 assert(0);
142 break;
143 }
144 return 0;
145 }
146 #endif
147
148 static uint32_t si_translate_fill(uint32_t func)
149 {
150 switch(func) {
151 case PIPE_POLYGON_MODE_FILL:
152 return V_028814_X_DRAW_TRIANGLES;
153 case PIPE_POLYGON_MODE_LINE:
154 return V_028814_X_DRAW_LINES;
155 case PIPE_POLYGON_MODE_POINT:
156 return V_028814_X_DRAW_POINTS;
157 default:
158 assert(0);
159 return V_028814_X_DRAW_POINTS;
160 }
161 }
162
163 /* translates straight */
164 static uint32_t si_translate_ds_func(int func)
165 {
166 return func;
167 }
168
169 static unsigned si_tex_wrap(unsigned wrap)
170 {
171 switch (wrap) {
172 default:
173 case PIPE_TEX_WRAP_REPEAT:
174 return V_008F30_SQ_TEX_WRAP;
175 case PIPE_TEX_WRAP_CLAMP:
176 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
177 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
178 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
179 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
180 return V_008F30_SQ_TEX_CLAMP_BORDER;
181 case PIPE_TEX_WRAP_MIRROR_REPEAT:
182 return V_008F30_SQ_TEX_MIRROR;
183 case PIPE_TEX_WRAP_MIRROR_CLAMP:
184 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
185 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
186 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
187 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
188 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
189 }
190 }
191
192 static unsigned si_tex_filter(unsigned filter)
193 {
194 switch (filter) {
195 default:
196 case PIPE_TEX_FILTER_NEAREST:
197 return V_008F38_SQ_TEX_XY_FILTER_POINT;
198 case PIPE_TEX_FILTER_LINEAR:
199 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
200 }
201 }
202
203 static unsigned si_tex_mipfilter(unsigned filter)
204 {
205 switch (filter) {
206 case PIPE_TEX_MIPFILTER_NEAREST:
207 return V_008F38_SQ_TEX_Z_FILTER_POINT;
208 case PIPE_TEX_MIPFILTER_LINEAR:
209 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
210 default:
211 case PIPE_TEX_MIPFILTER_NONE:
212 return V_008F38_SQ_TEX_Z_FILTER_NONE;
213 }
214 }
215
216 static unsigned si_tex_compare(unsigned compare)
217 {
218 switch (compare) {
219 default:
220 case PIPE_FUNC_NEVER:
221 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
222 case PIPE_FUNC_LESS:
223 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
224 case PIPE_FUNC_EQUAL:
225 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
226 case PIPE_FUNC_LEQUAL:
227 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
228 case PIPE_FUNC_GREATER:
229 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
230 case PIPE_FUNC_NOTEQUAL:
231 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
232 case PIPE_FUNC_GEQUAL:
233 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
234 case PIPE_FUNC_ALWAYS:
235 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
236 }
237 }
238
239 static unsigned si_tex_dim(unsigned dim)
240 {
241 switch (dim) {
242 default:
243 case PIPE_TEXTURE_1D:
244 return V_008F1C_SQ_RSRC_IMG_1D;
245 case PIPE_TEXTURE_1D_ARRAY:
246 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
247 case PIPE_TEXTURE_2D:
248 case PIPE_TEXTURE_RECT:
249 return V_008F1C_SQ_RSRC_IMG_2D;
250 case PIPE_TEXTURE_2D_ARRAY:
251 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
252 case PIPE_TEXTURE_3D:
253 return V_008F1C_SQ_RSRC_IMG_3D;
254 case PIPE_TEXTURE_CUBE:
255 return V_008F1C_SQ_RSRC_IMG_CUBE;
256 }
257 }
258
259 static uint32_t si_translate_dbformat(enum pipe_format format)
260 {
261 switch (format) {
262 case PIPE_FORMAT_Z16_UNORM:
263 return V_028040_Z_16;
264 case PIPE_FORMAT_Z24X8_UNORM:
265 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
266 return V_028040_Z_24; /* XXX no longer supported on SI */
267 case PIPE_FORMAT_Z32_FLOAT:
268 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
269 return V_028040_Z_32_FLOAT;
270 default:
271 return ~0U;
272 }
273 }
274
275 static uint32_t si_translate_colorswap(enum pipe_format format)
276 {
277 switch (format) {
278 /* 8-bit buffers. */
279 case PIPE_FORMAT_L4A4_UNORM:
280 case PIPE_FORMAT_A4R4_UNORM:
281 return V_028C70_SWAP_ALT;
282
283 case PIPE_FORMAT_A8_UNORM:
284 case PIPE_FORMAT_A8_UINT:
285 case PIPE_FORMAT_A8_SINT:
286 case PIPE_FORMAT_R4A4_UNORM:
287 return V_028C70_SWAP_ALT_REV;
288 case PIPE_FORMAT_I8_UNORM:
289 case PIPE_FORMAT_L8_UNORM:
290 case PIPE_FORMAT_I8_UINT:
291 case PIPE_FORMAT_I8_SINT:
292 case PIPE_FORMAT_L8_UINT:
293 case PIPE_FORMAT_L8_SINT:
294 case PIPE_FORMAT_L8_SRGB:
295 case PIPE_FORMAT_R8_UNORM:
296 case PIPE_FORMAT_R8_SNORM:
297 case PIPE_FORMAT_R8_UINT:
298 case PIPE_FORMAT_R8_SINT:
299 return V_028C70_SWAP_STD;
300
301 /* 16-bit buffers. */
302 case PIPE_FORMAT_B5G6R5_UNORM:
303 return V_028C70_SWAP_STD_REV;
304
305 case PIPE_FORMAT_B5G5R5A1_UNORM:
306 case PIPE_FORMAT_B5G5R5X1_UNORM:
307 return V_028C70_SWAP_ALT;
308
309 case PIPE_FORMAT_B4G4R4A4_UNORM:
310 case PIPE_FORMAT_B4G4R4X4_UNORM:
311 return V_028C70_SWAP_ALT;
312
313 case PIPE_FORMAT_Z16_UNORM:
314 return V_028C70_SWAP_STD;
315
316 case PIPE_FORMAT_L8A8_UNORM:
317 case PIPE_FORMAT_L8A8_UINT:
318 case PIPE_FORMAT_L8A8_SINT:
319 case PIPE_FORMAT_L8A8_SRGB:
320 return V_028C70_SWAP_ALT;
321 case PIPE_FORMAT_R8G8_UNORM:
322 case PIPE_FORMAT_R8G8_UINT:
323 case PIPE_FORMAT_R8G8_SINT:
324 return V_028C70_SWAP_STD;
325
326 case PIPE_FORMAT_R16_UNORM:
327 case PIPE_FORMAT_R16_UINT:
328 case PIPE_FORMAT_R16_SINT:
329 case PIPE_FORMAT_R16_FLOAT:
330 return V_028C70_SWAP_STD;
331
332 /* 32-bit buffers. */
333 case PIPE_FORMAT_A8B8G8R8_SRGB:
334 return V_028C70_SWAP_STD_REV;
335 case PIPE_FORMAT_B8G8R8A8_SRGB:
336 return V_028C70_SWAP_ALT;
337
338 case PIPE_FORMAT_B8G8R8A8_UNORM:
339 case PIPE_FORMAT_B8G8R8X8_UNORM:
340 return V_028C70_SWAP_ALT;
341
342 case PIPE_FORMAT_A8R8G8B8_UNORM:
343 case PIPE_FORMAT_X8R8G8B8_UNORM:
344 return V_028C70_SWAP_ALT_REV;
345 case PIPE_FORMAT_R8G8B8A8_SNORM:
346 case PIPE_FORMAT_R8G8B8A8_UNORM:
347 case PIPE_FORMAT_R8G8B8A8_SSCALED:
348 case PIPE_FORMAT_R8G8B8A8_USCALED:
349 case PIPE_FORMAT_R8G8B8A8_SINT:
350 case PIPE_FORMAT_R8G8B8A8_UINT:
351 case PIPE_FORMAT_R8G8B8X8_UNORM:
352 return V_028C70_SWAP_STD;
353
354 case PIPE_FORMAT_A8B8G8R8_UNORM:
355 case PIPE_FORMAT_X8B8G8R8_UNORM:
356 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
357 return V_028C70_SWAP_STD_REV;
358
359 case PIPE_FORMAT_Z24X8_UNORM:
360 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
361 return V_028C70_SWAP_STD;
362
363 case PIPE_FORMAT_X8Z24_UNORM:
364 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
365 return V_028C70_SWAP_STD;
366
367 case PIPE_FORMAT_R10G10B10A2_UNORM:
368 case PIPE_FORMAT_R10G10B10X2_SNORM:
369 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
370 return V_028C70_SWAP_STD;
371
372 case PIPE_FORMAT_B10G10R10A2_UNORM:
373 case PIPE_FORMAT_B10G10R10A2_UINT:
374 return V_028C70_SWAP_ALT;
375
376 case PIPE_FORMAT_R11G11B10_FLOAT:
377 case PIPE_FORMAT_R32_FLOAT:
378 case PIPE_FORMAT_R32_UINT:
379 case PIPE_FORMAT_R32_SINT:
380 case PIPE_FORMAT_Z32_FLOAT:
381 case PIPE_FORMAT_R16G16_FLOAT:
382 case PIPE_FORMAT_R16G16_UNORM:
383 case PIPE_FORMAT_R16G16_UINT:
384 case PIPE_FORMAT_R16G16_SINT:
385 return V_028C70_SWAP_STD;
386
387 /* 64-bit buffers. */
388 case PIPE_FORMAT_R32G32_FLOAT:
389 case PIPE_FORMAT_R32G32_UINT:
390 case PIPE_FORMAT_R32G32_SINT:
391 case PIPE_FORMAT_R16G16B16A16_UNORM:
392 case PIPE_FORMAT_R16G16B16A16_SNORM:
393 case PIPE_FORMAT_R16G16B16A16_USCALED:
394 case PIPE_FORMAT_R16G16B16A16_SSCALED:
395 case PIPE_FORMAT_R16G16B16A16_UINT:
396 case PIPE_FORMAT_R16G16B16A16_SINT:
397 case PIPE_FORMAT_R16G16B16A16_FLOAT:
398 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
399
400 /* 128-bit buffers. */
401 case PIPE_FORMAT_R32G32B32A32_FLOAT:
402 case PIPE_FORMAT_R32G32B32A32_SNORM:
403 case PIPE_FORMAT_R32G32B32A32_UNORM:
404 case PIPE_FORMAT_R32G32B32A32_SSCALED:
405 case PIPE_FORMAT_R32G32B32A32_USCALED:
406 case PIPE_FORMAT_R32G32B32A32_SINT:
407 case PIPE_FORMAT_R32G32B32A32_UINT:
408 return V_028C70_SWAP_STD;
409 default:
410 R600_ERR("unsupported colorswap format %d\n", format);
411 return ~0U;
412 }
413 return ~0U;
414 }
415
416 static uint32_t si_translate_colorformat(enum pipe_format format)
417 {
418 switch (format) {
419 /* 8-bit buffers. */
420 case PIPE_FORMAT_A8_UNORM:
421 case PIPE_FORMAT_A8_UINT:
422 case PIPE_FORMAT_A8_SINT:
423 case PIPE_FORMAT_I8_UNORM:
424 case PIPE_FORMAT_I8_UINT:
425 case PIPE_FORMAT_I8_SINT:
426 case PIPE_FORMAT_L8_UNORM:
427 case PIPE_FORMAT_L8_UINT:
428 case PIPE_FORMAT_L8_SINT:
429 case PIPE_FORMAT_L8_SRGB:
430 case PIPE_FORMAT_R8_UNORM:
431 case PIPE_FORMAT_R8_SNORM:
432 case PIPE_FORMAT_R8_UINT:
433 case PIPE_FORMAT_R8_SINT:
434 return V_028C70_COLOR_8;
435
436 /* 16-bit buffers. */
437 case PIPE_FORMAT_B5G6R5_UNORM:
438 return V_028C70_COLOR_5_6_5;
439
440 case PIPE_FORMAT_B5G5R5A1_UNORM:
441 case PIPE_FORMAT_B5G5R5X1_UNORM:
442 return V_028C70_COLOR_1_5_5_5;
443
444 case PIPE_FORMAT_B4G4R4A4_UNORM:
445 case PIPE_FORMAT_B4G4R4X4_UNORM:
446 return V_028C70_COLOR_4_4_4_4;
447
448 case PIPE_FORMAT_L8A8_UNORM:
449 case PIPE_FORMAT_L8A8_UINT:
450 case PIPE_FORMAT_L8A8_SINT:
451 case PIPE_FORMAT_L8A8_SRGB:
452 case PIPE_FORMAT_R8G8_UNORM:
453 case PIPE_FORMAT_R8G8_UINT:
454 case PIPE_FORMAT_R8G8_SINT:
455 return V_028C70_COLOR_8_8;
456
457 case PIPE_FORMAT_Z16_UNORM:
458 case PIPE_FORMAT_R16_UNORM:
459 case PIPE_FORMAT_R16_UINT:
460 case PIPE_FORMAT_R16_SINT:
461 case PIPE_FORMAT_R16_FLOAT:
462 case PIPE_FORMAT_R16G16_FLOAT:
463 return V_028C70_COLOR_16;
464
465 /* 32-bit buffers. */
466 case PIPE_FORMAT_A8B8G8R8_SRGB:
467 case PIPE_FORMAT_A8B8G8R8_UNORM:
468 case PIPE_FORMAT_A8R8G8B8_UNORM:
469 case PIPE_FORMAT_B8G8R8A8_SRGB:
470 case PIPE_FORMAT_B8G8R8A8_UNORM:
471 case PIPE_FORMAT_B8G8R8X8_UNORM:
472 case PIPE_FORMAT_R8G8B8A8_SNORM:
473 case PIPE_FORMAT_R8G8B8A8_UNORM:
474 case PIPE_FORMAT_R8G8B8X8_UNORM:
475 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
476 case PIPE_FORMAT_X8B8G8R8_UNORM:
477 case PIPE_FORMAT_X8R8G8B8_UNORM:
478 case PIPE_FORMAT_R8G8B8_UNORM:
479 case PIPE_FORMAT_R8G8B8A8_SSCALED:
480 case PIPE_FORMAT_R8G8B8A8_USCALED:
481 case PIPE_FORMAT_R8G8B8A8_SINT:
482 case PIPE_FORMAT_R8G8B8A8_UINT:
483 return V_028C70_COLOR_8_8_8_8;
484
485 case PIPE_FORMAT_R10G10B10A2_UNORM:
486 case PIPE_FORMAT_R10G10B10X2_SNORM:
487 case PIPE_FORMAT_B10G10R10A2_UNORM:
488 case PIPE_FORMAT_B10G10R10A2_UINT:
489 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
490 return V_028C70_COLOR_2_10_10_10;
491
492 case PIPE_FORMAT_Z24X8_UNORM:
493 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
494 return V_028C70_COLOR_8_24;
495
496 case PIPE_FORMAT_X8Z24_UNORM:
497 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
498 return V_028C70_COLOR_24_8;
499
500 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
501 return V_028C70_COLOR_X24_8_32_FLOAT;
502
503 case PIPE_FORMAT_R32_FLOAT:
504 case PIPE_FORMAT_Z32_FLOAT:
505 return V_028C70_COLOR_32;
506
507 case PIPE_FORMAT_R16G16_SSCALED:
508 case PIPE_FORMAT_R16G16_UNORM:
509 case PIPE_FORMAT_R16G16_UINT:
510 case PIPE_FORMAT_R16G16_SINT:
511 return V_028C70_COLOR_16_16;
512
513 case PIPE_FORMAT_R11G11B10_FLOAT:
514 return V_028C70_COLOR_10_11_11;
515
516 /* 64-bit buffers. */
517 case PIPE_FORMAT_R16G16B16_USCALED:
518 case PIPE_FORMAT_R16G16B16_SSCALED:
519 case PIPE_FORMAT_R16G16B16A16_UINT:
520 case PIPE_FORMAT_R16G16B16A16_SINT:
521 case PIPE_FORMAT_R16G16B16A16_USCALED:
522 case PIPE_FORMAT_R16G16B16A16_SSCALED:
523 case PIPE_FORMAT_R16G16B16A16_UNORM:
524 case PIPE_FORMAT_R16G16B16A16_SNORM:
525 case PIPE_FORMAT_R16G16B16_FLOAT:
526 case PIPE_FORMAT_R16G16B16A16_FLOAT:
527 return V_028C70_COLOR_16_16_16_16;
528
529 case PIPE_FORMAT_R32G32_FLOAT:
530 case PIPE_FORMAT_R32G32_USCALED:
531 case PIPE_FORMAT_R32G32_SSCALED:
532 case PIPE_FORMAT_R32G32_SINT:
533 case PIPE_FORMAT_R32G32_UINT:
534 return V_028C70_COLOR_32_32;
535
536 /* 128-bit buffers. */
537 case PIPE_FORMAT_R32G32B32A32_SNORM:
538 case PIPE_FORMAT_R32G32B32A32_UNORM:
539 case PIPE_FORMAT_R32G32B32A32_SSCALED:
540 case PIPE_FORMAT_R32G32B32A32_USCALED:
541 case PIPE_FORMAT_R32G32B32A32_SINT:
542 case PIPE_FORMAT_R32G32B32A32_UINT:
543 case PIPE_FORMAT_R32G32B32A32_FLOAT:
544 return V_028C70_COLOR_32_32_32_32;
545
546 /* YUV buffers. */
547 case PIPE_FORMAT_UYVY:
548 case PIPE_FORMAT_YUYV:
549 /* 96-bit buffers. */
550 case PIPE_FORMAT_R32G32B32_FLOAT:
551 /* 8-bit buffers. */
552 case PIPE_FORMAT_L4A4_UNORM:
553 case PIPE_FORMAT_R4A4_UNORM:
554 case PIPE_FORMAT_A4R4_UNORM:
555 default:
556 return ~0U; /* Unsupported. */
557 }
558 }
559
560 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
561 {
562 if (R600_BIG_ENDIAN) {
563 switch(colorformat) {
564 /* 8-bit buffers. */
565 case V_028C70_COLOR_8:
566 return V_028C70_ENDIAN_NONE;
567
568 /* 16-bit buffers. */
569 case V_028C70_COLOR_5_6_5:
570 case V_028C70_COLOR_1_5_5_5:
571 case V_028C70_COLOR_4_4_4_4:
572 case V_028C70_COLOR_16:
573 case V_028C70_COLOR_8_8:
574 return V_028C70_ENDIAN_8IN16;
575
576 /* 32-bit buffers. */
577 case V_028C70_COLOR_8_8_8_8:
578 case V_028C70_COLOR_2_10_10_10:
579 case V_028C70_COLOR_8_24:
580 case V_028C70_COLOR_24_8:
581 case V_028C70_COLOR_16_16:
582 return V_028C70_ENDIAN_8IN32;
583
584 /* 64-bit buffers. */
585 case V_028C70_COLOR_16_16_16_16:
586 return V_028C70_ENDIAN_8IN16;
587
588 case V_028C70_COLOR_32_32:
589 return V_028C70_ENDIAN_8IN32;
590
591 /* 128-bit buffers. */
592 case V_028C70_COLOR_32_32_32_32:
593 return V_028C70_ENDIAN_8IN32;
594 default:
595 return V_028C70_ENDIAN_NONE; /* Unsupported. */
596 }
597 } else {
598 return V_028C70_ENDIAN_NONE;
599 }
600 }
601
602 static uint32_t si_translate_texformat(struct pipe_screen *screen,
603 enum pipe_format format,
604 const struct util_format_description *desc,
605 int first_non_void)
606 {
607 boolean uniform = TRUE;
608 int i;
609
610 /* Colorspace (return non-RGB formats directly). */
611 switch (desc->colorspace) {
612 /* Depth stencil formats */
613 case UTIL_FORMAT_COLORSPACE_ZS:
614 switch (format) {
615 case PIPE_FORMAT_Z16_UNORM:
616 return V_008F14_IMG_DATA_FORMAT_16;
617 case PIPE_FORMAT_X24S8_UINT:
618 case PIPE_FORMAT_Z24X8_UNORM:
619 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
620 return V_008F14_IMG_DATA_FORMAT_24_8;
621 case PIPE_FORMAT_S8X24_UINT:
622 case PIPE_FORMAT_X8Z24_UNORM:
623 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
624 return V_008F14_IMG_DATA_FORMAT_8_24;
625 case PIPE_FORMAT_S8_UINT:
626 return V_008F14_IMG_DATA_FORMAT_8;
627 case PIPE_FORMAT_Z32_FLOAT:
628 return V_008F14_IMG_DATA_FORMAT_32;
629 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
630 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
631 default:
632 goto out_unknown;
633 }
634
635 case UTIL_FORMAT_COLORSPACE_YUV:
636 goto out_unknown; /* TODO */
637
638 case UTIL_FORMAT_COLORSPACE_SRGB:
639 break;
640
641 default:
642 break;
643 }
644
645 /* TODO compressed formats */
646
647 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
648 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
649 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
650 return V_008F14_IMG_DATA_FORMAT_10_11_11;
651 }
652
653 /* R8G8Bx_SNORM - TODO CxV8U8 */
654
655 /* See whether the components are of the same size. */
656 for (i = 1; i < desc->nr_channels; i++) {
657 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
658 }
659
660 /* Non-uniform formats. */
661 if (!uniform) {
662 switch(desc->nr_channels) {
663 case 3:
664 if (desc->channel[0].size == 5 &&
665 desc->channel[1].size == 6 &&
666 desc->channel[2].size == 5) {
667 return V_008F14_IMG_DATA_FORMAT_5_6_5;
668 }
669 goto out_unknown;
670 case 4:
671 if (desc->channel[0].size == 5 &&
672 desc->channel[1].size == 5 &&
673 desc->channel[2].size == 5 &&
674 desc->channel[3].size == 1) {
675 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
676 }
677 if (desc->channel[0].size == 10 &&
678 desc->channel[1].size == 10 &&
679 desc->channel[2].size == 10 &&
680 desc->channel[3].size == 2) {
681 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
682 }
683 goto out_unknown;
684 }
685 goto out_unknown;
686 }
687
688 if (first_non_void < 0 || first_non_void > 3)
689 goto out_unknown;
690
691 /* uniform formats */
692 switch (desc->channel[first_non_void].size) {
693 case 4:
694 switch (desc->nr_channels) {
695 case 2:
696 return V_008F14_IMG_DATA_FORMAT_4_4;
697 case 4:
698 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
699 }
700 break;
701 case 8:
702 switch (desc->nr_channels) {
703 case 1:
704 return V_008F14_IMG_DATA_FORMAT_8;
705 case 2:
706 return V_008F14_IMG_DATA_FORMAT_8_8;
707 case 4:
708 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
709 }
710 break;
711 case 16:
712 switch (desc->nr_channels) {
713 case 1:
714 return V_008F14_IMG_DATA_FORMAT_16;
715 case 2:
716 return V_008F14_IMG_DATA_FORMAT_16_16;
717 case 4:
718 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
719 }
720 break;
721 case 32:
722 switch (desc->nr_channels) {
723 case 1:
724 return V_008F14_IMG_DATA_FORMAT_32;
725 case 2:
726 return V_008F14_IMG_DATA_FORMAT_32_32;
727 case 3:
728 return V_008F14_IMG_DATA_FORMAT_32_32_32;
729 case 4:
730 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
731 }
732 }
733
734 out_unknown:
735 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
736 return ~0;
737 }
738
739 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
740 {
741 return si_translate_texformat(screen, format, util_format_description(format),
742 util_format_get_first_non_void_channel(format)) != ~0U;
743 }
744
745 uint32_t si_translate_vertexformat(struct pipe_screen *screen,
746 enum pipe_format format,
747 const struct util_format_description *desc,
748 int first_non_void)
749 {
750 uint32_t result;
751
752 if (desc->channel[first_non_void].type == UTIL_FORMAT_TYPE_FIXED)
753 return ~0;
754
755 result = si_translate_texformat(screen, format, desc, first_non_void);
756 if (result == V_008F0C_BUF_DATA_FORMAT_INVALID ||
757 result > V_008F0C_BUF_DATA_FORMAT_32_32_32_32)
758 result = ~0;
759
760 return result;
761 }
762
763 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
764 {
765 return si_translate_vertexformat(screen, format, util_format_description(format),
766 util_format_get_first_non_void_channel(format)) != ~0U;
767 }
768
769 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
770 {
771 return si_translate_colorformat(format) != ~0U &&
772 si_translate_colorswap(format) != ~0U;
773 }
774
775 static bool r600_is_zs_format_supported(enum pipe_format format)
776 {
777 return si_translate_dbformat(format) != ~0U;
778 }
779
780 boolean si_is_format_supported(struct pipe_screen *screen,
781 enum pipe_format format,
782 enum pipe_texture_target target,
783 unsigned sample_count,
784 unsigned usage)
785 {
786 unsigned retval = 0;
787
788 if (target >= PIPE_MAX_TEXTURE_TYPES) {
789 R600_ERR("r600: unsupported texture type %d\n", target);
790 return FALSE;
791 }
792
793 if (!util_format_is_supported(format, usage))
794 return FALSE;
795
796 /* Multisample */
797 if (sample_count > 1)
798 return FALSE;
799
800 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
801 si_is_sampler_format_supported(screen, format)) {
802 retval |= PIPE_BIND_SAMPLER_VIEW;
803 }
804
805 if ((usage & (PIPE_BIND_RENDER_TARGET |
806 PIPE_BIND_DISPLAY_TARGET |
807 PIPE_BIND_SCANOUT |
808 PIPE_BIND_SHARED)) &&
809 r600_is_colorbuffer_format_supported(format)) {
810 retval |= usage &
811 (PIPE_BIND_RENDER_TARGET |
812 PIPE_BIND_DISPLAY_TARGET |
813 PIPE_BIND_SCANOUT |
814 PIPE_BIND_SHARED);
815 }
816
817 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
818 r600_is_zs_format_supported(format)) {
819 retval |= PIPE_BIND_DEPTH_STENCIL;
820 }
821
822 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
823 si_is_vertex_format_supported(screen, format)) {
824 retval |= PIPE_BIND_VERTEX_BUFFER;
825 }
826
827 if (usage & PIPE_BIND_TRANSFER_READ)
828 retval |= PIPE_BIND_TRANSFER_READ;
829 if (usage & PIPE_BIND_TRANSFER_WRITE)
830 retval |= PIPE_BIND_TRANSFER_WRITE;
831
832 return retval == usage;
833 }
834
835 static void evergreen_set_blend_color(struct pipe_context *ctx,
836 const struct pipe_blend_color *state)
837 {
838 struct r600_context *rctx = (struct r600_context *)ctx;
839 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
840
841 if (rstate == NULL)
842 return;
843
844 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
845 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), NULL, 0);
846 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), NULL, 0);
847 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), NULL, 0);
848 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), NULL, 0);
849
850 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
851 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
852 r600_context_pipe_state_set(rctx, rstate);
853 }
854
855 static void *evergreen_create_blend_state(struct pipe_context *ctx,
856 const struct pipe_blend_state *state)
857 {
858 struct r600_context *rctx = (struct r600_context *)ctx;
859 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
860 struct r600_pipe_state *rstate;
861 uint32_t color_control, target_mask;
862 /* FIXME there is more then 8 framebuffer */
863 unsigned blend_cntl[8];
864
865 if (blend == NULL) {
866 return NULL;
867 }
868
869 rstate = &blend->rstate;
870
871 rstate->id = R600_PIPE_STATE_BLEND;
872
873 target_mask = 0;
874 color_control = S_028808_MODE(V_028808_CB_NORMAL);
875 if (state->logicop_enable) {
876 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
877 } else {
878 color_control |= S_028808_ROP3(0xcc);
879 }
880 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
881 if (state->independent_blend_enable) {
882 for (int i = 0; i < 8; i++) {
883 target_mask |= (state->rt[i].colormask << (4 * i));
884 }
885 } else {
886 for (int i = 0; i < 8; i++) {
887 target_mask |= (state->rt[0].colormask << (4 * i));
888 }
889 }
890 blend->cb_target_mask = target_mask;
891
892 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
893 color_control, NULL, 0);
894
895 r600_pipe_state_add_reg(rstate, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, ~0, NULL, 0);
896 r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, ~0, NULL, 0);
897
898 for (int i = 0; i < 8; i++) {
899 /* state->rt entries > 0 only written if independent blending */
900 const int j = state->independent_blend_enable ? i : 0;
901
902 unsigned eqRGB = state->rt[j].rgb_func;
903 unsigned srcRGB = state->rt[j].rgb_src_factor;
904 unsigned dstRGB = state->rt[j].rgb_dst_factor;
905 unsigned eqA = state->rt[j].alpha_func;
906 unsigned srcA = state->rt[j].alpha_src_factor;
907 unsigned dstA = state->rt[j].alpha_dst_factor;
908
909 blend_cntl[i] = 0;
910 if (!state->rt[j].blend_enable)
911 continue;
912
913 blend_cntl[i] |= S_028780_ENABLE(1);
914 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
915 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
916 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
917
918 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
919 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
920 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
921 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
922 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
923 }
924 }
925 for (int i = 0; i < 8; i++) {
926 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], NULL, 0);
927 }
928
929 return rstate;
930 }
931
932 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
933 const struct pipe_depth_stencil_alpha_state *state)
934 {
935 struct r600_context *rctx = (struct r600_context *)ctx;
936 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
937 unsigned db_depth_control, alpha_test_control, alpha_ref;
938 unsigned db_render_override, db_render_control;
939 struct r600_pipe_state *rstate;
940
941 if (dsa == NULL) {
942 return NULL;
943 }
944
945 dsa->valuemask[0] = state->stencil[0].valuemask;
946 dsa->valuemask[1] = state->stencil[1].valuemask;
947 dsa->writemask[0] = state->stencil[0].writemask;
948 dsa->writemask[1] = state->stencil[1].writemask;
949
950 rstate = &dsa->rstate;
951
952 rstate->id = R600_PIPE_STATE_DSA;
953 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
954 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
955 S_028800_ZFUNC(state->depth.func);
956
957 /* stencil */
958 if (state->stencil[0].enabled) {
959 db_depth_control |= S_028800_STENCIL_ENABLE(1);
960 db_depth_control |= S_028800_STENCILFUNC(si_translate_ds_func(state->stencil[0].func));
961 //db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
962 //db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
963 //db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
964
965 if (state->stencil[1].enabled) {
966 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
967 db_depth_control |= S_028800_STENCILFUNC_BF(si_translate_ds_func(state->stencil[1].func));
968 //db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
969 //db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
970 //db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
971 }
972 }
973
974 /* alpha */
975 alpha_test_control = 0;
976 alpha_ref = 0;
977 if (state->alpha.enabled) {
978 //alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
979 //alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
980 alpha_ref = fui(state->alpha.ref_value);
981 }
982 dsa->alpha_ref = alpha_ref;
983
984 /* misc */
985 db_render_control = 0;
986 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
987 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
988 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
989 /* TODO db_render_override depends on query */
990 r600_pipe_state_add_reg(rstate, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000, NULL, 0);
991 r600_pipe_state_add_reg(rstate, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000, NULL, 0);
992 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, NULL, 0);
993 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, NULL, 0);
994 //r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, NULL, 0);
995 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, NULL, 0);
996 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, NULL, 0);
997 r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, NULL, 0);
998 r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, NULL, 0);
999 r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, NULL, 0);
1000 r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, NULL, 0);
1001 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, NULL, 0);
1002 dsa->db_render_override = db_render_override;
1003
1004 return rstate;
1005 }
1006
1007 static void *evergreen_create_rs_state(struct pipe_context *ctx,
1008 const struct pipe_rasterizer_state *state)
1009 {
1010 struct r600_context *rctx = (struct r600_context *)ctx;
1011 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
1012 struct r600_pipe_state *rstate;
1013 unsigned tmp;
1014 unsigned prov_vtx = 1, polygon_dual_mode;
1015 unsigned clip_rule;
1016 float psize_min, psize_max;
1017
1018 if (rs == NULL) {
1019 return NULL;
1020 }
1021
1022 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
1023 state->fill_back != PIPE_POLYGON_MODE_FILL);
1024
1025 if (state->flatshade_first)
1026 prov_vtx = 0;
1027
1028 rstate = &rs->rstate;
1029 rs->flatshade = state->flatshade;
1030 rs->sprite_coord_enable = state->sprite_coord_enable;
1031 rs->pa_sc_line_stipple = state->line_stipple_enable ?
1032 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
1033 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
1034 rs->pa_su_sc_mode_cntl =
1035 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
1036 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
1037 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
1038 S_028814_FACE(!state->front_ccw) |
1039 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
1040 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
1041 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
1042 S_028814_POLY_MODE(polygon_dual_mode) |
1043 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
1044 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
1045 rs->pa_cl_clip_cntl =
1046 S_028810_PS_UCP_MODE(3) |
1047 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
1048 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
1049 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1050 rs->pa_cl_vs_out_cntl =
1051 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
1052 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
1053
1054 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
1055
1056 /* offset */
1057 rs->offset_units = state->offset_units;
1058 rs->offset_scale = state->offset_scale * 12.0f;
1059
1060 rstate->id = R600_PIPE_STATE_RASTERIZER;
1061 /* XXX: Flat shading hangs the GPU */
1062 tmp = S_0286D4_FLAT_SHADE_ENA(0);
1063 if (state->sprite_coord_enable) {
1064 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
1065 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1066 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1067 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1068 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
1069 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
1070 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
1071 }
1072 }
1073 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, NULL, 0);
1074
1075 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, NULL, 0);
1076 /* point size 12.4 fixed point */
1077 tmp = (unsigned)(state->point_size * 8.0);
1078 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), NULL, 0);
1079
1080 if (state->point_size_per_vertex) {
1081 psize_min = util_get_min_point_size(state);
1082 psize_max = 8192;
1083 } else {
1084 /* Force the point size to be as if the vertex output was disabled. */
1085 psize_min = state->point_size;
1086 psize_max = state->point_size;
1087 }
1088 /* Divide by two, because 0.5 = 1 pixel. */
1089 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
1090 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
1091 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)),
1092 NULL, 0);
1093
1094 tmp = (unsigned)state->line_width * 8;
1095 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), NULL, 0);
1096 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
1097 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable),
1098 NULL, 0);
1099
1100 r600_pipe_state_add_reg(rstate, R_028BDC_PA_SC_LINE_CNTL, 0x00000400, NULL, 0);
1101 r600_pipe_state_add_reg(rstate, R_028BE4_PA_SU_VTX_CNTL,
1102 S_028BE4_PIX_CENTER(state->gl_rasterization_rules),
1103 NULL, 0);
1104 r600_pipe_state_add_reg(rstate, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, NULL, 0);
1105 r600_pipe_state_add_reg(rstate, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, NULL, 0);
1106 r600_pipe_state_add_reg(rstate, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, NULL, 0);
1107 r600_pipe_state_add_reg(rstate, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, NULL, 0);
1108
1109 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), NULL, 0);
1110 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, NULL, 0);
1111 return rstate;
1112 }
1113
1114 static void *si_create_sampler_state(struct pipe_context *ctx,
1115 const struct pipe_sampler_state *state)
1116 {
1117 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
1118 union util_color uc;
1119 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
1120 unsigned border_color_type;
1121
1122 if (rstate == NULL) {
1123 return NULL;
1124 }
1125
1126 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
1127 switch (uc.ui) {
1128 case 0x000000FF:
1129 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
1130 break;
1131 case 0x00000000:
1132 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
1133 break;
1134 case 0xFFFFFFFF:
1135 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
1136 break;
1137 default: /* Use border color pointer */
1138 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
1139 }
1140
1141 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
1142 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
1143 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
1144 (state->max_anisotropy & 0x7) << 9 | /* XXX */
1145 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
1146 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
1147 aniso_flag_offset << 16 | /* XXX */
1148 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
1149 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
1150 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
1151 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
1152 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
1153 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
1154 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
1155 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
1156
1157 #if 0
1158 if (border_color_type == 3) {
1159 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0);
1160 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0);
1161 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0);
1162 r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0);
1163 }
1164 #endif
1165 return rstate;
1166 }
1167
1168 static void si_delete_sampler_state(struct pipe_context *ctx,
1169 void *state)
1170 {
1171 free(state);
1172 }
1173
1174 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
1175 struct pipe_resource *texture,
1176 const struct pipe_sampler_view *state)
1177 {
1178 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
1179 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
1180 const struct util_format_description *desc = util_format_description(state->format);
1181 unsigned blocksize = util_format_get_blocksize(tmp->real_format);
1182 unsigned format, num_format, endian, tiling_index;
1183 uint32_t pitch = 0;
1184 unsigned char state_swizzle[4], swizzle[4];
1185 unsigned height, depth, width;
1186 int first_non_void;
1187 uint64_t va;
1188
1189 if (view == NULL)
1190 return NULL;
1191
1192 /* initialize base object */
1193 view->base = *state;
1194 view->base.texture = NULL;
1195 pipe_reference(NULL, &texture->reference);
1196 view->base.texture = texture;
1197 view->base.reference.count = 1;
1198 view->base.context = ctx;
1199
1200 state_swizzle[0] = state->swizzle_r;
1201 state_swizzle[1] = state->swizzle_g;
1202 state_swizzle[2] = state->swizzle_b;
1203 state_swizzle[3] = state->swizzle_a;
1204 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
1205
1206 first_non_void = util_format_get_first_non_void_channel(state->format);
1207 switch (desc->channel[first_non_void].type) {
1208 case UTIL_FORMAT_TYPE_FLOAT:
1209 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
1210 break;
1211 case UTIL_FORMAT_TYPE_SIGNED:
1212 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
1213 break;
1214 case UTIL_FORMAT_TYPE_UNSIGNED:
1215 default:
1216 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
1217 }
1218
1219 format = si_translate_texformat(ctx->screen, state->format, desc, first_non_void);
1220 if (format == ~0) {
1221 format = 0;
1222 }
1223
1224 if (tmp->depth && !tmp->is_flushing_texture) {
1225 r600_texture_depth_flush(ctx, texture, TRUE);
1226 tmp = tmp->flushed_depth_texture;
1227 }
1228
1229 endian = si_colorformat_endian_swap(format);
1230
1231 height = texture->height0;
1232 depth = texture->depth0;
1233 width = texture->width0;
1234 pitch = align(tmp->pitch_in_blocks[0] *
1235 util_format_get_blockwidth(state->format), 8);
1236
1237 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1238 height = 1;
1239 depth = texture->array_size;
1240 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1241 depth = texture->array_size;
1242 }
1243
1244 tiling_index = 8;
1245 switch (tmp->surface.level[state->u.tex.first_level].mode) {
1246 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1247 tiling_index = 8;
1248 break;
1249 case RADEON_SURF_MODE_1D:
1250 tiling_index = 9;
1251 break;
1252 case RADEON_SURF_MODE_2D:
1253 if (tmp->resource.b.b.bind & PIPE_BIND_SCANOUT) {
1254 switch (blocksize) {
1255 case 1:
1256 tiling_index = 10;
1257 break;
1258 case 2:
1259 tiling_index = 11;
1260 break;
1261 case 4:
1262 tiling_index = 12;
1263 break;
1264 }
1265 break;
1266 } else switch (blocksize) {
1267 case 1:
1268 tiling_index = 14;
1269 break;
1270 case 2:
1271 tiling_index = 15;
1272 break;
1273 case 4:
1274 tiling_index = 16;
1275 break;
1276 case 8:
1277 tiling_index = 17;
1278 break;
1279 default:
1280 tiling_index = 13;
1281 }
1282 break;
1283 }
1284
1285 va = r600_resource_va(ctx->screen, texture);
1286 if (state->u.tex.last_level) {
1287 view->state[0] = (va + tmp->offset[1]) >> 8;
1288 } else {
1289 view->state[0] = (va + tmp->offset[0]) >> 8;
1290 }
1291 view->state[1] = (S_008F14_BASE_ADDRESS_HI((va + tmp->offset[0]) >> 40) |
1292 S_008F14_DATA_FORMAT(format) |
1293 S_008F14_NUM_FORMAT(num_format));
1294 view->state[2] = (S_008F18_WIDTH(width - 1) |
1295 S_008F18_HEIGHT(height - 1));
1296 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
1297 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
1298 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
1299 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
1300 S_008F1C_BASE_LEVEL(state->u.tex.first_level) |
1301 S_008F1C_LAST_LEVEL(state->u.tex.last_level) |
1302 S_008F1C_TILING_INDEX(tiling_index) |
1303 S_008F1C_TYPE(si_tex_dim(texture->target)));
1304 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
1305 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
1306 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
1307 view->state[6] = 0;
1308 view->state[7] = 0;
1309
1310 return &view->base;
1311 }
1312
1313 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1314 struct pipe_sampler_view **views)
1315 {
1316 }
1317
1318 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1319 struct pipe_sampler_view **views)
1320 {
1321 struct r600_context *rctx = (struct r600_context *)ctx;
1322 struct si_pipe_sampler_view **resource = (struct si_pipe_sampler_view **)views;
1323 struct r600_pipe_state *rstate = &rctx->ps_samplers.views_state;
1324 struct r600_resource *bo;
1325 int i;
1326 int has_depth = 0;
1327 uint64_t va;
1328 char *ptr;
1329
1330 if (!count)
1331 goto out;
1332
1333 r600_inval_texture_cache(rctx);
1334
1335 bo = (struct r600_resource*)
1336 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
1337 count * sizeof(resource[0]->state));
1338 ptr = rctx->ws->buffer_map(bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
1339
1340 for (i = 0; i < count; i++, ptr += sizeof(resource[0]->state)) {
1341 pipe_sampler_view_reference(
1342 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
1343 views[i]);
1344
1345 if (resource[i]) {
1346 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1347 has_depth = 1;
1348
1349 memcpy(ptr, resource[i]->state, sizeof(resource[0]->state));
1350 } else
1351 memset(ptr, 0, sizeof(resource[0]->state));
1352 }
1353
1354 rctx->ws->buffer_unmap(bo->cs_buf);
1355
1356 for (i = count; i < NUM_TEX_UNITS; i++) {
1357 if (rctx->ps_samplers.views[i])
1358 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
1359 }
1360
1361 rstate->nregs = 0;
1362 va = r600_resource_va(ctx->screen, (void *)bo);
1363 r600_pipe_state_add_reg(rstate, R_00B040_SPI_SHADER_USER_DATA_PS_4, va, bo, RADEON_USAGE_READ);
1364 r600_pipe_state_add_reg(rstate, R_00B044_SPI_SHADER_USER_DATA_PS_5, va >> 32, NULL, 0);
1365 r600_context_pipe_state_set(rctx, rstate);
1366
1367 out:
1368 rctx->have_depth_texture = has_depth;
1369 rctx->ps_samplers.n_views = count;
1370 }
1371
1372 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1373 {
1374 struct r600_context *rctx = (struct r600_context *)ctx;
1375 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
1376 struct r600_pipe_state *rstate = &rctx->ps_samplers.samplers_state;
1377 struct r600_resource *bo;
1378 uint64_t va;
1379 char *ptr;
1380 int i;
1381
1382 if (!count)
1383 goto out;
1384
1385 r600_inval_texture_cache(rctx);
1386
1387 bo = (struct r600_resource*)
1388 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
1389 count * sizeof(rstates[0]->val));
1390 ptr = rctx->ws->buffer_map(bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
1391
1392 for (i = 0; i < count; i++, ptr += sizeof(rstates[0]->val)) {
1393 memcpy(ptr, rstates[i]->val, sizeof(rstates[0]->val));
1394 }
1395
1396 rctx->ws->buffer_unmap(bo->cs_buf);
1397
1398 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
1399
1400 rstate->nregs = 0;
1401 va = r600_resource_va(ctx->screen, (void *)bo);
1402 r600_pipe_state_add_reg(rstate, R_00B038_SPI_SHADER_USER_DATA_PS_2, va, bo, RADEON_USAGE_READ);
1403 r600_pipe_state_add_reg(rstate, R_00B03C_SPI_SHADER_USER_DATA_PS_3, va >> 32, NULL, 0);
1404 r600_context_pipe_state_set(rctx, rstate);
1405
1406 out:
1407 rctx->ps_samplers.n_samplers = count;
1408 }
1409
1410 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1411 {
1412 }
1413
1414 static void evergreen_set_clip_state(struct pipe_context *ctx,
1415 const struct pipe_clip_state *state)
1416 {
1417 struct r600_context *rctx = (struct r600_context *)ctx;
1418 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1419
1420 if (rstate == NULL)
1421 return;
1422
1423 rctx->clip = *state;
1424 rstate->id = R600_PIPE_STATE_CLIP;
1425 for (int i = 0; i < 6; i++) {
1426 r600_pipe_state_add_reg(rstate,
1427 R_0285BC_PA_CL_UCP_0_X + i * 16,
1428 fui(state->ucp[i][0]), NULL, 0);
1429 r600_pipe_state_add_reg(rstate,
1430 R_0285C0_PA_CL_UCP_0_Y + i * 16,
1431 fui(state->ucp[i][1]) , NULL, 0);
1432 r600_pipe_state_add_reg(rstate,
1433 R_0285C4_PA_CL_UCP_0_Z + i * 16,
1434 fui(state->ucp[i][2]), NULL, 0);
1435 r600_pipe_state_add_reg(rstate,
1436 R_0285C8_PA_CL_UCP_0_W + i * 16,
1437 fui(state->ucp[i][3]), NULL, 0);
1438 }
1439
1440 free(rctx->states[R600_PIPE_STATE_CLIP]);
1441 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1442 r600_context_pipe_state_set(rctx, rstate);
1443 }
1444
1445 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1446 const struct pipe_poly_stipple *state)
1447 {
1448 }
1449
1450 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1451 {
1452 }
1453
1454 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1455 const struct pipe_scissor_state *state)
1456 {
1457 struct r600_context *rctx = (struct r600_context *)ctx;
1458 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1459 uint32_t tl, br;
1460
1461 if (rstate == NULL)
1462 return;
1463
1464 rstate->id = R600_PIPE_STATE_SCISSOR;
1465 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
1466 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1467 r600_pipe_state_add_reg(rstate,
1468 R_028210_PA_SC_CLIPRECT_0_TL, tl,
1469 NULL, 0);
1470 r600_pipe_state_add_reg(rstate,
1471 R_028214_PA_SC_CLIPRECT_0_BR, br,
1472 NULL, 0);
1473 r600_pipe_state_add_reg(rstate,
1474 R_028218_PA_SC_CLIPRECT_1_TL, tl,
1475 NULL, 0);
1476 r600_pipe_state_add_reg(rstate,
1477 R_02821C_PA_SC_CLIPRECT_1_BR, br,
1478 NULL, 0);
1479 r600_pipe_state_add_reg(rstate,
1480 R_028220_PA_SC_CLIPRECT_2_TL, tl,
1481 NULL, 0);
1482 r600_pipe_state_add_reg(rstate,
1483 R_028224_PA_SC_CLIPRECT_2_BR, br,
1484 NULL, 0);
1485 r600_pipe_state_add_reg(rstate,
1486 R_028228_PA_SC_CLIPRECT_3_TL, tl,
1487 NULL, 0);
1488 r600_pipe_state_add_reg(rstate,
1489 R_02822C_PA_SC_CLIPRECT_3_BR, br,
1490 NULL, 0);
1491
1492 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1493 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1494 r600_context_pipe_state_set(rctx, rstate);
1495 }
1496
1497 static void evergreen_set_viewport_state(struct pipe_context *ctx,
1498 const struct pipe_viewport_state *state)
1499 {
1500 struct r600_context *rctx = (struct r600_context *)ctx;
1501 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1502
1503 if (rstate == NULL)
1504 return;
1505
1506 rctx->viewport = *state;
1507 rstate->id = R600_PIPE_STATE_VIEWPORT;
1508 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, NULL, 0);
1509 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, NULL, 0);
1510 r600_pipe_state_add_reg(rstate, R_028350_PA_SC_RASTER_CONFIG, 0x00000000, NULL, 0);
1511 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), NULL, 0);
1512 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), NULL, 0);
1513 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), NULL, 0);
1514 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), NULL, 0);
1515 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), NULL, 0);
1516 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), NULL, 0);
1517 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, NULL, 0);
1518
1519 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1520 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1521 r600_context_pipe_state_set(rctx, rstate);
1522 }
1523
1524 static void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
1525 const struct pipe_framebuffer_state *state, int cb)
1526 {
1527 struct r600_resource_texture *rtex;
1528 struct r600_surface *surf;
1529 unsigned level = state->cbufs[cb]->u.tex.level;
1530 unsigned pitch, slice;
1531 unsigned color_info, color_attrib;
1532 unsigned format, swap, ntype, endian;
1533 uint64_t offset;
1534 unsigned blocksize;
1535 const struct util_format_description *desc;
1536 int i;
1537 unsigned blend_clamp = 0, blend_bypass = 0;
1538
1539 surf = (struct r600_surface *)state->cbufs[cb];
1540 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1541 blocksize = util_format_get_blocksize(rtex->real_format);
1542
1543 if (rtex->depth)
1544 rctx->have_depth_fb = TRUE;
1545
1546 if (rtex->depth && !rtex->is_flushing_texture) {
1547 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1548 rtex = rtex->flushed_depth_texture;
1549 }
1550
1551 offset = rtex->surface.level[level].offset;
1552 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1553 offset += rtex->surface.level[level].slice_size *
1554 state->cbufs[cb]->u.tex.first_layer;
1555 }
1556 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1557 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1558 if (slice) {
1559 slice = slice - 1;
1560 }
1561
1562 color_attrib = S_028C74_TILE_MODE_INDEX(8);
1563 switch (rtex->surface.level[level].mode) {
1564 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1565 color_attrib = S_028C74_TILE_MODE_INDEX(8);
1566 break;
1567 case RADEON_SURF_MODE_1D:
1568 color_attrib = S_028C74_TILE_MODE_INDEX(9);
1569 break;
1570 case RADEON_SURF_MODE_2D:
1571 if (rtex->resource.b.b.bind & PIPE_BIND_SCANOUT) {
1572 switch (blocksize) {
1573 case 1:
1574 color_attrib = S_028C74_TILE_MODE_INDEX(10);
1575 break;
1576 case 2:
1577 color_attrib = S_028C74_TILE_MODE_INDEX(11);
1578 break;
1579 case 4:
1580 color_attrib = S_028C74_TILE_MODE_INDEX(12);
1581 break;
1582 }
1583 break;
1584 } else switch (blocksize) {
1585 case 1:
1586 color_attrib = S_028C74_TILE_MODE_INDEX(14);
1587 break;
1588 case 2:
1589 color_attrib = S_028C74_TILE_MODE_INDEX(15);
1590 break;
1591 case 4:
1592 color_attrib = S_028C74_TILE_MODE_INDEX(16);
1593 break;
1594 case 8:
1595 color_attrib = S_028C74_TILE_MODE_INDEX(17);
1596 break;
1597 default:
1598 color_attrib = S_028C74_TILE_MODE_INDEX(13);
1599 }
1600 break;
1601 }
1602
1603 desc = util_format_description(surf->base.format);
1604 for (i = 0; i < 4; i++) {
1605 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1606 break;
1607 }
1608 }
1609 if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1610 ntype = V_028C70_NUMBER_FLOAT;
1611 } else {
1612 ntype = V_028C70_NUMBER_UNORM;
1613 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1614 ntype = V_028C70_NUMBER_SRGB;
1615 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1616 if (desc->channel[i].normalized)
1617 ntype = V_028C70_NUMBER_SNORM;
1618 else if (desc->channel[i].pure_integer)
1619 ntype = V_028C70_NUMBER_SINT;
1620 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1621 if (desc->channel[i].normalized)
1622 ntype = V_028C70_NUMBER_UNORM;
1623 else if (desc->channel[i].pure_integer)
1624 ntype = V_028C70_NUMBER_UINT;
1625 }
1626 }
1627
1628 format = si_translate_colorformat(surf->base.format);
1629 swap = si_translate_colorswap(surf->base.format);
1630 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1631 endian = V_028C70_ENDIAN_NONE;
1632 } else {
1633 endian = si_colorformat_endian_swap(format);
1634 }
1635
1636 /* blend clamp should be set for all NORM/SRGB types */
1637 if (ntype == V_028C70_NUMBER_UNORM ||
1638 ntype == V_028C70_NUMBER_SNORM ||
1639 ntype == V_028C70_NUMBER_SRGB)
1640 blend_clamp = 1;
1641
1642 /* set blend bypass according to docs if SINT/UINT or
1643 8/24 COLOR variants */
1644 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1645 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1646 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1647 blend_clamp = 0;
1648 blend_bypass = 1;
1649 }
1650
1651 color_info = S_028C70_FORMAT(format) |
1652 S_028C70_COMP_SWAP(swap) |
1653 S_028C70_BLEND_CLAMP(blend_clamp) |
1654 S_028C70_BLEND_BYPASS(blend_bypass) |
1655 S_028C70_NUMBER_TYPE(ntype) |
1656 S_028C70_ENDIAN(endian);
1657
1658 rctx->alpha_ref_dirty = true;
1659
1660 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1661 offset >>= 8;
1662
1663 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1664 r600_pipe_state_add_reg(rstate,
1665 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
1666 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1667 r600_pipe_state_add_reg(rstate,
1668 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
1669 S_028C64_TILE_MAX(pitch),
1670 NULL, 0);
1671 r600_pipe_state_add_reg(rstate,
1672 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
1673 S_028C68_TILE_MAX(slice),
1674 NULL, 0);
1675 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1676 r600_pipe_state_add_reg(rstate,
1677 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1678 0x00000000, NULL, 0);
1679 } else {
1680 r600_pipe_state_add_reg(rstate,
1681 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1682 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1683 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer),
1684 NULL, 0);
1685 }
1686 r600_pipe_state_add_reg(rstate,
1687 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
1688 color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1689 r600_pipe_state_add_reg(rstate,
1690 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
1691 color_attrib,
1692 &rtex->resource, RADEON_USAGE_READWRITE);
1693 }
1694
1695 static void si_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
1696 const struct pipe_framebuffer_state *state)
1697 {
1698 struct r600_resource_texture *rtex;
1699 struct r600_surface *surf;
1700 unsigned level, first_layer, pitch, slice, format;
1701 uint32_t db_z_info, stencil_info;
1702 uint64_t offset;
1703
1704 if (state->zsbuf == NULL) {
1705 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO, 0, NULL, 0);
1706 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO, 0, NULL, 0);
1707 return;
1708 }
1709
1710 surf = (struct r600_surface *)state->zsbuf;
1711 level = surf->base.u.tex.level;
1712 rtex = (struct r600_resource_texture*)surf->base.texture;
1713
1714 first_layer = surf->base.u.tex.first_layer;
1715 format = si_translate_dbformat(rtex->real_format);
1716
1717 offset = r600_resource_va(rctx->context.screen, surf->base.texture);
1718 offset += rtex->surface.level[level].offset;
1719 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1720 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1721 if (slice) {
1722 slice = slice - 1;
1723 }
1724 offset >>= 8;
1725
1726 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
1727 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1728 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
1729 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1730 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1731 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1732 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer),
1733 NULL, 0);
1734
1735 db_z_info = S_028040_FORMAT(format);
1736 stencil_info = S_028044_FORMAT(rtex->stencil != 0);
1737
1738 switch (format) {
1739 case V_028040_Z_16:
1740 db_z_info |= S_028040_TILE_MODE_INDEX(5);
1741 stencil_info |= S_028044_TILE_MODE_INDEX(5);
1742 break;
1743 case V_028040_Z_24:
1744 case V_028040_Z_32_FLOAT:
1745 db_z_info |= S_028040_TILE_MODE_INDEX(6);
1746 stencil_info |= S_028044_TILE_MODE_INDEX(6);
1747 break;
1748 default:
1749 db_z_info |= S_028040_TILE_MODE_INDEX(7);
1750 stencil_info |= S_028044_TILE_MODE_INDEX(7);
1751 }
1752
1753 if (rtex->stencil) {
1754 uint64_t stencil_offset =
1755 r600_texture_get_offset(rtex->stencil, level, first_layer);
1756
1757 stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil);
1758 stencil_offset >>= 8;
1759
1760 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1761 stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1762 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1763 stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1764 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1765 stencil_info, NULL, 0);
1766 } else {
1767 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1768 0, NULL, 0);
1769 }
1770
1771 if (format != ~0U) {
1772 r600_pipe_state_add_reg(rstate, R_02803C_DB_DEPTH_INFO, 0x1, NULL, 0);
1773 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO, db_z_info, NULL, 0);
1774 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
1775 S_028058_PITCH_TILE_MAX(pitch),
1776 NULL, 0);
1777 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
1778 S_02805C_SLICE_TILE_MAX(slice),
1779 NULL, 0);
1780
1781 } else {
1782 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO, 0, NULL, 0);
1783 }
1784 }
1785
1786 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1787 const struct pipe_framebuffer_state *state)
1788 {
1789 struct r600_context *rctx = (struct r600_context *)ctx;
1790 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1791 uint32_t shader_mask, tl, br;
1792 int tl_x, tl_y, br_x, br_y;
1793
1794 if (rstate == NULL)
1795 return;
1796
1797 r600_flush_framebuffer(rctx, false);
1798
1799 /* unreference old buffer and reference new one */
1800 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1801
1802 util_copy_framebuffer_state(&rctx->framebuffer, state);
1803
1804 /* build states */
1805 rctx->have_depth_fb = 0;
1806 rctx->nr_cbufs = state->nr_cbufs;
1807 for (int i = 0; i < state->nr_cbufs; i++) {
1808 evergreen_cb(rctx, rstate, state, i);
1809 }
1810 si_db(rctx, rstate, state);
1811
1812 shader_mask = 0;
1813 for (int i = 0; i < state->nr_cbufs; i++) {
1814 shader_mask |= 0xf << (i * 4);
1815 }
1816 tl_x = 0;
1817 tl_y = 0;
1818 br_x = state->width;
1819 br_y = state->height;
1820 #if 0 /* These shouldn't be necessary on SI, see PA_SC_ENHANCE register */
1821 /* EG hw workaround */
1822 if (br_x == 0)
1823 tl_x = 1;
1824 if (br_y == 0)
1825 tl_y = 1;
1826 /* cayman hw workaround */
1827 if (rctx->chip_class == CAYMAN) {
1828 if (br_x == 1 && br_y == 1)
1829 br_x = 2;
1830 }
1831 #endif
1832 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1833 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1834
1835 r600_pipe_state_add_reg(rstate,
1836 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1837 NULL, 0);
1838 r600_pipe_state_add_reg(rstate,
1839 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1840 NULL, 0);
1841 r600_pipe_state_add_reg(rstate,
1842 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1843 NULL, 0);
1844 r600_pipe_state_add_reg(rstate,
1845 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1846 NULL, 0);
1847 r600_pipe_state_add_reg(rstate,
1848 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1849 NULL, 0);
1850 r600_pipe_state_add_reg(rstate,
1851 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1852 NULL, 0);
1853 r600_pipe_state_add_reg(rstate,
1854 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1855 NULL, 0);
1856 r600_pipe_state_add_reg(rstate,
1857 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1858 NULL, 0);
1859 r600_pipe_state_add_reg(rstate,
1860 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1861 NULL, 0);
1862 r600_pipe_state_add_reg(rstate,
1863 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1864 NULL, 0);
1865
1866 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1867 shader_mask, NULL, 0);
1868
1869 r600_pipe_state_add_reg(rstate, R_028BE0_PA_SC_AA_CONFIG,
1870 0x00000000, NULL, 0);
1871
1872 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1873 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1874 r600_context_pipe_state_set(rctx, rstate);
1875
1876 if (state->zsbuf) {
1877 cayman_polygon_offset_update(rctx);
1878 }
1879 }
1880
1881 void cayman_init_state_functions(struct r600_context *rctx)
1882 {
1883 rctx->context.create_blend_state = evergreen_create_blend_state;
1884 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1885 rctx->context.create_fs_state = si_create_shader_state;
1886 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1887 rctx->context.create_sampler_state = si_create_sampler_state;
1888 rctx->context.create_sampler_view = evergreen_create_sampler_view;
1889 rctx->context.create_vertex_elements_state = si_create_vertex_elements;
1890 rctx->context.create_vs_state = si_create_shader_state;
1891 rctx->context.bind_blend_state = r600_bind_blend_state;
1892 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1893 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1894 rctx->context.bind_fs_state = r600_bind_ps_shader;
1895 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1896 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1897 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1898 rctx->context.bind_vs_state = r600_bind_vs_shader;
1899 rctx->context.delete_blend_state = r600_delete_state;
1900 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1901 rctx->context.delete_fs_state = r600_delete_ps_shader;
1902 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1903 rctx->context.delete_sampler_state = si_delete_sampler_state;
1904 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1905 rctx->context.delete_vs_state = r600_delete_vs_shader;
1906 rctx->context.set_blend_color = evergreen_set_blend_color;
1907 rctx->context.set_clip_state = evergreen_set_clip_state;
1908 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1909 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1910 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1911 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1912 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1913 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1914 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1915 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1916 rctx->context.set_index_buffer = r600_set_index_buffer;
1917 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1918 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1919 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1920 rctx->context.texture_barrier = r600_texture_barrier;
1921 rctx->context.create_stream_output_target = r600_create_so_target;
1922 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1923 rctx->context.set_stream_output_targets = r600_set_so_targets;
1924 }
1925
1926 void si_init_config(struct r600_context *rctx)
1927 {
1928 struct r600_pipe_state *rstate = &rctx->config;
1929 unsigned tmp;
1930
1931 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, NULL, 0);
1932
1933 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, NULL, 0);
1934 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, NULL, 0);
1935 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, NULL, 0);
1936 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, NULL, 0);
1937 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, NULL, 0);
1938 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, NULL, 0);
1939 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, NULL, 0);
1940 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, NULL, 0);
1941 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, NULL, 0);
1942 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, NULL, 0);
1943 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, NULL, 0);
1944 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, NULL, 0);
1945 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, NULL, 0);
1946 r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x0, NULL, 0);
1947 r600_pipe_state_add_reg(rstate, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0, NULL, 0);
1948 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, NULL, 0);
1949 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, NULL, 0);
1950 r600_pipe_state_add_reg(rstate, R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63), NULL, 0);
1951 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, NULL, 0);
1952 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, NULL, 0);
1953 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, NULL, 0);
1954
1955 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, NULL, 0);
1956
1957 r600_pipe_state_add_reg(rstate, R_028B54_VGT_SHADER_STAGES_EN, 0, NULL, 0);
1958 r600_pipe_state_add_reg(rstate, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210, NULL, 0);
1959 r600_pipe_state_add_reg(rstate, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98, NULL, 0);
1960
1961 r600_pipe_state_add_reg(rstate, R_028804_DB_EQAA, 0x110000, NULL, 0);
1962 r600_context_pipe_state_set(rctx, rstate);
1963 }
1964
1965 void cayman_polygon_offset_update(struct r600_context *rctx)
1966 {
1967 struct r600_pipe_state state;
1968
1969 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
1970 state.nregs = 0;
1971 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
1972 float offset_units = rctx->rasterizer->offset_units;
1973 unsigned offset_db_fmt_cntl = 0, depth;
1974
1975 switch (rctx->framebuffer.zsbuf->texture->format) {
1976 case PIPE_FORMAT_Z24X8_UNORM:
1977 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1978 depth = -24;
1979 offset_units *= 2.0f;
1980 break;
1981 case PIPE_FORMAT_Z32_FLOAT:
1982 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1983 depth = -23;
1984 offset_units *= 1.0f;
1985 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1986 break;
1987 case PIPE_FORMAT_Z16_UNORM:
1988 depth = -16;
1989 offset_units *= 4.0f;
1990 break;
1991 default:
1992 return;
1993 }
1994 /* FIXME some of those reg can be computed with cso */
1995 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
1996 r600_pipe_state_add_reg(&state,
1997 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1998 fui(rctx->rasterizer->offset_scale), NULL, 0);
1999 r600_pipe_state_add_reg(&state,
2000 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2001 fui(offset_units), NULL, 0);
2002 r600_pipe_state_add_reg(&state,
2003 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2004 fui(rctx->rasterizer->offset_scale), NULL, 0);
2005 r600_pipe_state_add_reg(&state,
2006 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2007 fui(offset_units), NULL, 0);
2008 r600_pipe_state_add_reg(&state,
2009 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2010 offset_db_fmt_cntl, NULL, 0);
2011 r600_context_pipe_state_set(rctx, &state);
2012 }
2013 }
2014
2015 void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader)
2016 {
2017 struct r600_context *rctx = (struct r600_context *)ctx;
2018 struct r600_pipe_state *rstate = &shader->rstate;
2019 struct r600_shader *rshader = &shader->shader;
2020 unsigned i, exports_ps, num_cout, spi_ps_in_control, db_shader_control;
2021 unsigned num_sgprs, num_user_sgprs;
2022 int pos_index = -1, face_index = -1;
2023 int ninterp = 0;
2024 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2025 unsigned spi_baryc_cntl;
2026 uint64_t va;
2027
2028 if (si_pipe_shader_create(ctx, shader))
2029 return;
2030
2031 rstate->nregs = 0;
2032
2033 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2034 for (i = 0; i < rshader->ninput; i++) {
2035 ninterp++;
2036 /* XXX: Flat shading hangs the GPU */
2037 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2038 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2039 rctx->rasterizer->flatshade))
2040 have_linear = TRUE;
2041 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2042 have_linear = TRUE;
2043 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2044 have_perspective = TRUE;
2045 if (rshader->input[i].centroid)
2046 have_centroid = TRUE;
2047 }
2048
2049 for (i = 0; i < rshader->noutput; i++) {
2050 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2051 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2052 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2053 db_shader_control |= 0; // XXX OP_VAL or TEST_VAL?
2054 }
2055 if (rshader->uses_kill)
2056 db_shader_control |= S_02880C_KILL_ENABLE(1);
2057
2058 exports_ps = 0;
2059 num_cout = 0;
2060 for (i = 0; i < rshader->noutput; i++) {
2061 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2062 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2063 exports_ps |= 1;
2064 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
2065 if (rshader->fs_write_all)
2066 num_cout = rshader->nr_cbufs;
2067 else
2068 num_cout++;
2069 }
2070 }
2071 if (!exports_ps) {
2072 /* always at least export 1 component per pixel */
2073 exports_ps = 2;
2074 }
2075
2076 spi_ps_in_control = S_0286D8_NUM_INTERP(ninterp);
2077
2078 spi_baryc_cntl = 0;
2079 if (have_perspective)
2080 spi_baryc_cntl |= have_centroid ?
2081 S_0286E0_PERSP_CENTROID_CNTL(1) : S_0286E0_PERSP_CENTER_CNTL(1);
2082 if (have_linear)
2083 spi_baryc_cntl |= have_centroid ?
2084 S_0286E0_LINEAR_CENTROID_CNTL(1) : S_0286E0_LINEAR_CENTER_CNTL(1);
2085
2086 r600_pipe_state_add_reg(rstate,
2087 R_0286E0_SPI_BARYC_CNTL,
2088 spi_baryc_cntl,
2089 NULL, 0);
2090
2091 r600_pipe_state_add_reg(rstate,
2092 R_0286CC_SPI_PS_INPUT_ENA,
2093 shader->spi_ps_input_ena,
2094 NULL, 0);
2095
2096 r600_pipe_state_add_reg(rstate,
2097 R_0286D0_SPI_PS_INPUT_ADDR,
2098 shader->spi_ps_input_ena,
2099 NULL, 0);
2100
2101 r600_pipe_state_add_reg(rstate,
2102 R_0286D8_SPI_PS_IN_CONTROL,
2103 spi_ps_in_control,
2104 NULL, 0);
2105
2106 /* XXX: Depends on Z buffer format? */
2107 r600_pipe_state_add_reg(rstate,
2108 R_028710_SPI_SHADER_Z_FORMAT,
2109 0,
2110 NULL, 0);
2111
2112 /* XXX: Depends on color buffer format? */
2113 r600_pipe_state_add_reg(rstate,
2114 R_028714_SPI_SHADER_COL_FORMAT,
2115 S_028714_COL0_EXPORT_FORMAT(V_028714_SPI_SHADER_32_ABGR),
2116 NULL, 0);
2117
2118 va = r600_resource_va(ctx->screen, (void *)shader->bo);
2119 r600_pipe_state_add_reg(rstate,
2120 R_00B020_SPI_SHADER_PGM_LO_PS,
2121 va >> 8,
2122 shader->bo, RADEON_USAGE_READ);
2123 r600_pipe_state_add_reg(rstate,
2124 R_00B024_SPI_SHADER_PGM_HI_PS,
2125 va >> 40,
2126 shader->bo, RADEON_USAGE_READ);
2127
2128 num_user_sgprs = 6;
2129 num_sgprs = shader->num_sgprs;
2130 if (num_user_sgprs > num_sgprs)
2131 num_sgprs = num_user_sgprs;
2132 /* Last 2 reserved SGPRs are used for VCC */
2133 num_sgprs += 2;
2134 assert(num_sgprs <= 104);
2135
2136 r600_pipe_state_add_reg(rstate,
2137 R_00B028_SPI_SHADER_PGM_RSRC1_PS,
2138 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
2139 S_00B028_SGPRS((num_sgprs - 1) / 8),
2140 NULL, 0);
2141 r600_pipe_state_add_reg(rstate,
2142 R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
2143 S_00B02C_USER_SGPR(num_user_sgprs),
2144 NULL, 0);
2145
2146 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
2147 db_shader_control,
2148 NULL, 0);
2149
2150 shader->sprite_coord_enable = rctx->sprite_coord_enable;
2151 }
2152
2153 void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader)
2154 {
2155 struct r600_context *rctx = (struct r600_context *)ctx;
2156 struct r600_pipe_state *rstate = &shader->rstate;
2157 struct r600_shader *rshader = &shader->shader;
2158 unsigned num_sgprs, num_user_sgprs;
2159 unsigned nparams, i;
2160 uint64_t va;
2161
2162 if (si_pipe_shader_create(ctx, shader))
2163 return;
2164
2165 /* clear previous register */
2166 rstate->nregs = 0;
2167
2168 /* Certain attributes (position, psize, etc.) don't count as params.
2169 * VS is required to export at least one param and r600_shader_from_tgsi()
2170 * takes care of adding a dummy export.
2171 */
2172 for (nparams = 0, i = 0 ; i < rshader->noutput; i++) {
2173 if (rshader->output[i].name != TGSI_SEMANTIC_POSITION)
2174 nparams++;
2175 }
2176 if (nparams < 1)
2177 nparams = 1;
2178
2179 r600_pipe_state_add_reg(rstate,
2180 R_0286C4_SPI_VS_OUT_CONFIG,
2181 S_0286C4_VS_EXPORT_COUNT(nparams - 1),
2182 NULL, 0);
2183
2184 r600_pipe_state_add_reg(rstate,
2185 R_02870C_SPI_SHADER_POS_FORMAT,
2186 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
2187 S_02870C_POS1_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE) |
2188 S_02870C_POS2_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE) |
2189 S_02870C_POS3_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE),
2190 NULL, 0);
2191
2192 va = r600_resource_va(ctx->screen, (void *)shader->bo);
2193 r600_pipe_state_add_reg(rstate,
2194 R_00B120_SPI_SHADER_PGM_LO_VS,
2195 va >> 8,
2196 shader->bo, RADEON_USAGE_READ);
2197 r600_pipe_state_add_reg(rstate,
2198 R_00B124_SPI_SHADER_PGM_HI_VS,
2199 va >> 40,
2200 shader->bo, RADEON_USAGE_READ);
2201
2202 num_user_sgprs = 8;
2203 num_sgprs = shader->num_sgprs;
2204 if (num_user_sgprs > num_sgprs)
2205 num_sgprs = num_user_sgprs;
2206 /* Last 2 reserved SGPRs are used for VCC */
2207 num_sgprs += 2;
2208 assert(num_sgprs <= 104);
2209
2210 r600_pipe_state_add_reg(rstate,
2211 R_00B128_SPI_SHADER_PGM_RSRC1_VS,
2212 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
2213 S_00B128_SGPRS((num_sgprs - 1) / 8),
2214 NULL, 0);
2215 r600_pipe_state_add_reg(rstate,
2216 R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
2217 S_00B12C_USER_SGPR(num_user_sgprs),
2218 NULL, 0);
2219 }
2220
2221 void si_update_spi_map(struct r600_context *rctx)
2222 {
2223 struct r600_shader *ps = &rctx->ps_shader->shader;
2224 struct r600_shader *vs = &rctx->vs_shader->shader;
2225 struct r600_pipe_state *rstate = &rctx->spi;
2226 unsigned i, j, tmp;
2227
2228 rstate->nregs = 0;
2229
2230 for (i = 0; i < ps->ninput; i++) {
2231 tmp = 0;
2232
2233 #if 0
2234 /* XXX: Flat shading hangs the GPU */
2235 if (ps->input[i].name == TGSI_SEMANTIC_POSITION ||
2236 ps->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2237 (ps->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2238 rctx->rasterizer && rctx->rasterizer->flatshade)) {
2239 tmp |= S_028644_FLAT_SHADE(1);
2240 }
2241 #endif
2242
2243 if (ps->input[i].name == TGSI_SEMANTIC_GENERIC &&
2244 rctx->sprite_coord_enable & (1 << ps->input[i].sid)) {
2245 tmp |= S_028644_PT_SPRITE_TEX(1);
2246 }
2247
2248 for (j = 0; j < vs->noutput; j++) {
2249 if (ps->input[i].name == vs->output[j].name &&
2250 ps->input[i].sid == vs->output[j].sid) {
2251 tmp |= S_028644_OFFSET(vs->output[j].param_offset);
2252 break;
2253 }
2254 }
2255
2256 if (j == vs->noutput) {
2257 /* No corresponding output found, load defaults into input */
2258 tmp |= S_028644_OFFSET(0x20);
2259 }
2260
2261 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2262 tmp, NULL, 0);
2263 }
2264
2265 if (rstate->nregs > 0)
2266 r600_context_pipe_state_set(rctx, rstate);
2267 }
2268
2269 void *cayman_create_db_flush_dsa(struct r600_context *rctx)
2270 {
2271 struct pipe_depth_stencil_alpha_state dsa;
2272 struct r600_pipe_state *rstate;
2273
2274 memset(&dsa, 0, sizeof(dsa));
2275
2276 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2277 r600_pipe_state_add_reg(rstate,
2278 R_028000_DB_RENDER_CONTROL,
2279 S_028000_DEPTH_COPY(1) |
2280 S_028000_STENCIL_COPY(1) |
2281 S_028000_COPY_CENTROID(1),
2282 NULL, 0);
2283 return rstate;
2284 }