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radeonsi: move blender to new state handling
[mesa.git] / src / gallium / drivers / radeonsi / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include "pipe/p_defines.h"
30 #include "pipe/p_state.h"
31 #include "pipe/p_context.h"
32 #include "tgsi/tgsi_scan.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_util.h"
35 #include "util/u_blitter.h"
36 #include "util/u_double_list.h"
37 #include "util/u_transfer.h"
38 #include "util/u_surface.h"
39 #include "util/u_pack_color.h"
40 #include "util/u_memory.h"
41 #include "util/u_inlines.h"
42 #include "util/u_framebuffer.h"
43 #include "pipebuffer/pb_buffer.h"
44 #include "r600.h"
45 #include "sid.h"
46 #include "r600_resource.h"
47 #include "radeonsi_pipe.h"
48 #include "si_state.h"
49
50 #if 0
51 static uint32_t r600_translate_stencil_op(int s_op)
52 {
53 switch (s_op) {
54 case PIPE_STENCIL_OP_KEEP:
55 return V_028800_STENCIL_KEEP;
56 case PIPE_STENCIL_OP_ZERO:
57 return V_028800_STENCIL_ZERO;
58 case PIPE_STENCIL_OP_REPLACE:
59 return V_028800_STENCIL_REPLACE;
60 case PIPE_STENCIL_OP_INCR:
61 return V_028800_STENCIL_INCR;
62 case PIPE_STENCIL_OP_DECR:
63 return V_028800_STENCIL_DECR;
64 case PIPE_STENCIL_OP_INCR_WRAP:
65 return V_028800_STENCIL_INCR_WRAP;
66 case PIPE_STENCIL_OP_DECR_WRAP:
67 return V_028800_STENCIL_DECR_WRAP;
68 case PIPE_STENCIL_OP_INVERT:
69 return V_028800_STENCIL_INVERT;
70 default:
71 R600_ERR("Unknown stencil op %d", s_op);
72 assert(0);
73 break;
74 }
75 return 0;
76 }
77 #endif
78
79 static uint32_t si_translate_fill(uint32_t func)
80 {
81 switch(func) {
82 case PIPE_POLYGON_MODE_FILL:
83 return V_028814_X_DRAW_TRIANGLES;
84 case PIPE_POLYGON_MODE_LINE:
85 return V_028814_X_DRAW_LINES;
86 case PIPE_POLYGON_MODE_POINT:
87 return V_028814_X_DRAW_POINTS;
88 default:
89 assert(0);
90 return V_028814_X_DRAW_POINTS;
91 }
92 }
93
94 /* translates straight */
95 static uint32_t si_translate_ds_func(int func)
96 {
97 return func;
98 }
99
100 static unsigned si_tex_wrap(unsigned wrap)
101 {
102 switch (wrap) {
103 default:
104 case PIPE_TEX_WRAP_REPEAT:
105 return V_008F30_SQ_TEX_WRAP;
106 case PIPE_TEX_WRAP_CLAMP:
107 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
108 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
109 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
110 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
111 return V_008F30_SQ_TEX_CLAMP_BORDER;
112 case PIPE_TEX_WRAP_MIRROR_REPEAT:
113 return V_008F30_SQ_TEX_MIRROR;
114 case PIPE_TEX_WRAP_MIRROR_CLAMP:
115 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
116 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
117 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
118 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
119 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
120 }
121 }
122
123 static unsigned si_tex_filter(unsigned filter)
124 {
125 switch (filter) {
126 default:
127 case PIPE_TEX_FILTER_NEAREST:
128 return V_008F38_SQ_TEX_XY_FILTER_POINT;
129 case PIPE_TEX_FILTER_LINEAR:
130 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
131 }
132 }
133
134 static unsigned si_tex_mipfilter(unsigned filter)
135 {
136 switch (filter) {
137 case PIPE_TEX_MIPFILTER_NEAREST:
138 return V_008F38_SQ_TEX_Z_FILTER_POINT;
139 case PIPE_TEX_MIPFILTER_LINEAR:
140 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
141 default:
142 case PIPE_TEX_MIPFILTER_NONE:
143 return V_008F38_SQ_TEX_Z_FILTER_NONE;
144 }
145 }
146
147 static unsigned si_tex_compare(unsigned compare)
148 {
149 switch (compare) {
150 default:
151 case PIPE_FUNC_NEVER:
152 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
153 case PIPE_FUNC_LESS:
154 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
155 case PIPE_FUNC_EQUAL:
156 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
157 case PIPE_FUNC_LEQUAL:
158 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
159 case PIPE_FUNC_GREATER:
160 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
161 case PIPE_FUNC_NOTEQUAL:
162 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
163 case PIPE_FUNC_GEQUAL:
164 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
165 case PIPE_FUNC_ALWAYS:
166 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
167 }
168 }
169
170 static unsigned si_tex_dim(unsigned dim)
171 {
172 switch (dim) {
173 default:
174 case PIPE_TEXTURE_1D:
175 return V_008F1C_SQ_RSRC_IMG_1D;
176 case PIPE_TEXTURE_1D_ARRAY:
177 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
178 case PIPE_TEXTURE_2D:
179 case PIPE_TEXTURE_RECT:
180 return V_008F1C_SQ_RSRC_IMG_2D;
181 case PIPE_TEXTURE_2D_ARRAY:
182 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
183 case PIPE_TEXTURE_3D:
184 return V_008F1C_SQ_RSRC_IMG_3D;
185 case PIPE_TEXTURE_CUBE:
186 return V_008F1C_SQ_RSRC_IMG_CUBE;
187 }
188 }
189
190 static uint32_t si_translate_dbformat(enum pipe_format format)
191 {
192 switch (format) {
193 case PIPE_FORMAT_Z16_UNORM:
194 return V_028040_Z_16;
195 case PIPE_FORMAT_Z24X8_UNORM:
196 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
197 return V_028040_Z_24; /* XXX no longer supported on SI */
198 case PIPE_FORMAT_Z32_FLOAT:
199 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
200 return V_028040_Z_32_FLOAT;
201 default:
202 return ~0U;
203 }
204 }
205
206 static uint32_t si_translate_colorswap(enum pipe_format format)
207 {
208 switch (format) {
209 /* 8-bit buffers. */
210 case PIPE_FORMAT_L4A4_UNORM:
211 case PIPE_FORMAT_A4R4_UNORM:
212 return V_028C70_SWAP_ALT;
213
214 case PIPE_FORMAT_A8_UNORM:
215 case PIPE_FORMAT_A8_UINT:
216 case PIPE_FORMAT_A8_SINT:
217 case PIPE_FORMAT_R4A4_UNORM:
218 return V_028C70_SWAP_ALT_REV;
219 case PIPE_FORMAT_I8_UNORM:
220 case PIPE_FORMAT_L8_UNORM:
221 case PIPE_FORMAT_I8_UINT:
222 case PIPE_FORMAT_I8_SINT:
223 case PIPE_FORMAT_L8_UINT:
224 case PIPE_FORMAT_L8_SINT:
225 case PIPE_FORMAT_L8_SRGB:
226 case PIPE_FORMAT_R8_UNORM:
227 case PIPE_FORMAT_R8_SNORM:
228 case PIPE_FORMAT_R8_UINT:
229 case PIPE_FORMAT_R8_SINT:
230 return V_028C70_SWAP_STD;
231
232 /* 16-bit buffers. */
233 case PIPE_FORMAT_B5G6R5_UNORM:
234 return V_028C70_SWAP_STD_REV;
235
236 case PIPE_FORMAT_B5G5R5A1_UNORM:
237 case PIPE_FORMAT_B5G5R5X1_UNORM:
238 return V_028C70_SWAP_ALT;
239
240 case PIPE_FORMAT_B4G4R4A4_UNORM:
241 case PIPE_FORMAT_B4G4R4X4_UNORM:
242 return V_028C70_SWAP_ALT;
243
244 case PIPE_FORMAT_Z16_UNORM:
245 return V_028C70_SWAP_STD;
246
247 case PIPE_FORMAT_L8A8_UNORM:
248 case PIPE_FORMAT_L8A8_UINT:
249 case PIPE_FORMAT_L8A8_SINT:
250 case PIPE_FORMAT_L8A8_SRGB:
251 return V_028C70_SWAP_ALT;
252 case PIPE_FORMAT_R8G8_UNORM:
253 case PIPE_FORMAT_R8G8_UINT:
254 case PIPE_FORMAT_R8G8_SINT:
255 return V_028C70_SWAP_STD;
256
257 case PIPE_FORMAT_R16_UNORM:
258 case PIPE_FORMAT_R16_UINT:
259 case PIPE_FORMAT_R16_SINT:
260 case PIPE_FORMAT_R16_FLOAT:
261 return V_028C70_SWAP_STD;
262
263 /* 32-bit buffers. */
264 case PIPE_FORMAT_A8B8G8R8_SRGB:
265 return V_028C70_SWAP_STD_REV;
266 case PIPE_FORMAT_B8G8R8A8_SRGB:
267 return V_028C70_SWAP_ALT;
268
269 case PIPE_FORMAT_B8G8R8A8_UNORM:
270 case PIPE_FORMAT_B8G8R8X8_UNORM:
271 return V_028C70_SWAP_ALT;
272
273 case PIPE_FORMAT_A8R8G8B8_UNORM:
274 case PIPE_FORMAT_X8R8G8B8_UNORM:
275 return V_028C70_SWAP_ALT_REV;
276 case PIPE_FORMAT_R8G8B8A8_SNORM:
277 case PIPE_FORMAT_R8G8B8A8_UNORM:
278 case PIPE_FORMAT_R8G8B8A8_SSCALED:
279 case PIPE_FORMAT_R8G8B8A8_USCALED:
280 case PIPE_FORMAT_R8G8B8A8_SINT:
281 case PIPE_FORMAT_R8G8B8A8_UINT:
282 case PIPE_FORMAT_R8G8B8X8_UNORM:
283 return V_028C70_SWAP_STD;
284
285 case PIPE_FORMAT_A8B8G8R8_UNORM:
286 case PIPE_FORMAT_X8B8G8R8_UNORM:
287 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
288 return V_028C70_SWAP_STD_REV;
289
290 case PIPE_FORMAT_Z24X8_UNORM:
291 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
292 return V_028C70_SWAP_STD;
293
294 case PIPE_FORMAT_X8Z24_UNORM:
295 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
296 return V_028C70_SWAP_STD;
297
298 case PIPE_FORMAT_R10G10B10A2_UNORM:
299 case PIPE_FORMAT_R10G10B10X2_SNORM:
300 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
301 return V_028C70_SWAP_STD;
302
303 case PIPE_FORMAT_B10G10R10A2_UNORM:
304 case PIPE_FORMAT_B10G10R10A2_UINT:
305 return V_028C70_SWAP_ALT;
306
307 case PIPE_FORMAT_R11G11B10_FLOAT:
308 case PIPE_FORMAT_R32_FLOAT:
309 case PIPE_FORMAT_R32_UINT:
310 case PIPE_FORMAT_R32_SINT:
311 case PIPE_FORMAT_Z32_FLOAT:
312 case PIPE_FORMAT_R16G16_FLOAT:
313 case PIPE_FORMAT_R16G16_UNORM:
314 case PIPE_FORMAT_R16G16_UINT:
315 case PIPE_FORMAT_R16G16_SINT:
316 return V_028C70_SWAP_STD;
317
318 /* 64-bit buffers. */
319 case PIPE_FORMAT_R32G32_FLOAT:
320 case PIPE_FORMAT_R32G32_UINT:
321 case PIPE_FORMAT_R32G32_SINT:
322 case PIPE_FORMAT_R16G16B16A16_UNORM:
323 case PIPE_FORMAT_R16G16B16A16_SNORM:
324 case PIPE_FORMAT_R16G16B16A16_USCALED:
325 case PIPE_FORMAT_R16G16B16A16_SSCALED:
326 case PIPE_FORMAT_R16G16B16A16_UINT:
327 case PIPE_FORMAT_R16G16B16A16_SINT:
328 case PIPE_FORMAT_R16G16B16A16_FLOAT:
329 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
330
331 /* 128-bit buffers. */
332 case PIPE_FORMAT_R32G32B32A32_FLOAT:
333 case PIPE_FORMAT_R32G32B32A32_SNORM:
334 case PIPE_FORMAT_R32G32B32A32_UNORM:
335 case PIPE_FORMAT_R32G32B32A32_SSCALED:
336 case PIPE_FORMAT_R32G32B32A32_USCALED:
337 case PIPE_FORMAT_R32G32B32A32_SINT:
338 case PIPE_FORMAT_R32G32B32A32_UINT:
339 return V_028C70_SWAP_STD;
340 default:
341 R600_ERR("unsupported colorswap format %d\n", format);
342 return ~0U;
343 }
344 return ~0U;
345 }
346
347 static uint32_t si_translate_colorformat(enum pipe_format format)
348 {
349 switch (format) {
350 /* 8-bit buffers. */
351 case PIPE_FORMAT_A8_UNORM:
352 case PIPE_FORMAT_A8_UINT:
353 case PIPE_FORMAT_A8_SINT:
354 case PIPE_FORMAT_I8_UNORM:
355 case PIPE_FORMAT_I8_UINT:
356 case PIPE_FORMAT_I8_SINT:
357 case PIPE_FORMAT_L8_UNORM:
358 case PIPE_FORMAT_L8_UINT:
359 case PIPE_FORMAT_L8_SINT:
360 case PIPE_FORMAT_L8_SRGB:
361 case PIPE_FORMAT_R8_UNORM:
362 case PIPE_FORMAT_R8_SNORM:
363 case PIPE_FORMAT_R8_UINT:
364 case PIPE_FORMAT_R8_SINT:
365 return V_028C70_COLOR_8;
366
367 /* 16-bit buffers. */
368 case PIPE_FORMAT_B5G6R5_UNORM:
369 return V_028C70_COLOR_5_6_5;
370
371 case PIPE_FORMAT_B5G5R5A1_UNORM:
372 case PIPE_FORMAT_B5G5R5X1_UNORM:
373 return V_028C70_COLOR_1_5_5_5;
374
375 case PIPE_FORMAT_B4G4R4A4_UNORM:
376 case PIPE_FORMAT_B4G4R4X4_UNORM:
377 return V_028C70_COLOR_4_4_4_4;
378
379 case PIPE_FORMAT_L8A8_UNORM:
380 case PIPE_FORMAT_L8A8_UINT:
381 case PIPE_FORMAT_L8A8_SINT:
382 case PIPE_FORMAT_L8A8_SRGB:
383 case PIPE_FORMAT_R8G8_UNORM:
384 case PIPE_FORMAT_R8G8_UINT:
385 case PIPE_FORMAT_R8G8_SINT:
386 return V_028C70_COLOR_8_8;
387
388 case PIPE_FORMAT_Z16_UNORM:
389 case PIPE_FORMAT_R16_UNORM:
390 case PIPE_FORMAT_R16_UINT:
391 case PIPE_FORMAT_R16_SINT:
392 case PIPE_FORMAT_R16_FLOAT:
393 case PIPE_FORMAT_R16G16_FLOAT:
394 return V_028C70_COLOR_16;
395
396 /* 32-bit buffers. */
397 case PIPE_FORMAT_A8B8G8R8_SRGB:
398 case PIPE_FORMAT_A8B8G8R8_UNORM:
399 case PIPE_FORMAT_A8R8G8B8_UNORM:
400 case PIPE_FORMAT_B8G8R8A8_SRGB:
401 case PIPE_FORMAT_B8G8R8A8_UNORM:
402 case PIPE_FORMAT_B8G8R8X8_UNORM:
403 case PIPE_FORMAT_R8G8B8A8_SNORM:
404 case PIPE_FORMAT_R8G8B8A8_UNORM:
405 case PIPE_FORMAT_R8G8B8X8_UNORM:
406 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
407 case PIPE_FORMAT_X8B8G8R8_UNORM:
408 case PIPE_FORMAT_X8R8G8B8_UNORM:
409 case PIPE_FORMAT_R8G8B8_UNORM:
410 case PIPE_FORMAT_R8G8B8A8_SSCALED:
411 case PIPE_FORMAT_R8G8B8A8_USCALED:
412 case PIPE_FORMAT_R8G8B8A8_SINT:
413 case PIPE_FORMAT_R8G8B8A8_UINT:
414 return V_028C70_COLOR_8_8_8_8;
415
416 case PIPE_FORMAT_R10G10B10A2_UNORM:
417 case PIPE_FORMAT_R10G10B10X2_SNORM:
418 case PIPE_FORMAT_B10G10R10A2_UNORM:
419 case PIPE_FORMAT_B10G10R10A2_UINT:
420 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
421 return V_028C70_COLOR_2_10_10_10;
422
423 case PIPE_FORMAT_Z24X8_UNORM:
424 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
425 return V_028C70_COLOR_8_24;
426
427 case PIPE_FORMAT_X8Z24_UNORM:
428 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
429 return V_028C70_COLOR_24_8;
430
431 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
432 return V_028C70_COLOR_X24_8_32_FLOAT;
433
434 case PIPE_FORMAT_R32_FLOAT:
435 case PIPE_FORMAT_Z32_FLOAT:
436 return V_028C70_COLOR_32;
437
438 case PIPE_FORMAT_R16G16_SSCALED:
439 case PIPE_FORMAT_R16G16_UNORM:
440 case PIPE_FORMAT_R16G16_UINT:
441 case PIPE_FORMAT_R16G16_SINT:
442 return V_028C70_COLOR_16_16;
443
444 case PIPE_FORMAT_R11G11B10_FLOAT:
445 return V_028C70_COLOR_10_11_11;
446
447 /* 64-bit buffers. */
448 case PIPE_FORMAT_R16G16B16_USCALED:
449 case PIPE_FORMAT_R16G16B16_SSCALED:
450 case PIPE_FORMAT_R16G16B16A16_UINT:
451 case PIPE_FORMAT_R16G16B16A16_SINT:
452 case PIPE_FORMAT_R16G16B16A16_USCALED:
453 case PIPE_FORMAT_R16G16B16A16_SSCALED:
454 case PIPE_FORMAT_R16G16B16A16_UNORM:
455 case PIPE_FORMAT_R16G16B16A16_SNORM:
456 case PIPE_FORMAT_R16G16B16_FLOAT:
457 case PIPE_FORMAT_R16G16B16A16_FLOAT:
458 return V_028C70_COLOR_16_16_16_16;
459
460 case PIPE_FORMAT_R32G32_FLOAT:
461 case PIPE_FORMAT_R32G32_USCALED:
462 case PIPE_FORMAT_R32G32_SSCALED:
463 case PIPE_FORMAT_R32G32_SINT:
464 case PIPE_FORMAT_R32G32_UINT:
465 return V_028C70_COLOR_32_32;
466
467 /* 128-bit buffers. */
468 case PIPE_FORMAT_R32G32B32A32_SNORM:
469 case PIPE_FORMAT_R32G32B32A32_UNORM:
470 case PIPE_FORMAT_R32G32B32A32_SSCALED:
471 case PIPE_FORMAT_R32G32B32A32_USCALED:
472 case PIPE_FORMAT_R32G32B32A32_SINT:
473 case PIPE_FORMAT_R32G32B32A32_UINT:
474 case PIPE_FORMAT_R32G32B32A32_FLOAT:
475 return V_028C70_COLOR_32_32_32_32;
476
477 /* YUV buffers. */
478 case PIPE_FORMAT_UYVY:
479 case PIPE_FORMAT_YUYV:
480 /* 96-bit buffers. */
481 case PIPE_FORMAT_R32G32B32_FLOAT:
482 /* 8-bit buffers. */
483 case PIPE_FORMAT_L4A4_UNORM:
484 case PIPE_FORMAT_R4A4_UNORM:
485 case PIPE_FORMAT_A4R4_UNORM:
486 default:
487 return ~0U; /* Unsupported. */
488 }
489 }
490
491 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
492 {
493 if (R600_BIG_ENDIAN) {
494 switch(colorformat) {
495 /* 8-bit buffers. */
496 case V_028C70_COLOR_8:
497 return V_028C70_ENDIAN_NONE;
498
499 /* 16-bit buffers. */
500 case V_028C70_COLOR_5_6_5:
501 case V_028C70_COLOR_1_5_5_5:
502 case V_028C70_COLOR_4_4_4_4:
503 case V_028C70_COLOR_16:
504 case V_028C70_COLOR_8_8:
505 return V_028C70_ENDIAN_8IN16;
506
507 /* 32-bit buffers. */
508 case V_028C70_COLOR_8_8_8_8:
509 case V_028C70_COLOR_2_10_10_10:
510 case V_028C70_COLOR_8_24:
511 case V_028C70_COLOR_24_8:
512 case V_028C70_COLOR_16_16:
513 return V_028C70_ENDIAN_8IN32;
514
515 /* 64-bit buffers. */
516 case V_028C70_COLOR_16_16_16_16:
517 return V_028C70_ENDIAN_8IN16;
518
519 case V_028C70_COLOR_32_32:
520 return V_028C70_ENDIAN_8IN32;
521
522 /* 128-bit buffers. */
523 case V_028C70_COLOR_32_32_32_32:
524 return V_028C70_ENDIAN_8IN32;
525 default:
526 return V_028C70_ENDIAN_NONE; /* Unsupported. */
527 }
528 } else {
529 return V_028C70_ENDIAN_NONE;
530 }
531 }
532
533 static uint32_t si_translate_texformat(struct pipe_screen *screen,
534 enum pipe_format format,
535 const struct util_format_description *desc,
536 int first_non_void)
537 {
538 boolean uniform = TRUE;
539 int i;
540
541 /* Colorspace (return non-RGB formats directly). */
542 switch (desc->colorspace) {
543 /* Depth stencil formats */
544 case UTIL_FORMAT_COLORSPACE_ZS:
545 switch (format) {
546 case PIPE_FORMAT_Z16_UNORM:
547 return V_008F14_IMG_DATA_FORMAT_16;
548 case PIPE_FORMAT_X24S8_UINT:
549 case PIPE_FORMAT_Z24X8_UNORM:
550 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
551 return V_008F14_IMG_DATA_FORMAT_24_8;
552 case PIPE_FORMAT_S8X24_UINT:
553 case PIPE_FORMAT_X8Z24_UNORM:
554 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
555 return V_008F14_IMG_DATA_FORMAT_8_24;
556 case PIPE_FORMAT_S8_UINT:
557 return V_008F14_IMG_DATA_FORMAT_8;
558 case PIPE_FORMAT_Z32_FLOAT:
559 return V_008F14_IMG_DATA_FORMAT_32;
560 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
561 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
562 default:
563 goto out_unknown;
564 }
565
566 case UTIL_FORMAT_COLORSPACE_YUV:
567 goto out_unknown; /* TODO */
568
569 case UTIL_FORMAT_COLORSPACE_SRGB:
570 break;
571
572 default:
573 break;
574 }
575
576 /* TODO compressed formats */
577
578 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
579 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
580 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
581 return V_008F14_IMG_DATA_FORMAT_10_11_11;
582 }
583
584 /* R8G8Bx_SNORM - TODO CxV8U8 */
585
586 /* See whether the components are of the same size. */
587 for (i = 1; i < desc->nr_channels; i++) {
588 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
589 }
590
591 /* Non-uniform formats. */
592 if (!uniform) {
593 switch(desc->nr_channels) {
594 case 3:
595 if (desc->channel[0].size == 5 &&
596 desc->channel[1].size == 6 &&
597 desc->channel[2].size == 5) {
598 return V_008F14_IMG_DATA_FORMAT_5_6_5;
599 }
600 goto out_unknown;
601 case 4:
602 if (desc->channel[0].size == 5 &&
603 desc->channel[1].size == 5 &&
604 desc->channel[2].size == 5 &&
605 desc->channel[3].size == 1) {
606 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
607 }
608 if (desc->channel[0].size == 10 &&
609 desc->channel[1].size == 10 &&
610 desc->channel[2].size == 10 &&
611 desc->channel[3].size == 2) {
612 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
613 }
614 goto out_unknown;
615 }
616 goto out_unknown;
617 }
618
619 if (first_non_void < 0 || first_non_void > 3)
620 goto out_unknown;
621
622 /* uniform formats */
623 switch (desc->channel[first_non_void].size) {
624 case 4:
625 switch (desc->nr_channels) {
626 case 2:
627 return V_008F14_IMG_DATA_FORMAT_4_4;
628 case 4:
629 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
630 }
631 break;
632 case 8:
633 switch (desc->nr_channels) {
634 case 1:
635 return V_008F14_IMG_DATA_FORMAT_8;
636 case 2:
637 return V_008F14_IMG_DATA_FORMAT_8_8;
638 case 4:
639 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
640 }
641 break;
642 case 16:
643 switch (desc->nr_channels) {
644 case 1:
645 return V_008F14_IMG_DATA_FORMAT_16;
646 case 2:
647 return V_008F14_IMG_DATA_FORMAT_16_16;
648 case 4:
649 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
650 }
651 break;
652 case 32:
653 switch (desc->nr_channels) {
654 case 1:
655 return V_008F14_IMG_DATA_FORMAT_32;
656 case 2:
657 return V_008F14_IMG_DATA_FORMAT_32_32;
658 case 3:
659 return V_008F14_IMG_DATA_FORMAT_32_32_32;
660 case 4:
661 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
662 }
663 }
664
665 out_unknown:
666 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
667 return ~0;
668 }
669
670 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
671 {
672 return si_translate_texformat(screen, format, util_format_description(format),
673 util_format_get_first_non_void_channel(format)) != ~0U;
674 }
675
676 uint32_t si_translate_vertexformat(struct pipe_screen *screen,
677 enum pipe_format format,
678 const struct util_format_description *desc,
679 int first_non_void)
680 {
681 uint32_t result;
682
683 if (desc->channel[first_non_void].type == UTIL_FORMAT_TYPE_FIXED)
684 return ~0;
685
686 result = si_translate_texformat(screen, format, desc, first_non_void);
687 if (result == V_008F0C_BUF_DATA_FORMAT_INVALID ||
688 result > V_008F0C_BUF_DATA_FORMAT_32_32_32_32)
689 result = ~0;
690
691 return result;
692 }
693
694 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
695 {
696 return si_translate_vertexformat(screen, format, util_format_description(format),
697 util_format_get_first_non_void_channel(format)) != ~0U;
698 }
699
700 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
701 {
702 return si_translate_colorformat(format) != ~0U &&
703 si_translate_colorswap(format) != ~0U;
704 }
705
706 static bool r600_is_zs_format_supported(enum pipe_format format)
707 {
708 return si_translate_dbformat(format) != ~0U;
709 }
710
711 boolean si_is_format_supported(struct pipe_screen *screen,
712 enum pipe_format format,
713 enum pipe_texture_target target,
714 unsigned sample_count,
715 unsigned usage)
716 {
717 unsigned retval = 0;
718
719 if (target >= PIPE_MAX_TEXTURE_TYPES) {
720 R600_ERR("r600: unsupported texture type %d\n", target);
721 return FALSE;
722 }
723
724 if (!util_format_is_supported(format, usage))
725 return FALSE;
726
727 /* Multisample */
728 if (sample_count > 1)
729 return FALSE;
730
731 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
732 si_is_sampler_format_supported(screen, format)) {
733 retval |= PIPE_BIND_SAMPLER_VIEW;
734 }
735
736 if ((usage & (PIPE_BIND_RENDER_TARGET |
737 PIPE_BIND_DISPLAY_TARGET |
738 PIPE_BIND_SCANOUT |
739 PIPE_BIND_SHARED)) &&
740 r600_is_colorbuffer_format_supported(format)) {
741 retval |= usage &
742 (PIPE_BIND_RENDER_TARGET |
743 PIPE_BIND_DISPLAY_TARGET |
744 PIPE_BIND_SCANOUT |
745 PIPE_BIND_SHARED);
746 }
747
748 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
749 r600_is_zs_format_supported(format)) {
750 retval |= PIPE_BIND_DEPTH_STENCIL;
751 }
752
753 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
754 si_is_vertex_format_supported(screen, format)) {
755 retval |= PIPE_BIND_VERTEX_BUFFER;
756 }
757
758 if (usage & PIPE_BIND_TRANSFER_READ)
759 retval |= PIPE_BIND_TRANSFER_READ;
760 if (usage & PIPE_BIND_TRANSFER_WRITE)
761 retval |= PIPE_BIND_TRANSFER_WRITE;
762
763 return retval == usage;
764 }
765
766 static void evergreen_set_blend_color(struct pipe_context *ctx,
767 const struct pipe_blend_color *state)
768 {
769 struct r600_context *rctx = (struct r600_context *)ctx;
770 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
771
772 if (rstate == NULL)
773 return;
774
775 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
776 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), NULL, 0);
777 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), NULL, 0);
778 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), NULL, 0);
779 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), NULL, 0);
780
781 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
782 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
783 r600_context_pipe_state_set(rctx, rstate);
784 }
785
786 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
787 const struct pipe_depth_stencil_alpha_state *state)
788 {
789 struct r600_context *rctx = (struct r600_context *)ctx;
790 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
791 unsigned db_depth_control, alpha_test_control, alpha_ref;
792 unsigned db_render_override, db_render_control;
793 struct r600_pipe_state *rstate;
794
795 if (dsa == NULL) {
796 return NULL;
797 }
798
799 dsa->valuemask[0] = state->stencil[0].valuemask;
800 dsa->valuemask[1] = state->stencil[1].valuemask;
801 dsa->writemask[0] = state->stencil[0].writemask;
802 dsa->writemask[1] = state->stencil[1].writemask;
803
804 rstate = &dsa->rstate;
805
806 rstate->id = R600_PIPE_STATE_DSA;
807 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
808 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
809 S_028800_ZFUNC(state->depth.func);
810
811 /* stencil */
812 if (state->stencil[0].enabled) {
813 db_depth_control |= S_028800_STENCIL_ENABLE(1);
814 db_depth_control |= S_028800_STENCILFUNC(si_translate_ds_func(state->stencil[0].func));
815 //db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
816 //db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
817 //db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
818
819 if (state->stencil[1].enabled) {
820 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
821 db_depth_control |= S_028800_STENCILFUNC_BF(si_translate_ds_func(state->stencil[1].func));
822 //db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
823 //db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
824 //db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
825 }
826 }
827
828 /* alpha */
829 alpha_test_control = 0;
830 alpha_ref = 0;
831 if (state->alpha.enabled) {
832 //alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
833 //alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
834 alpha_ref = fui(state->alpha.ref_value);
835 }
836 dsa->alpha_ref = alpha_ref;
837
838 /* misc */
839 db_render_control = 0;
840 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
841 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
842 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
843 /* TODO db_render_override depends on query */
844 r600_pipe_state_add_reg(rstate, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000, NULL, 0);
845 r600_pipe_state_add_reg(rstate, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000, NULL, 0);
846 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, NULL, 0);
847 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, NULL, 0);
848 //r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, NULL, 0);
849 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, NULL, 0);
850 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, NULL, 0);
851 r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, NULL, 0);
852 r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, NULL, 0);
853 r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, NULL, 0);
854 r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, NULL, 0);
855 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, NULL, 0);
856 dsa->db_render_override = db_render_override;
857
858 return rstate;
859 }
860
861 static void *evergreen_create_rs_state(struct pipe_context *ctx,
862 const struct pipe_rasterizer_state *state)
863 {
864 struct r600_context *rctx = (struct r600_context *)ctx;
865 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
866 struct r600_pipe_state *rstate;
867 unsigned tmp;
868 unsigned prov_vtx = 1, polygon_dual_mode;
869 unsigned clip_rule;
870 float psize_min, psize_max;
871
872 if (rs == NULL) {
873 return NULL;
874 }
875
876 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
877 state->fill_back != PIPE_POLYGON_MODE_FILL);
878
879 if (state->flatshade_first)
880 prov_vtx = 0;
881
882 rstate = &rs->rstate;
883 rs->flatshade = state->flatshade;
884 rs->sprite_coord_enable = state->sprite_coord_enable;
885 rs->pa_sc_line_stipple = state->line_stipple_enable ?
886 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
887 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
888 rs->pa_su_sc_mode_cntl =
889 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
890 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
891 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
892 S_028814_FACE(!state->front_ccw) |
893 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
894 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
895 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
896 S_028814_POLY_MODE(polygon_dual_mode) |
897 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
898 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
899 rs->pa_cl_clip_cntl =
900 S_028810_PS_UCP_MODE(3) |
901 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
902 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
903 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
904 rs->pa_cl_vs_out_cntl =
905 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
906 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
907
908 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
909
910 /* offset */
911 rs->offset_units = state->offset_units;
912 rs->offset_scale = state->offset_scale * 12.0f;
913
914 rstate->id = R600_PIPE_STATE_RASTERIZER;
915 /* XXX: Flat shading hangs the GPU */
916 tmp = S_0286D4_FLAT_SHADE_ENA(0);
917 if (state->sprite_coord_enable) {
918 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
919 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
920 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
921 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
922 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
923 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
924 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
925 }
926 }
927 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, NULL, 0);
928
929 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, NULL, 0);
930 /* point size 12.4 fixed point */
931 tmp = (unsigned)(state->point_size * 8.0);
932 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), NULL, 0);
933
934 if (state->point_size_per_vertex) {
935 psize_min = util_get_min_point_size(state);
936 psize_max = 8192;
937 } else {
938 /* Force the point size to be as if the vertex output was disabled. */
939 psize_min = state->point_size;
940 psize_max = state->point_size;
941 }
942 /* Divide by two, because 0.5 = 1 pixel. */
943 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
944 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
945 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)),
946 NULL, 0);
947
948 tmp = (unsigned)state->line_width * 8;
949 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), NULL, 0);
950 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
951 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable),
952 NULL, 0);
953
954 r600_pipe_state_add_reg(rstate, R_028BDC_PA_SC_LINE_CNTL, 0x00000400, NULL, 0);
955 r600_pipe_state_add_reg(rstate, R_028BE4_PA_SU_VTX_CNTL,
956 S_028BE4_PIX_CENTER(state->gl_rasterization_rules),
957 NULL, 0);
958 r600_pipe_state_add_reg(rstate, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, NULL, 0);
959 r600_pipe_state_add_reg(rstate, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, NULL, 0);
960 r600_pipe_state_add_reg(rstate, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, NULL, 0);
961 r600_pipe_state_add_reg(rstate, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, NULL, 0);
962
963 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), NULL, 0);
964 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, NULL, 0);
965 return rstate;
966 }
967
968 static void *si_create_sampler_state(struct pipe_context *ctx,
969 const struct pipe_sampler_state *state)
970 {
971 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
972 union util_color uc;
973 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
974 unsigned border_color_type;
975
976 if (rstate == NULL) {
977 return NULL;
978 }
979
980 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
981 switch (uc.ui) {
982 case 0x000000FF:
983 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
984 break;
985 case 0x00000000:
986 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
987 break;
988 case 0xFFFFFFFF:
989 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
990 break;
991 default: /* Use border color pointer */
992 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
993 }
994
995 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
996 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
997 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
998 (state->max_anisotropy & 0x7) << 9 | /* XXX */
999 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
1000 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
1001 aniso_flag_offset << 16 | /* XXX */
1002 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
1003 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
1004 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
1005 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
1006 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
1007 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
1008 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
1009 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
1010
1011 #if 0
1012 if (border_color_type == 3) {
1013 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0);
1014 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0);
1015 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0);
1016 r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0);
1017 }
1018 #endif
1019 return rstate;
1020 }
1021
1022 static void si_delete_sampler_state(struct pipe_context *ctx,
1023 void *state)
1024 {
1025 free(state);
1026 }
1027
1028 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
1029 struct pipe_resource *texture,
1030 const struct pipe_sampler_view *state)
1031 {
1032 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
1033 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
1034 const struct util_format_description *desc = util_format_description(state->format);
1035 unsigned blocksize = util_format_get_blocksize(tmp->real_format);
1036 unsigned format, num_format, endian, tiling_index;
1037 uint32_t pitch = 0;
1038 unsigned char state_swizzle[4], swizzle[4];
1039 unsigned height, depth, width;
1040 int first_non_void;
1041 uint64_t va;
1042
1043 if (view == NULL)
1044 return NULL;
1045
1046 /* initialize base object */
1047 view->base = *state;
1048 view->base.texture = NULL;
1049 pipe_reference(NULL, &texture->reference);
1050 view->base.texture = texture;
1051 view->base.reference.count = 1;
1052 view->base.context = ctx;
1053
1054 state_swizzle[0] = state->swizzle_r;
1055 state_swizzle[1] = state->swizzle_g;
1056 state_swizzle[2] = state->swizzle_b;
1057 state_swizzle[3] = state->swizzle_a;
1058 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
1059
1060 first_non_void = util_format_get_first_non_void_channel(state->format);
1061 switch (desc->channel[first_non_void].type) {
1062 case UTIL_FORMAT_TYPE_FLOAT:
1063 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
1064 break;
1065 case UTIL_FORMAT_TYPE_SIGNED:
1066 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
1067 break;
1068 case UTIL_FORMAT_TYPE_UNSIGNED:
1069 default:
1070 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
1071 }
1072
1073 format = si_translate_texformat(ctx->screen, state->format, desc, first_non_void);
1074 if (format == ~0) {
1075 format = 0;
1076 }
1077
1078 if (tmp->depth && !tmp->is_flushing_texture) {
1079 r600_texture_depth_flush(ctx, texture, TRUE);
1080 tmp = tmp->flushed_depth_texture;
1081 }
1082
1083 endian = si_colorformat_endian_swap(format);
1084
1085 height = texture->height0;
1086 depth = texture->depth0;
1087 width = texture->width0;
1088 pitch = align(tmp->pitch_in_blocks[0] *
1089 util_format_get_blockwidth(state->format), 8);
1090
1091 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1092 height = 1;
1093 depth = texture->array_size;
1094 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1095 depth = texture->array_size;
1096 }
1097
1098 tiling_index = 8;
1099 switch (tmp->surface.level[state->u.tex.first_level].mode) {
1100 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1101 tiling_index = 8;
1102 break;
1103 case RADEON_SURF_MODE_1D:
1104 tiling_index = 9;
1105 break;
1106 case RADEON_SURF_MODE_2D:
1107 if (tmp->resource.b.b.bind & PIPE_BIND_SCANOUT) {
1108 switch (blocksize) {
1109 case 1:
1110 tiling_index = 10;
1111 break;
1112 case 2:
1113 tiling_index = 11;
1114 break;
1115 case 4:
1116 tiling_index = 12;
1117 break;
1118 }
1119 break;
1120 } else switch (blocksize) {
1121 case 1:
1122 tiling_index = 14;
1123 break;
1124 case 2:
1125 tiling_index = 15;
1126 break;
1127 case 4:
1128 tiling_index = 16;
1129 break;
1130 case 8:
1131 tiling_index = 17;
1132 break;
1133 default:
1134 tiling_index = 13;
1135 }
1136 break;
1137 }
1138
1139 va = r600_resource_va(ctx->screen, texture);
1140 if (state->u.tex.last_level) {
1141 view->state[0] = (va + tmp->offset[1]) >> 8;
1142 } else {
1143 view->state[0] = (va + tmp->offset[0]) >> 8;
1144 }
1145 view->state[1] = (S_008F14_BASE_ADDRESS_HI((va + tmp->offset[0]) >> 40) |
1146 S_008F14_DATA_FORMAT(format) |
1147 S_008F14_NUM_FORMAT(num_format));
1148 view->state[2] = (S_008F18_WIDTH(width - 1) |
1149 S_008F18_HEIGHT(height - 1));
1150 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
1151 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
1152 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
1153 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
1154 S_008F1C_BASE_LEVEL(state->u.tex.first_level) |
1155 S_008F1C_LAST_LEVEL(state->u.tex.last_level) |
1156 S_008F1C_TILING_INDEX(tiling_index) |
1157 S_008F1C_TYPE(si_tex_dim(texture->target)));
1158 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
1159 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
1160 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
1161 view->state[6] = 0;
1162 view->state[7] = 0;
1163
1164 return &view->base;
1165 }
1166
1167 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1168 struct pipe_sampler_view **views)
1169 {
1170 }
1171
1172 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1173 struct pipe_sampler_view **views)
1174 {
1175 struct r600_context *rctx = (struct r600_context *)ctx;
1176 struct si_pipe_sampler_view **resource = (struct si_pipe_sampler_view **)views;
1177 struct r600_pipe_state *rstate = &rctx->ps_samplers.views_state;
1178 struct r600_resource *bo;
1179 int i;
1180 int has_depth = 0;
1181 uint64_t va;
1182 char *ptr;
1183
1184 if (!count)
1185 goto out;
1186
1187 r600_inval_texture_cache(rctx);
1188
1189 bo = (struct r600_resource*)
1190 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
1191 count * sizeof(resource[0]->state));
1192 ptr = rctx->ws->buffer_map(bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
1193
1194 for (i = 0; i < count; i++, ptr += sizeof(resource[0]->state)) {
1195 pipe_sampler_view_reference(
1196 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
1197 views[i]);
1198
1199 if (resource[i]) {
1200 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1201 has_depth = 1;
1202
1203 memcpy(ptr, resource[i]->state, sizeof(resource[0]->state));
1204 } else
1205 memset(ptr, 0, sizeof(resource[0]->state));
1206 }
1207
1208 rctx->ws->buffer_unmap(bo->cs_buf);
1209
1210 for (i = count; i < NUM_TEX_UNITS; i++) {
1211 if (rctx->ps_samplers.views[i])
1212 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
1213 }
1214
1215 rstate->nregs = 0;
1216 va = r600_resource_va(ctx->screen, (void *)bo);
1217 r600_pipe_state_add_reg(rstate, R_00B040_SPI_SHADER_USER_DATA_PS_4, va, bo, RADEON_USAGE_READ);
1218 r600_pipe_state_add_reg(rstate, R_00B044_SPI_SHADER_USER_DATA_PS_5, va >> 32, NULL, 0);
1219 r600_context_pipe_state_set(rctx, rstate);
1220
1221 out:
1222 rctx->have_depth_texture = has_depth;
1223 rctx->ps_samplers.n_views = count;
1224 }
1225
1226 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1227 {
1228 struct r600_context *rctx = (struct r600_context *)ctx;
1229 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
1230 struct r600_pipe_state *rstate = &rctx->ps_samplers.samplers_state;
1231 struct r600_resource *bo;
1232 uint64_t va;
1233 char *ptr;
1234 int i;
1235
1236 if (!count)
1237 goto out;
1238
1239 r600_inval_texture_cache(rctx);
1240
1241 bo = (struct r600_resource*)
1242 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
1243 count * sizeof(rstates[0]->val));
1244 ptr = rctx->ws->buffer_map(bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
1245
1246 for (i = 0; i < count; i++, ptr += sizeof(rstates[0]->val)) {
1247 memcpy(ptr, rstates[i]->val, sizeof(rstates[0]->val));
1248 }
1249
1250 rctx->ws->buffer_unmap(bo->cs_buf);
1251
1252 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
1253
1254 rstate->nregs = 0;
1255 va = r600_resource_va(ctx->screen, (void *)bo);
1256 r600_pipe_state_add_reg(rstate, R_00B038_SPI_SHADER_USER_DATA_PS_2, va, bo, RADEON_USAGE_READ);
1257 r600_pipe_state_add_reg(rstate, R_00B03C_SPI_SHADER_USER_DATA_PS_3, va >> 32, NULL, 0);
1258 r600_context_pipe_state_set(rctx, rstate);
1259
1260 out:
1261 rctx->ps_samplers.n_samplers = count;
1262 }
1263
1264 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1265 {
1266 }
1267
1268 static void evergreen_set_clip_state(struct pipe_context *ctx,
1269 const struct pipe_clip_state *state)
1270 {
1271 struct r600_context *rctx = (struct r600_context *)ctx;
1272 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1273
1274 if (rstate == NULL)
1275 return;
1276
1277 rctx->clip = *state;
1278 rstate->id = R600_PIPE_STATE_CLIP;
1279 for (int i = 0; i < 6; i++) {
1280 r600_pipe_state_add_reg(rstate,
1281 R_0285BC_PA_CL_UCP_0_X + i * 16,
1282 fui(state->ucp[i][0]), NULL, 0);
1283 r600_pipe_state_add_reg(rstate,
1284 R_0285C0_PA_CL_UCP_0_Y + i * 16,
1285 fui(state->ucp[i][1]) , NULL, 0);
1286 r600_pipe_state_add_reg(rstate,
1287 R_0285C4_PA_CL_UCP_0_Z + i * 16,
1288 fui(state->ucp[i][2]), NULL, 0);
1289 r600_pipe_state_add_reg(rstate,
1290 R_0285C8_PA_CL_UCP_0_W + i * 16,
1291 fui(state->ucp[i][3]), NULL, 0);
1292 }
1293
1294 free(rctx->states[R600_PIPE_STATE_CLIP]);
1295 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1296 r600_context_pipe_state_set(rctx, rstate);
1297 }
1298
1299 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1300 const struct pipe_poly_stipple *state)
1301 {
1302 }
1303
1304 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1305 {
1306 }
1307
1308 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1309 const struct pipe_scissor_state *state)
1310 {
1311 struct r600_context *rctx = (struct r600_context *)ctx;
1312 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1313 uint32_t tl, br;
1314
1315 if (rstate == NULL)
1316 return;
1317
1318 rstate->id = R600_PIPE_STATE_SCISSOR;
1319 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
1320 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1321 r600_pipe_state_add_reg(rstate,
1322 R_028210_PA_SC_CLIPRECT_0_TL, tl,
1323 NULL, 0);
1324 r600_pipe_state_add_reg(rstate,
1325 R_028214_PA_SC_CLIPRECT_0_BR, br,
1326 NULL, 0);
1327 r600_pipe_state_add_reg(rstate,
1328 R_028218_PA_SC_CLIPRECT_1_TL, tl,
1329 NULL, 0);
1330 r600_pipe_state_add_reg(rstate,
1331 R_02821C_PA_SC_CLIPRECT_1_BR, br,
1332 NULL, 0);
1333 r600_pipe_state_add_reg(rstate,
1334 R_028220_PA_SC_CLIPRECT_2_TL, tl,
1335 NULL, 0);
1336 r600_pipe_state_add_reg(rstate,
1337 R_028224_PA_SC_CLIPRECT_2_BR, br,
1338 NULL, 0);
1339 r600_pipe_state_add_reg(rstate,
1340 R_028228_PA_SC_CLIPRECT_3_TL, tl,
1341 NULL, 0);
1342 r600_pipe_state_add_reg(rstate,
1343 R_02822C_PA_SC_CLIPRECT_3_BR, br,
1344 NULL, 0);
1345
1346 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1347 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1348 r600_context_pipe_state_set(rctx, rstate);
1349 }
1350
1351 static void evergreen_set_viewport_state(struct pipe_context *ctx,
1352 const struct pipe_viewport_state *state)
1353 {
1354 struct r600_context *rctx = (struct r600_context *)ctx;
1355 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1356
1357 if (rstate == NULL)
1358 return;
1359
1360 rctx->viewport = *state;
1361 rstate->id = R600_PIPE_STATE_VIEWPORT;
1362 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, NULL, 0);
1363 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, NULL, 0);
1364 r600_pipe_state_add_reg(rstate, R_028350_PA_SC_RASTER_CONFIG, 0x00000000, NULL, 0);
1365 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), NULL, 0);
1366 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), NULL, 0);
1367 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), NULL, 0);
1368 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), NULL, 0);
1369 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), NULL, 0);
1370 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), NULL, 0);
1371 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, NULL, 0);
1372
1373 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1374 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1375 r600_context_pipe_state_set(rctx, rstate);
1376 }
1377
1378 static void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
1379 const struct pipe_framebuffer_state *state, int cb)
1380 {
1381 struct r600_resource_texture *rtex;
1382 struct r600_surface *surf;
1383 unsigned level = state->cbufs[cb]->u.tex.level;
1384 unsigned pitch, slice;
1385 unsigned color_info, color_attrib;
1386 unsigned format, swap, ntype, endian;
1387 uint64_t offset;
1388 unsigned blocksize;
1389 const struct util_format_description *desc;
1390 int i;
1391 unsigned blend_clamp = 0, blend_bypass = 0;
1392
1393 surf = (struct r600_surface *)state->cbufs[cb];
1394 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1395 blocksize = util_format_get_blocksize(rtex->real_format);
1396
1397 if (rtex->depth)
1398 rctx->have_depth_fb = TRUE;
1399
1400 if (rtex->depth && !rtex->is_flushing_texture) {
1401 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1402 rtex = rtex->flushed_depth_texture;
1403 }
1404
1405 offset = rtex->surface.level[level].offset;
1406 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1407 offset += rtex->surface.level[level].slice_size *
1408 state->cbufs[cb]->u.tex.first_layer;
1409 }
1410 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1411 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1412 if (slice) {
1413 slice = slice - 1;
1414 }
1415
1416 color_attrib = S_028C74_TILE_MODE_INDEX(8);
1417 switch (rtex->surface.level[level].mode) {
1418 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1419 color_attrib = S_028C74_TILE_MODE_INDEX(8);
1420 break;
1421 case RADEON_SURF_MODE_1D:
1422 color_attrib = S_028C74_TILE_MODE_INDEX(9);
1423 break;
1424 case RADEON_SURF_MODE_2D:
1425 if (rtex->resource.b.b.bind & PIPE_BIND_SCANOUT) {
1426 switch (blocksize) {
1427 case 1:
1428 color_attrib = S_028C74_TILE_MODE_INDEX(10);
1429 break;
1430 case 2:
1431 color_attrib = S_028C74_TILE_MODE_INDEX(11);
1432 break;
1433 case 4:
1434 color_attrib = S_028C74_TILE_MODE_INDEX(12);
1435 break;
1436 }
1437 break;
1438 } else switch (blocksize) {
1439 case 1:
1440 color_attrib = S_028C74_TILE_MODE_INDEX(14);
1441 break;
1442 case 2:
1443 color_attrib = S_028C74_TILE_MODE_INDEX(15);
1444 break;
1445 case 4:
1446 color_attrib = S_028C74_TILE_MODE_INDEX(16);
1447 break;
1448 case 8:
1449 color_attrib = S_028C74_TILE_MODE_INDEX(17);
1450 break;
1451 default:
1452 color_attrib = S_028C74_TILE_MODE_INDEX(13);
1453 }
1454 break;
1455 }
1456
1457 desc = util_format_description(surf->base.format);
1458 for (i = 0; i < 4; i++) {
1459 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1460 break;
1461 }
1462 }
1463 if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1464 ntype = V_028C70_NUMBER_FLOAT;
1465 } else {
1466 ntype = V_028C70_NUMBER_UNORM;
1467 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1468 ntype = V_028C70_NUMBER_SRGB;
1469 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1470 if (desc->channel[i].normalized)
1471 ntype = V_028C70_NUMBER_SNORM;
1472 else if (desc->channel[i].pure_integer)
1473 ntype = V_028C70_NUMBER_SINT;
1474 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1475 if (desc->channel[i].normalized)
1476 ntype = V_028C70_NUMBER_UNORM;
1477 else if (desc->channel[i].pure_integer)
1478 ntype = V_028C70_NUMBER_UINT;
1479 }
1480 }
1481
1482 format = si_translate_colorformat(surf->base.format);
1483 swap = si_translate_colorswap(surf->base.format);
1484 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1485 endian = V_028C70_ENDIAN_NONE;
1486 } else {
1487 endian = si_colorformat_endian_swap(format);
1488 }
1489
1490 /* blend clamp should be set for all NORM/SRGB types */
1491 if (ntype == V_028C70_NUMBER_UNORM ||
1492 ntype == V_028C70_NUMBER_SNORM ||
1493 ntype == V_028C70_NUMBER_SRGB)
1494 blend_clamp = 1;
1495
1496 /* set blend bypass according to docs if SINT/UINT or
1497 8/24 COLOR variants */
1498 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1499 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1500 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1501 blend_clamp = 0;
1502 blend_bypass = 1;
1503 }
1504
1505 color_info = S_028C70_FORMAT(format) |
1506 S_028C70_COMP_SWAP(swap) |
1507 S_028C70_BLEND_CLAMP(blend_clamp) |
1508 S_028C70_BLEND_BYPASS(blend_bypass) |
1509 S_028C70_NUMBER_TYPE(ntype) |
1510 S_028C70_ENDIAN(endian);
1511
1512 rctx->alpha_ref_dirty = true;
1513
1514 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1515 offset >>= 8;
1516
1517 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1518 r600_pipe_state_add_reg(rstate,
1519 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
1520 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1521 r600_pipe_state_add_reg(rstate,
1522 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
1523 S_028C64_TILE_MAX(pitch),
1524 NULL, 0);
1525 r600_pipe_state_add_reg(rstate,
1526 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
1527 S_028C68_TILE_MAX(slice),
1528 NULL, 0);
1529 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1530 r600_pipe_state_add_reg(rstate,
1531 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1532 0x00000000, NULL, 0);
1533 } else {
1534 r600_pipe_state_add_reg(rstate,
1535 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1536 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1537 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer),
1538 NULL, 0);
1539 }
1540 r600_pipe_state_add_reg(rstate,
1541 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
1542 color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1543 r600_pipe_state_add_reg(rstate,
1544 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
1545 color_attrib,
1546 &rtex->resource, RADEON_USAGE_READWRITE);
1547 }
1548
1549 static void si_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
1550 const struct pipe_framebuffer_state *state)
1551 {
1552 struct r600_resource_texture *rtex;
1553 struct r600_surface *surf;
1554 unsigned level, first_layer, pitch, slice, format;
1555 uint32_t db_z_info, stencil_info;
1556 uint64_t offset;
1557
1558 if (state->zsbuf == NULL) {
1559 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO, 0, NULL, 0);
1560 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO, 0, NULL, 0);
1561 return;
1562 }
1563
1564 surf = (struct r600_surface *)state->zsbuf;
1565 level = surf->base.u.tex.level;
1566 rtex = (struct r600_resource_texture*)surf->base.texture;
1567
1568 first_layer = surf->base.u.tex.first_layer;
1569 format = si_translate_dbformat(rtex->real_format);
1570
1571 offset = r600_resource_va(rctx->context.screen, surf->base.texture);
1572 offset += rtex->surface.level[level].offset;
1573 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1574 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1575 if (slice) {
1576 slice = slice - 1;
1577 }
1578 offset >>= 8;
1579
1580 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
1581 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1582 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
1583 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1584 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1585 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1586 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer),
1587 NULL, 0);
1588
1589 db_z_info = S_028040_FORMAT(format);
1590 stencil_info = S_028044_FORMAT(rtex->stencil != 0);
1591
1592 switch (format) {
1593 case V_028040_Z_16:
1594 db_z_info |= S_028040_TILE_MODE_INDEX(5);
1595 stencil_info |= S_028044_TILE_MODE_INDEX(5);
1596 break;
1597 case V_028040_Z_24:
1598 case V_028040_Z_32_FLOAT:
1599 db_z_info |= S_028040_TILE_MODE_INDEX(6);
1600 stencil_info |= S_028044_TILE_MODE_INDEX(6);
1601 break;
1602 default:
1603 db_z_info |= S_028040_TILE_MODE_INDEX(7);
1604 stencil_info |= S_028044_TILE_MODE_INDEX(7);
1605 }
1606
1607 if (rtex->stencil) {
1608 uint64_t stencil_offset =
1609 r600_texture_get_offset(rtex->stencil, level, first_layer);
1610
1611 stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil);
1612 stencil_offset >>= 8;
1613
1614 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1615 stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1616 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1617 stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1618 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1619 stencil_info, NULL, 0);
1620 } else {
1621 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1622 0, NULL, 0);
1623 }
1624
1625 if (format != ~0U) {
1626 r600_pipe_state_add_reg(rstate, R_02803C_DB_DEPTH_INFO, 0x1, NULL, 0);
1627 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO, db_z_info, NULL, 0);
1628 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
1629 S_028058_PITCH_TILE_MAX(pitch),
1630 NULL, 0);
1631 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
1632 S_02805C_SLICE_TILE_MAX(slice),
1633 NULL, 0);
1634
1635 } else {
1636 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO, 0, NULL, 0);
1637 }
1638 }
1639
1640 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1641 const struct pipe_framebuffer_state *state)
1642 {
1643 struct r600_context *rctx = (struct r600_context *)ctx;
1644 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1645 uint32_t shader_mask, tl, br;
1646 int tl_x, tl_y, br_x, br_y;
1647
1648 if (rstate == NULL)
1649 return;
1650
1651 r600_flush_framebuffer(rctx, false);
1652
1653 /* unreference old buffer and reference new one */
1654 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1655
1656 util_copy_framebuffer_state(&rctx->framebuffer, state);
1657
1658 /* build states */
1659 rctx->have_depth_fb = 0;
1660 rctx->nr_cbufs = state->nr_cbufs;
1661 for (int i = 0; i < state->nr_cbufs; i++) {
1662 evergreen_cb(rctx, rstate, state, i);
1663 }
1664 si_db(rctx, rstate, state);
1665
1666 shader_mask = 0;
1667 for (int i = 0; i < state->nr_cbufs; i++) {
1668 shader_mask |= 0xf << (i * 4);
1669 }
1670 tl_x = 0;
1671 tl_y = 0;
1672 br_x = state->width;
1673 br_y = state->height;
1674 #if 0 /* These shouldn't be necessary on SI, see PA_SC_ENHANCE register */
1675 /* EG hw workaround */
1676 if (br_x == 0)
1677 tl_x = 1;
1678 if (br_y == 0)
1679 tl_y = 1;
1680 /* cayman hw workaround */
1681 if (rctx->chip_class == CAYMAN) {
1682 if (br_x == 1 && br_y == 1)
1683 br_x = 2;
1684 }
1685 #endif
1686 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1687 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1688
1689 r600_pipe_state_add_reg(rstate,
1690 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1691 NULL, 0);
1692 r600_pipe_state_add_reg(rstate,
1693 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1694 NULL, 0);
1695 r600_pipe_state_add_reg(rstate,
1696 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1697 NULL, 0);
1698 r600_pipe_state_add_reg(rstate,
1699 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1700 NULL, 0);
1701 r600_pipe_state_add_reg(rstate,
1702 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1703 NULL, 0);
1704 r600_pipe_state_add_reg(rstate,
1705 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1706 NULL, 0);
1707 r600_pipe_state_add_reg(rstate,
1708 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1709 NULL, 0);
1710 r600_pipe_state_add_reg(rstate,
1711 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1712 NULL, 0);
1713 r600_pipe_state_add_reg(rstate,
1714 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1715 NULL, 0);
1716 r600_pipe_state_add_reg(rstate,
1717 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1718 NULL, 0);
1719
1720 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1721 shader_mask, NULL, 0);
1722
1723 r600_pipe_state_add_reg(rstate, R_028BE0_PA_SC_AA_CONFIG,
1724 0x00000000, NULL, 0);
1725
1726 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1727 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1728 r600_context_pipe_state_set(rctx, rstate);
1729
1730 if (state->zsbuf) {
1731 cayman_polygon_offset_update(rctx);
1732 }
1733 }
1734
1735 void cayman_init_state_functions(struct r600_context *rctx)
1736 {
1737 si_init_state_functions(rctx);
1738 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1739 rctx->context.create_fs_state = si_create_shader_state;
1740 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1741 rctx->context.create_sampler_state = si_create_sampler_state;
1742 rctx->context.create_sampler_view = evergreen_create_sampler_view;
1743 rctx->context.create_vertex_elements_state = si_create_vertex_elements;
1744 rctx->context.create_vs_state = si_create_shader_state;
1745 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1746 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1747 rctx->context.bind_fs_state = r600_bind_ps_shader;
1748 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1749 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1750 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1751 rctx->context.bind_vs_state = r600_bind_vs_shader;
1752 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1753 rctx->context.delete_fs_state = r600_delete_ps_shader;
1754 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1755 rctx->context.delete_sampler_state = si_delete_sampler_state;
1756 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1757 rctx->context.delete_vs_state = r600_delete_vs_shader;
1758 rctx->context.set_blend_color = evergreen_set_blend_color;
1759 rctx->context.set_clip_state = evergreen_set_clip_state;
1760 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1761 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1762 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1763 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1764 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1765 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1766 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1767 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1768 rctx->context.set_index_buffer = r600_set_index_buffer;
1769 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1770 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1771 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1772 rctx->context.texture_barrier = r600_texture_barrier;
1773 rctx->context.create_stream_output_target = r600_create_so_target;
1774 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1775 rctx->context.set_stream_output_targets = r600_set_so_targets;
1776 }
1777
1778 void si_init_config(struct r600_context *rctx)
1779 {
1780 struct r600_pipe_state *rstate = &rctx->config;
1781 unsigned tmp;
1782
1783 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, NULL, 0);
1784
1785 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, NULL, 0);
1786 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, NULL, 0);
1787 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, NULL, 0);
1788 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, NULL, 0);
1789 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, NULL, 0);
1790 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, NULL, 0);
1791 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, NULL, 0);
1792 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, NULL, 0);
1793 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, NULL, 0);
1794 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, NULL, 0);
1795 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, NULL, 0);
1796 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, NULL, 0);
1797 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, NULL, 0);
1798 r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x0, NULL, 0);
1799 r600_pipe_state_add_reg(rstate, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0, NULL, 0);
1800 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, NULL, 0);
1801 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, NULL, 0);
1802 r600_pipe_state_add_reg(rstate, R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63), NULL, 0);
1803 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, NULL, 0);
1804 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, NULL, 0);
1805 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, NULL, 0);
1806
1807 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, NULL, 0);
1808
1809 r600_pipe_state_add_reg(rstate, R_028B54_VGT_SHADER_STAGES_EN, 0, NULL, 0);
1810 r600_pipe_state_add_reg(rstate, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210, NULL, 0);
1811 r600_pipe_state_add_reg(rstate, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98, NULL, 0);
1812
1813 r600_pipe_state_add_reg(rstate, R_028804_DB_EQAA, 0x110000, NULL, 0);
1814 r600_context_pipe_state_set(rctx, rstate);
1815 }
1816
1817 void cayman_polygon_offset_update(struct r600_context *rctx)
1818 {
1819 struct r600_pipe_state state;
1820
1821 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
1822 state.nregs = 0;
1823 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
1824 float offset_units = rctx->rasterizer->offset_units;
1825 unsigned offset_db_fmt_cntl = 0, depth;
1826
1827 switch (rctx->framebuffer.zsbuf->texture->format) {
1828 case PIPE_FORMAT_Z24X8_UNORM:
1829 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1830 depth = -24;
1831 offset_units *= 2.0f;
1832 break;
1833 case PIPE_FORMAT_Z32_FLOAT:
1834 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1835 depth = -23;
1836 offset_units *= 1.0f;
1837 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1838 break;
1839 case PIPE_FORMAT_Z16_UNORM:
1840 depth = -16;
1841 offset_units *= 4.0f;
1842 break;
1843 default:
1844 return;
1845 }
1846 /* FIXME some of those reg can be computed with cso */
1847 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
1848 r600_pipe_state_add_reg(&state,
1849 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1850 fui(rctx->rasterizer->offset_scale), NULL, 0);
1851 r600_pipe_state_add_reg(&state,
1852 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1853 fui(offset_units), NULL, 0);
1854 r600_pipe_state_add_reg(&state,
1855 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1856 fui(rctx->rasterizer->offset_scale), NULL, 0);
1857 r600_pipe_state_add_reg(&state,
1858 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1859 fui(offset_units), NULL, 0);
1860 r600_pipe_state_add_reg(&state,
1861 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1862 offset_db_fmt_cntl, NULL, 0);
1863 r600_context_pipe_state_set(rctx, &state);
1864 }
1865 }
1866
1867 void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader)
1868 {
1869 struct r600_context *rctx = (struct r600_context *)ctx;
1870 struct r600_pipe_state *rstate = &shader->rstate;
1871 struct r600_shader *rshader = &shader->shader;
1872 unsigned i, exports_ps, num_cout, spi_ps_in_control, db_shader_control;
1873 unsigned num_sgprs, num_user_sgprs;
1874 int pos_index = -1, face_index = -1;
1875 int ninterp = 0;
1876 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
1877 unsigned spi_baryc_cntl;
1878 uint64_t va;
1879
1880 if (si_pipe_shader_create(ctx, shader))
1881 return;
1882
1883 rstate->nregs = 0;
1884
1885 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
1886 for (i = 0; i < rshader->ninput; i++) {
1887 ninterp++;
1888 /* XXX: Flat shading hangs the GPU */
1889 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
1890 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
1891 rctx->rasterizer->flatshade))
1892 have_linear = TRUE;
1893 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
1894 have_linear = TRUE;
1895 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
1896 have_perspective = TRUE;
1897 if (rshader->input[i].centroid)
1898 have_centroid = TRUE;
1899 }
1900
1901 for (i = 0; i < rshader->noutput; i++) {
1902 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1903 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
1904 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1905 db_shader_control |= 0; // XXX OP_VAL or TEST_VAL?
1906 }
1907 if (rshader->uses_kill)
1908 db_shader_control |= S_02880C_KILL_ENABLE(1);
1909
1910 exports_ps = 0;
1911 num_cout = 0;
1912 for (i = 0; i < rshader->noutput; i++) {
1913 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
1914 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1915 exports_ps |= 1;
1916 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
1917 if (rshader->fs_write_all)
1918 num_cout = rshader->nr_cbufs;
1919 else
1920 num_cout++;
1921 }
1922 }
1923 if (!exports_ps) {
1924 /* always at least export 1 component per pixel */
1925 exports_ps = 2;
1926 }
1927
1928 spi_ps_in_control = S_0286D8_NUM_INTERP(ninterp);
1929
1930 spi_baryc_cntl = 0;
1931 if (have_perspective)
1932 spi_baryc_cntl |= have_centroid ?
1933 S_0286E0_PERSP_CENTROID_CNTL(1) : S_0286E0_PERSP_CENTER_CNTL(1);
1934 if (have_linear)
1935 spi_baryc_cntl |= have_centroid ?
1936 S_0286E0_LINEAR_CENTROID_CNTL(1) : S_0286E0_LINEAR_CENTER_CNTL(1);
1937
1938 r600_pipe_state_add_reg(rstate,
1939 R_0286E0_SPI_BARYC_CNTL,
1940 spi_baryc_cntl,
1941 NULL, 0);
1942
1943 r600_pipe_state_add_reg(rstate,
1944 R_0286CC_SPI_PS_INPUT_ENA,
1945 shader->spi_ps_input_ena,
1946 NULL, 0);
1947
1948 r600_pipe_state_add_reg(rstate,
1949 R_0286D0_SPI_PS_INPUT_ADDR,
1950 shader->spi_ps_input_ena,
1951 NULL, 0);
1952
1953 r600_pipe_state_add_reg(rstate,
1954 R_0286D8_SPI_PS_IN_CONTROL,
1955 spi_ps_in_control,
1956 NULL, 0);
1957
1958 /* XXX: Depends on Z buffer format? */
1959 r600_pipe_state_add_reg(rstate,
1960 R_028710_SPI_SHADER_Z_FORMAT,
1961 0,
1962 NULL, 0);
1963
1964 /* XXX: Depends on color buffer format? */
1965 r600_pipe_state_add_reg(rstate,
1966 R_028714_SPI_SHADER_COL_FORMAT,
1967 S_028714_COL0_EXPORT_FORMAT(V_028714_SPI_SHADER_32_ABGR),
1968 NULL, 0);
1969
1970 va = r600_resource_va(ctx->screen, (void *)shader->bo);
1971 r600_pipe_state_add_reg(rstate,
1972 R_00B020_SPI_SHADER_PGM_LO_PS,
1973 va >> 8,
1974 shader->bo, RADEON_USAGE_READ);
1975 r600_pipe_state_add_reg(rstate,
1976 R_00B024_SPI_SHADER_PGM_HI_PS,
1977 va >> 40,
1978 shader->bo, RADEON_USAGE_READ);
1979
1980 num_user_sgprs = 6;
1981 num_sgprs = shader->num_sgprs;
1982 if (num_user_sgprs > num_sgprs)
1983 num_sgprs = num_user_sgprs;
1984 /* Last 2 reserved SGPRs are used for VCC */
1985 num_sgprs += 2;
1986 assert(num_sgprs <= 104);
1987
1988 r600_pipe_state_add_reg(rstate,
1989 R_00B028_SPI_SHADER_PGM_RSRC1_PS,
1990 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
1991 S_00B028_SGPRS((num_sgprs - 1) / 8),
1992 NULL, 0);
1993 r600_pipe_state_add_reg(rstate,
1994 R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1995 S_00B02C_USER_SGPR(num_user_sgprs),
1996 NULL, 0);
1997
1998 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
1999 db_shader_control,
2000 NULL, 0);
2001
2002 shader->sprite_coord_enable = rctx->sprite_coord_enable;
2003 }
2004
2005 void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader)
2006 {
2007 struct r600_context *rctx = (struct r600_context *)ctx;
2008 struct r600_pipe_state *rstate = &shader->rstate;
2009 struct r600_shader *rshader = &shader->shader;
2010 unsigned num_sgprs, num_user_sgprs;
2011 unsigned nparams, i;
2012 uint64_t va;
2013
2014 if (si_pipe_shader_create(ctx, shader))
2015 return;
2016
2017 /* clear previous register */
2018 rstate->nregs = 0;
2019
2020 /* Certain attributes (position, psize, etc.) don't count as params.
2021 * VS is required to export at least one param and r600_shader_from_tgsi()
2022 * takes care of adding a dummy export.
2023 */
2024 for (nparams = 0, i = 0 ; i < rshader->noutput; i++) {
2025 if (rshader->output[i].name != TGSI_SEMANTIC_POSITION)
2026 nparams++;
2027 }
2028 if (nparams < 1)
2029 nparams = 1;
2030
2031 r600_pipe_state_add_reg(rstate,
2032 R_0286C4_SPI_VS_OUT_CONFIG,
2033 S_0286C4_VS_EXPORT_COUNT(nparams - 1),
2034 NULL, 0);
2035
2036 r600_pipe_state_add_reg(rstate,
2037 R_02870C_SPI_SHADER_POS_FORMAT,
2038 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
2039 S_02870C_POS1_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE) |
2040 S_02870C_POS2_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE) |
2041 S_02870C_POS3_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE),
2042 NULL, 0);
2043
2044 va = r600_resource_va(ctx->screen, (void *)shader->bo);
2045 r600_pipe_state_add_reg(rstate,
2046 R_00B120_SPI_SHADER_PGM_LO_VS,
2047 va >> 8,
2048 shader->bo, RADEON_USAGE_READ);
2049 r600_pipe_state_add_reg(rstate,
2050 R_00B124_SPI_SHADER_PGM_HI_VS,
2051 va >> 40,
2052 shader->bo, RADEON_USAGE_READ);
2053
2054 num_user_sgprs = 8;
2055 num_sgprs = shader->num_sgprs;
2056 if (num_user_sgprs > num_sgprs)
2057 num_sgprs = num_user_sgprs;
2058 /* Last 2 reserved SGPRs are used for VCC */
2059 num_sgprs += 2;
2060 assert(num_sgprs <= 104);
2061
2062 r600_pipe_state_add_reg(rstate,
2063 R_00B128_SPI_SHADER_PGM_RSRC1_VS,
2064 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
2065 S_00B128_SGPRS((num_sgprs - 1) / 8),
2066 NULL, 0);
2067 r600_pipe_state_add_reg(rstate,
2068 R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
2069 S_00B12C_USER_SGPR(num_user_sgprs),
2070 NULL, 0);
2071 }
2072
2073 void si_update_spi_map(struct r600_context *rctx)
2074 {
2075 struct r600_shader *ps = &rctx->ps_shader->shader;
2076 struct r600_shader *vs = &rctx->vs_shader->shader;
2077 struct r600_pipe_state *rstate = &rctx->spi;
2078 unsigned i, j, tmp;
2079
2080 rstate->nregs = 0;
2081
2082 for (i = 0; i < ps->ninput; i++) {
2083 tmp = 0;
2084
2085 #if 0
2086 /* XXX: Flat shading hangs the GPU */
2087 if (ps->input[i].name == TGSI_SEMANTIC_POSITION ||
2088 ps->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2089 (ps->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2090 rctx->rasterizer && rctx->rasterizer->flatshade)) {
2091 tmp |= S_028644_FLAT_SHADE(1);
2092 }
2093 #endif
2094
2095 if (ps->input[i].name == TGSI_SEMANTIC_GENERIC &&
2096 rctx->sprite_coord_enable & (1 << ps->input[i].sid)) {
2097 tmp |= S_028644_PT_SPRITE_TEX(1);
2098 }
2099
2100 for (j = 0; j < vs->noutput; j++) {
2101 if (ps->input[i].name == vs->output[j].name &&
2102 ps->input[i].sid == vs->output[j].sid) {
2103 tmp |= S_028644_OFFSET(vs->output[j].param_offset);
2104 break;
2105 }
2106 }
2107
2108 if (j == vs->noutput) {
2109 /* No corresponding output found, load defaults into input */
2110 tmp |= S_028644_OFFSET(0x20);
2111 }
2112
2113 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2114 tmp, NULL, 0);
2115 }
2116
2117 if (rstate->nregs > 0)
2118 r600_context_pipe_state_set(rctx, rstate);
2119 }
2120
2121 void *cayman_create_db_flush_dsa(struct r600_context *rctx)
2122 {
2123 struct pipe_depth_stencil_alpha_state dsa;
2124 struct r600_pipe_state *rstate;
2125
2126 memset(&dsa, 0, sizeof(dsa));
2127
2128 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2129 r600_pipe_state_add_reg(rstate,
2130 R_028000_DB_RENDER_CONTROL,
2131 S_028000_DEPTH_COPY(1) |
2132 S_028000_STENCIL_COPY(1) |
2133 S_028000_COPY_CENTROID(1),
2134 NULL, 0);
2135 return rstate;
2136 }