2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "../../winsys/radeon/drm/radeon_winsys.h"
30 #include "util/u_double_list.h"
31 #include "util/u_transfer.h"
33 #define R600_ERR(fmt, args...) \
34 fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
52 struct r600_tiling_info
{
53 unsigned num_channels
;
58 struct r600_resource
{
62 struct pb_buffer
*buf
;
63 struct radeon_winsys_cs_handle
*cs_buf
;
69 /* R600/R700 STATES */
70 #define R600_GROUP_MAX 16
71 #define R600_BLOCK_MAX_BO 32
72 #define R600_BLOCK_MAX_REG 128
74 /* each range covers 9 bits of dword space = 512 dwords = 2k bytes */
75 /* there is a block entry for each register so 512 blocks */
76 /* we have no registers to read/write below 0x8000 (0x2000 in dw space) */
77 /* we use some fake offsets at 0x40000 to do evergreen sampler borders so take 0x42000 as a max bound*/
78 #define RANGE_OFFSET_START 0x8000
80 #define NUM_RANGES (0x42000 - RANGE_OFFSET_START) / (4 << HASH_SHIFT) /* 128 << 9 = 64k */
82 #define CTX_RANGE_ID(offset) ((((offset - RANGE_OFFSET_START) >> 2) >> HASH_SHIFT) & 255)
83 #define CTX_BLOCK_ID(offset) (((offset - RANGE_OFFSET_START) >> 2) & ((1 << HASH_SHIFT) - 1))
85 struct r600_pipe_reg
{
87 struct r600_block
*block
;
88 struct r600_resource
*bo
;
89 enum radeon_bo_usage bo_usage
;
93 struct r600_pipe_state
{
96 struct r600_pipe_reg regs
[R600_BLOCK_MAX_REG
];
99 #define R600_BLOCK_STATUS_ENABLED (1 << 0)
100 #define R600_BLOCK_STATUS_DIRTY (1 << 1)
102 struct r600_block_reloc
{
103 struct r600_resource
*bo
;
104 enum radeon_bo_usage bo_usage
;
105 unsigned bo_pm4_index
;
109 struct list_head list
;
110 struct list_head enable_list
;
113 unsigned start_offset
;
114 unsigned pm4_ndwords
;
119 uint32_t pm4
[R600_BLOCK_MAX_REG
];
120 unsigned pm4_bo_index
[R600_BLOCK_MAX_REG
];
121 struct r600_block_reloc reloc
[R600_BLOCK_MAX_BO
];
125 struct r600_block
**blocks
;
132 struct pipe_query_data_so_statistics so
;
134 /* The kind of query */
136 /* Offset of the first result for current query */
137 unsigned results_start
;
138 /* Offset of the next free result after current query data */
139 unsigned results_end
;
140 /* Size of the result in memory for both begin_query and end_query,
141 * this can be one or two numbers, or it could even be a size of a structure. */
142 unsigned result_size
;
143 /* The buffer where query results are stored. It's used as a ring,
144 * data blocks for current query are stored sequentially from
145 * results_start to results_end, with wrapping on the buffer end */
146 struct r600_resource
*buffer
;
147 /* The number of dwords for begin_query or end_query. */
149 /* linked list of queries */
150 struct list_head list
;
153 struct r600_so_target
{
154 struct pipe_stream_output_target b
;
156 /* The buffer where BUFFER_FILLED_SIZE is stored. */
157 struct r600_resource
*filled_size
;
162 #define R600_CONTEXT_DRAW_PENDING (1 << 0)
163 #define R600_CONTEXT_DST_CACHES_DIRTY (1 << 1)
164 #define R600_CONTEXT_CHECK_EVENT_FLUSH (1 << 2)
167 uint32_t vgt_num_indices
;
168 uint32_t vgt_num_instances
;
169 uint32_t vgt_index_type
;
170 uint32_t vgt_draw_initiator
;
171 uint32_t indices_bo_offset
;
172 unsigned db_render_override
;
173 unsigned db_render_control
;
174 struct r600_resource
*indices
;
180 void r600_get_backend_mask(struct r600_context
*ctx
);
181 void r600_context_fini(struct r600_context
*ctx
);
182 void r600_context_pipe_state_set(struct r600_context
*ctx
, struct r600_pipe_state
*state
);
183 void r600_context_flush(struct r600_context
*ctx
, unsigned flags
);
184 void r600_context_draw(struct r600_context
*ctx
, const struct r600_draw
*draw
);
186 struct r600_query
*r600_context_query_create(struct r600_context
*ctx
, unsigned query_type
);
187 void r600_context_query_destroy(struct r600_context
*ctx
, struct r600_query
*query
);
188 boolean
r600_context_query_result(struct r600_context
*ctx
,
189 struct r600_query
*query
,
190 boolean wait
, void *vresult
);
191 void r600_query_begin(struct r600_context
*ctx
, struct r600_query
*query
);
192 void r600_query_end(struct r600_context
*ctx
, struct r600_query
*query
);
193 void r600_context_queries_suspend(struct r600_context
*ctx
);
194 void r600_context_queries_resume(struct r600_context
*ctx
);
195 void r600_query_predication(struct r600_context
*ctx
, struct r600_query
*query
, int operation
,
197 void r600_context_emit_fence(struct r600_context
*ctx
, struct r600_resource
*fence
,
198 unsigned offset
, unsigned value
);
199 void r600_inval_shader_cache(struct r600_context
*ctx
);
200 void r600_inval_texture_cache(struct r600_context
*ctx
);
201 void r600_inval_vertex_cache(struct r600_context
*ctx
);
202 void r600_flush_framebuffer(struct r600_context
*ctx
, bool flush_now
);
204 void r600_context_streamout_begin(struct r600_context
*ctx
);
205 void r600_context_streamout_end(struct r600_context
*ctx
);
206 void r600_context_draw_opaque_count(struct r600_context
*ctx
, struct r600_so_target
*t
);
207 void r600_need_cs_space(struct r600_context
*ctx
, unsigned num_dw
, boolean count_draw_in
);
208 void r600_context_block_emit_dirty(struct r600_context
*ctx
, struct r600_block
*block
);
209 void r600_context_block_resource_emit_dirty(struct r600_context
*ctx
, struct r600_block
*block
);
211 int si_context_init(struct r600_context
*ctx
);
212 void evergreen_context_draw(struct r600_context
*ctx
, const struct r600_draw
*draw
);
214 void _r600_pipe_state_add_reg(struct r600_context
*ctx
,
215 struct r600_pipe_state
*state
,
216 uint32_t offset
, uint32_t value
,
217 uint32_t range_id
, uint32_t block_id
,
218 struct r600_resource
*bo
,
219 enum radeon_bo_usage usage
);
221 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state
*state
,
222 uint32_t offset
, uint32_t value
,
223 struct r600_resource
*bo
,
224 enum radeon_bo_usage usage
);
226 #define r600_pipe_state_add_reg(state, offset, value, bo, usage) _r600_pipe_state_add_reg(rctx, state, offset, value, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset), bo, usage)
228 static inline void r600_pipe_state_mod_reg(struct r600_pipe_state
*state
,
231 state
->regs
[state
->nregs
].value
= value
;
235 static inline void r600_pipe_state_mod_reg_bo(struct r600_pipe_state
*state
,
236 uint32_t value
, struct r600_resource
*bo
,
237 enum radeon_bo_usage usage
)
239 state
->regs
[state
->nregs
].value
= value
;
240 state
->regs
[state
->nregs
].bo
= bo
;
241 state
->regs
[state
->nregs
].bo_usage
= usage
;