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Merge branch 'gallium-userbuf'
[mesa.git] / src / gallium / drivers / radeonsi / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "util/u_blitter.h"
28 #include "util/u_memory.h"
29 #include "util/u_format.h"
30 #include "pipebuffer/pb_buffer.h"
31 #include "pipe/p_shader_tokens.h"
32 #include "tgsi/tgsi_parse.h"
33 #include "r600_hw_context_priv.h"
34 #include "radeonsi_pipe.h"
35 #include "sid.h"
36
37 static void r600_emit_surface_sync(struct r600_context *rctx, struct r600_atom *atom)
38 {
39 struct radeon_winsys_cs *cs = rctx->cs;
40 struct r600_atom_surface_sync *a = (struct r600_atom_surface_sync*)atom;
41
42 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
43 cs->buf[cs->cdw++] = a->flush_flags; /* CP_COHER_CNTL */
44 cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */
45 cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */
46 cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */
47
48 a->flush_flags = 0;
49 }
50
51 static void r600_emit_r6xx_flush_and_inv(struct r600_context *rctx, struct r600_atom *atom)
52 {
53 struct radeon_winsys_cs *cs = rctx->cs;
54 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
55 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
56 }
57
58 static void r600_init_atom(struct r600_atom *atom,
59 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
60 unsigned num_dw,
61 enum r600_atom_flags flags)
62 {
63 atom->emit = emit;
64 atom->num_dw = num_dw;
65 atom->flags = flags;
66 }
67
68 void r600_init_common_atoms(struct r600_context *rctx)
69 {
70 r600_init_atom(&rctx->atom_surface_sync.atom, r600_emit_surface_sync, 5, EMIT_EARLY);
71 r600_init_atom(&rctx->atom_r6xx_flush_and_inv, r600_emit_r6xx_flush_and_inv, 2, EMIT_EARLY);
72 }
73
74 unsigned r600_get_cb_flush_flags(struct r600_context *rctx)
75 {
76 unsigned flags = 0;
77
78 if (rctx->framebuffer.nr_cbufs) {
79 flags |= S_0085F0_CB_ACTION_ENA(1) |
80 (((1 << rctx->framebuffer.nr_cbufs) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT);
81 }
82
83 return flags;
84 }
85
86 void r600_texture_barrier(struct pipe_context *ctx)
87 {
88 struct r600_context *rctx = (struct r600_context *)ctx;
89
90 rctx->atom_surface_sync.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx);
91 r600_atom_dirty(rctx, &rctx->atom_surface_sync.atom);
92 }
93
94 static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
95 {
96 static const int prim_conv[] = {
97 V_008958_DI_PT_POINTLIST,
98 V_008958_DI_PT_LINELIST,
99 V_008958_DI_PT_LINELOOP,
100 V_008958_DI_PT_LINESTRIP,
101 V_008958_DI_PT_TRILIST,
102 V_008958_DI_PT_TRISTRIP,
103 V_008958_DI_PT_TRIFAN,
104 V_008958_DI_PT_QUADLIST,
105 V_008958_DI_PT_QUADSTRIP,
106 V_008958_DI_PT_POLYGON,
107 -1,
108 -1,
109 -1,
110 -1
111 };
112
113 *prim = prim_conv[pprim];
114 if (*prim == -1) {
115 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
116 return false;
117 }
118 return true;
119 }
120
121 /* common state between evergreen and r600 */
122 void r600_bind_blend_state(struct pipe_context *ctx, void *state)
123 {
124 struct r600_context *rctx = (struct r600_context *)ctx;
125 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
126 struct r600_pipe_state *rstate;
127
128 if (state == NULL)
129 return;
130 rstate = &blend->rstate;
131 rctx->states[rstate->id] = rstate;
132 rctx->cb_target_mask = blend->cb_target_mask;
133 rctx->cb_color_control = blend->cb_color_control;
134
135 r600_context_pipe_state_set(rctx, rstate);
136 }
137
138 static void r600_set_stencil_ref(struct pipe_context *ctx,
139 const struct r600_stencil_ref *state)
140 {
141 struct r600_context *rctx = (struct r600_context *)ctx;
142 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
143
144 if (rstate == NULL)
145 return;
146
147 rstate->id = R600_PIPE_STATE_STENCIL_REF;
148 r600_pipe_state_add_reg(rstate,
149 R_028430_DB_STENCILREFMASK,
150 S_028430_STENCILTESTVAL(state->ref_value[0]) |
151 S_028430_STENCILMASK(state->valuemask[0]) |
152 S_028430_STENCILWRITEMASK(state->writemask[0]),
153 NULL, 0);
154 r600_pipe_state_add_reg(rstate,
155 R_028434_DB_STENCILREFMASK_BF,
156 S_028434_STENCILTESTVAL_BF(state->ref_value[1]) |
157 S_028434_STENCILMASK_BF(state->valuemask[1]) |
158 S_028434_STENCILWRITEMASK_BF(state->writemask[1]),
159 NULL, 0);
160
161 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
162 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
163 r600_context_pipe_state_set(rctx, rstate);
164 }
165
166 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
167 const struct pipe_stencil_ref *state)
168 {
169 struct r600_context *rctx = (struct r600_context *)ctx;
170 struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
171 struct r600_stencil_ref ref;
172
173 rctx->stencil_ref = *state;
174
175 if (!dsa)
176 return;
177
178 ref.ref_value[0] = state->ref_value[0];
179 ref.ref_value[1] = state->ref_value[1];
180 ref.valuemask[0] = dsa->valuemask[0];
181 ref.valuemask[1] = dsa->valuemask[1];
182 ref.writemask[0] = dsa->writemask[0];
183 ref.writemask[1] = dsa->writemask[1];
184
185 r600_set_stencil_ref(ctx, &ref);
186 }
187
188 void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
189 {
190 struct r600_context *rctx = (struct r600_context *)ctx;
191 struct r600_pipe_dsa *dsa = state;
192 struct r600_pipe_state *rstate;
193 struct r600_stencil_ref ref;
194
195 if (state == NULL)
196 return;
197 rstate = &dsa->rstate;
198 rctx->states[rstate->id] = rstate;
199 rctx->alpha_ref = dsa->alpha_ref;
200 rctx->alpha_ref_dirty = true;
201 r600_context_pipe_state_set(rctx, rstate);
202
203 ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
204 ref.ref_value[1] = rctx->stencil_ref.ref_value[1];
205 ref.valuemask[0] = dsa->valuemask[0];
206 ref.valuemask[1] = dsa->valuemask[1];
207 ref.writemask[0] = dsa->writemask[0];
208 ref.writemask[1] = dsa->writemask[1];
209
210 r600_set_stencil_ref(ctx, &ref);
211 }
212
213 void r600_bind_rs_state(struct pipe_context *ctx, void *state)
214 {
215 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
216 struct r600_context *rctx = (struct r600_context *)ctx;
217
218 if (state == NULL)
219 return;
220
221 rctx->sprite_coord_enable = rs->sprite_coord_enable;
222 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
223 rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
224 rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
225 rctx->pa_cl_vs_out_cntl = rs->pa_cl_vs_out_cntl;
226
227 rctx->rasterizer = rs;
228
229 rctx->states[rs->rstate.id] = &rs->rstate;
230 r600_context_pipe_state_set(rctx, &rs->rstate);
231
232 if (rctx->chip_class >= CAYMAN) {
233 cayman_polygon_offset_update(rctx);
234 }
235 }
236
237 void r600_delete_rs_state(struct pipe_context *ctx, void *state)
238 {
239 struct r600_context *rctx = (struct r600_context *)ctx;
240 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
241
242 if (rctx->rasterizer == rs) {
243 rctx->rasterizer = NULL;
244 }
245 if (rctx->states[rs->rstate.id] == &rs->rstate) {
246 rctx->states[rs->rstate.id] = NULL;
247 }
248 free(rs);
249 }
250
251 void r600_sampler_view_destroy(struct pipe_context *ctx,
252 struct pipe_sampler_view *state)
253 {
254 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
255
256 pipe_resource_reference(&state->texture, NULL);
257 FREE(resource);
258 }
259
260 void r600_delete_state(struct pipe_context *ctx, void *state)
261 {
262 struct r600_context *rctx = (struct r600_context *)ctx;
263 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
264
265 if (rctx->states[rstate->id] == rstate) {
266 rctx->states[rstate->id] = NULL;
267 }
268 for (int i = 0; i < rstate->nregs; i++) {
269 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
270 }
271 free(rstate);
272 }
273
274 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
275 {
276 struct r600_context *rctx = (struct r600_context *)ctx;
277 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
278
279 rctx->vertex_elements = v;
280 if (v) {
281 r600_inval_shader_cache(rctx);
282
283 rctx->states[v->rstate.id] = &v->rstate;
284 r600_context_pipe_state_set(rctx, &v->rstate);
285 }
286 }
287
288 void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
289 {
290 struct r600_context *rctx = (struct r600_context *)ctx;
291 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
292
293 if (rctx->states[v->rstate.id] == &v->rstate) {
294 rctx->states[v->rstate.id] = NULL;
295 }
296 if (rctx->vertex_elements == state)
297 rctx->vertex_elements = NULL;
298 FREE(state);
299 }
300
301
302 void r600_set_index_buffer(struct pipe_context *ctx,
303 const struct pipe_index_buffer *ib)
304 {
305 struct r600_context *rctx = (struct r600_context *)ctx;
306
307 if (ib) {
308 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
309 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
310 } else {
311 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
312 }
313 }
314
315 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
316 const struct pipe_vertex_buffer *buffers)
317 {
318 struct r600_context *rctx = (struct r600_context *)ctx;
319
320 util_copy_vertex_buffers(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, count);
321 }
322
323 void *si_create_vertex_elements(struct pipe_context *ctx,
324 unsigned count,
325 const struct pipe_vertex_element *elements)
326 {
327 struct r600_context *rctx = (struct r600_context *)ctx;
328 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
329
330 assert(count < 32);
331 if (!v)
332 return NULL;
333
334 v->count = count;
335 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
336
337 return v;
338 }
339
340 void *si_create_shader_state(struct pipe_context *ctx,
341 const struct pipe_shader_state *state)
342 {
343 struct si_pipe_shader *shader = CALLOC_STRUCT(si_pipe_shader);
344
345 shader->tokens = tgsi_dup_tokens(state->tokens);
346 shader->so = state->stream_output;
347
348 return shader;
349 }
350
351 void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
352 {
353 struct r600_context *rctx = (struct r600_context *)ctx;
354
355 if (rctx->ps_shader != state)
356 rctx->shader_dirty = true;
357
358 /* TODO delete old shader */
359 rctx->ps_shader = (struct si_pipe_shader *)state;
360 if (state) {
361 r600_inval_shader_cache(rctx);
362 r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
363 }
364 }
365
366 void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
367 {
368 struct r600_context *rctx = (struct r600_context *)ctx;
369
370 if (rctx->vs_shader != state)
371 rctx->shader_dirty = true;
372
373 /* TODO delete old shader */
374 rctx->vs_shader = (struct si_pipe_shader *)state;
375 if (state) {
376 r600_inval_shader_cache(rctx);
377 r600_context_pipe_state_set(rctx, &rctx->vs_shader->rstate);
378 }
379 }
380
381 void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
382 {
383 struct r600_context *rctx = (struct r600_context *)ctx;
384 struct si_pipe_shader *shader = (struct si_pipe_shader *)state;
385
386 if (rctx->ps_shader == shader) {
387 rctx->ps_shader = NULL;
388 }
389
390 free(shader->tokens);
391 si_pipe_shader_destroy(ctx, shader);
392 free(shader);
393 }
394
395 void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
396 {
397 struct r600_context *rctx = (struct r600_context *)ctx;
398 struct si_pipe_shader *shader = (struct si_pipe_shader *)state;
399
400 if (rctx->vs_shader == shader) {
401 rctx->vs_shader = NULL;
402 }
403
404 free(shader->tokens);
405 si_pipe_shader_destroy(ctx, shader);
406 free(shader);
407 }
408
409 static void r600_update_alpha_ref(struct r600_context *rctx)
410 {
411 #if 0
412 unsigned alpha_ref;
413 struct r600_pipe_state rstate;
414
415 alpha_ref = rctx->alpha_ref;
416 rstate.nregs = 0;
417 if (rctx->export_16bpc)
418 alpha_ref &= ~0x1FFF;
419 r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref, NULL, 0);
420
421 r600_context_pipe_state_set(rctx, &rstate);
422 rctx->alpha_ref_dirty = false;
423 #endif
424 }
425
426 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
427 struct pipe_constant_buffer *cb)
428 {
429 struct r600_context *rctx = (struct r600_context *)ctx;
430 struct r600_resource *rbuffer = cb ? r600_resource(cb->buffer) : NULL;
431 struct r600_pipe_state *rstate;
432 uint64_t va_offset;
433 uint32_t offset;
434
435 /* Note that the state tracker can unbind constant buffers by
436 * passing NULL here.
437 */
438 if (cb == NULL) {
439 return;
440 }
441
442 r600_inval_shader_cache(rctx);
443
444 if (cb->user_buffer)
445 r600_upload_const_buffer(rctx, &rbuffer, cb->user_buffer, cb->buffer_size, &offset);
446 else
447 offset = 0;
448 va_offset = r600_resource_va(ctx->screen, (void*)rbuffer);
449 va_offset += offset;
450 //va_offset >>= 8;
451
452 switch (shader) {
453 case PIPE_SHADER_VERTEX:
454 rstate = &rctx->vs_const_buffer;
455 rstate->nregs = 0;
456 r600_pipe_state_add_reg(rstate,
457 R_00B130_SPI_SHADER_USER_DATA_VS_0,
458 va_offset, rbuffer, RADEON_USAGE_READ);
459 r600_pipe_state_add_reg(rstate,
460 R_00B134_SPI_SHADER_USER_DATA_VS_1,
461 va_offset >> 32, NULL, 0);
462 break;
463 case PIPE_SHADER_FRAGMENT:
464 rstate = &rctx->ps_const_buffer;
465 rstate->nregs = 0;
466 r600_pipe_state_add_reg(rstate,
467 R_00B030_SPI_SHADER_USER_DATA_PS_0,
468 va_offset, rbuffer, RADEON_USAGE_READ);
469 r600_pipe_state_add_reg(rstate,
470 R_00B034_SPI_SHADER_USER_DATA_PS_1,
471 va_offset >> 32, NULL, 0);
472 break;
473 default:
474 R600_ERR("unsupported %d\n", shader);
475 return;
476 }
477
478 r600_context_pipe_state_set(rctx, rstate);
479
480 if (cb->buffer != &rbuffer->b.b)
481 pipe_resource_reference((struct pipe_resource**)&rbuffer, NULL);
482 }
483
484 struct pipe_stream_output_target *
485 r600_create_so_target(struct pipe_context *ctx,
486 struct pipe_resource *buffer,
487 unsigned buffer_offset,
488 unsigned buffer_size)
489 {
490 struct r600_context *rctx = (struct r600_context *)ctx;
491 struct r600_so_target *t;
492 void *ptr;
493
494 t = CALLOC_STRUCT(r600_so_target);
495 if (!t) {
496 return NULL;
497 }
498
499 t->b.reference.count = 1;
500 t->b.context = ctx;
501 pipe_resource_reference(&t->b.buffer, buffer);
502 t->b.buffer_offset = buffer_offset;
503 t->b.buffer_size = buffer_size;
504
505 t->filled_size = (struct r600_resource*)
506 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
507 ptr = rctx->ws->buffer_map(t->filled_size->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
508 memset(ptr, 0, t->filled_size->buf->size);
509 rctx->ws->buffer_unmap(t->filled_size->cs_buf);
510
511 return &t->b;
512 }
513
514 void r600_so_target_destroy(struct pipe_context *ctx,
515 struct pipe_stream_output_target *target)
516 {
517 struct r600_so_target *t = (struct r600_so_target*)target;
518 pipe_resource_reference(&t->b.buffer, NULL);
519 pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
520 FREE(t);
521 }
522
523 void r600_set_so_targets(struct pipe_context *ctx,
524 unsigned num_targets,
525 struct pipe_stream_output_target **targets,
526 unsigned append_bitmask)
527 {
528 struct r600_context *rctx = (struct r600_context *)ctx;
529 unsigned i;
530
531 /* Stop streamout. */
532 if (rctx->num_so_targets) {
533 r600_context_streamout_end(rctx);
534 }
535
536 /* Set the new targets. */
537 for (i = 0; i < num_targets; i++) {
538 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
539 }
540 for (; i < rctx->num_so_targets; i++) {
541 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
542 }
543
544 rctx->num_so_targets = num_targets;
545 rctx->streamout_start = num_targets != 0;
546 rctx->streamout_append_bitmask = append_bitmask;
547 }
548
549 static void r600_vertex_buffer_update(struct r600_context *rctx)
550 {
551 struct pipe_context *ctx = &rctx->context;
552 struct r600_pipe_state *rstate = &rctx->vs_user_data;
553 struct r600_resource *rbuffer, *t_list_buffer;
554 struct pipe_vertex_buffer *vertex_buffer;
555 unsigned i, count, offset;
556 uint32_t *ptr;
557 uint64_t va;
558
559 r600_inval_vertex_cache(rctx);
560
561 if (rctx->vertex_elements->vbuffer_need_offset) {
562 /* one resource per vertex elements */
563 count = rctx->vertex_elements->count;
564 } else {
565 /* bind vertex buffer once */
566 count = rctx->nr_vertex_buffers;
567 }
568 assert(count <= 256 / 4);
569
570 t_list_buffer = (struct r600_resource*)
571 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM,
572 PIPE_USAGE_IMMUTABLE, 4 * 4 * count);
573 if (t_list_buffer == NULL)
574 return;
575
576 ptr = (uint32_t*)rctx->ws->buffer_map(t_list_buffer->cs_buf,
577 rctx->cs,
578 PIPE_TRANSFER_WRITE);
579
580 for (i = 0 ; i < count; i++, ptr += 4) {
581 struct pipe_vertex_element *velem = &rctx->vertex_elements->elements[i];
582 const struct util_format_description *desc;
583 unsigned data_format, num_format;
584 int first_non_void;
585
586 if (rctx->vertex_elements->vbuffer_need_offset) {
587 /* one resource per vertex elements */
588 unsigned vbuffer_index;
589 vbuffer_index = rctx->vertex_elements->elements[i].vertex_buffer_index;
590 vertex_buffer = &rctx->vertex_buffer[vbuffer_index];
591 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
592 offset = rctx->vertex_elements->vbuffer_offset[i];
593 } else {
594 /* bind vertex buffer once */
595 vertex_buffer = &rctx->vertex_buffer[i];
596 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
597 offset = 0;
598 }
599 if (vertex_buffer == NULL || rbuffer == NULL)
600 continue;
601 offset += vertex_buffer->buffer_offset;
602
603 va = r600_resource_va(ctx->screen, (void*)rbuffer);
604 va += offset;
605
606 desc = util_format_description(velem->src_format);
607 first_non_void = util_format_get_first_non_void_channel(velem->src_format);
608 data_format = si_translate_vertexformat(ctx->screen,
609 velem->src_format,
610 desc, first_non_void);
611
612 switch (desc->channel[first_non_void].type) {
613 case UTIL_FORMAT_TYPE_FIXED:
614 num_format = V_008F0C_BUF_NUM_FORMAT_USCALED; /* XXX */
615 break;
616 case UTIL_FORMAT_TYPE_SIGNED:
617 num_format = V_008F0C_BUF_NUM_FORMAT_SNORM;
618 break;
619 case UTIL_FORMAT_TYPE_UNSIGNED:
620 num_format = V_008F0C_BUF_NUM_FORMAT_UNORM;
621 break;
622 case UTIL_FORMAT_TYPE_FLOAT:
623 default:
624 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
625 }
626
627 /* Fill in T# buffer resource description */
628 ptr[0] = va & 0xFFFFFFFF;
629 ptr[1] = (S_008F04_BASE_ADDRESS_HI(va >> 32) |
630 S_008F04_STRIDE(vertex_buffer->stride));
631 if (vertex_buffer->stride > 0)
632 ptr[2] = ((vertex_buffer->buffer->width0 - offset) /
633 vertex_buffer->stride);
634 else
635 ptr[2] = vertex_buffer->buffer->width0 - offset;
636 ptr[3] = (S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
637 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
638 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
639 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
640 S_008F0C_NUM_FORMAT(num_format) |
641 S_008F0C_DATA_FORMAT(data_format));
642
643 r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ);
644 }
645
646 rstate->nregs = 0;
647
648 va = r600_resource_va(ctx->screen, (void*)t_list_buffer);
649 r600_pipe_state_add_reg(rstate,
650 R_00B148_SPI_SHADER_USER_DATA_VS_6,
651 va, t_list_buffer, RADEON_USAGE_READ);
652 r600_pipe_state_add_reg(rstate,
653 R_00B14C_SPI_SHADER_USER_DATA_VS_7,
654 va >> 32,
655 NULL, 0);
656
657 r600_context_pipe_state_set(rctx, rstate);
658 }
659
660 static void si_update_derived_state(struct r600_context *rctx)
661 {
662 struct pipe_context * ctx = (struct pipe_context*)rctx;
663
664 if (!rctx->blitter->running) {
665 if (rctx->have_depth_fb || rctx->have_depth_texture)
666 r600_flush_depth_textures(rctx);
667 }
668
669 if (rctx->shader_dirty) {
670 si_pipe_shader_destroy(&rctx->context, rctx->vs_shader);
671 }
672
673 if (rctx->shader_dirty ||
674 (rctx->ps_shader->shader.fs_write_all &&
675 (rctx->ps_shader->shader.nr_cbufs != rctx->nr_cbufs)) ||
676 (rctx->sprite_coord_enable &&
677 (rctx->ps_shader->sprite_coord_enable != rctx->sprite_coord_enable))) {
678 si_pipe_shader_destroy(&rctx->context, rctx->ps_shader);
679 }
680
681 if (rctx->alpha_ref_dirty) {
682 r600_update_alpha_ref(rctx);
683 }
684
685 if (!rctx->vs_shader->bo) {
686 si_pipe_shader_vs(ctx, rctx->vs_shader);
687
688 r600_context_pipe_state_set(rctx, &rctx->vs_shader->rstate);
689 }
690
691 if (!rctx->ps_shader->bo) {
692 si_pipe_shader_ps(ctx, rctx->ps_shader);
693
694 r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
695 }
696
697 if (rctx->shader_dirty) {
698 si_update_spi_map(rctx);
699 rctx->shader_dirty = false;
700 }
701 }
702
703 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
704 {
705 struct r600_context *rctx = (struct r600_context *)ctx;
706 struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
707 struct pipe_draw_info info = *dinfo;
708 struct r600_draw rdraw = {};
709 struct pipe_index_buffer ib = {};
710 unsigned prim, mask, ls_mask = 0;
711 struct r600_block *dirty_block = NULL, *next_block = NULL;
712 struct r600_atom *state = NULL, *next_state = NULL;
713 int i;
714
715 if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
716 (info.indexed && !rctx->index_buffer.buffer) ||
717 !r600_conv_pipe_prim(info.mode, &prim)) {
718 return;
719 }
720
721 if (!rctx->ps_shader || !rctx->vs_shader)
722 return;
723
724 si_update_derived_state(rctx);
725
726 r600_vertex_buffer_update(rctx);
727
728 rdraw.vgt_num_indices = info.count;
729 rdraw.vgt_num_instances = info.instance_count;
730
731 if (info.indexed) {
732 /* Initialize the index buffer struct. */
733 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
734 ib.index_size = rctx->index_buffer.index_size;
735 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
736
737 /* Translate or upload, if needed. */
738 r600_translate_index_buffer(rctx, &ib, info.count);
739
740 if (ib.user_buffer) {
741 r600_upload_index_buffer(rctx, &ib, info.count);
742 }
743
744 /* Initialize the r600_draw struct with index buffer info. */
745 if (ib.index_size == 4) {
746 rdraw.vgt_index_type = V_028A7C_VGT_INDEX_32 |
747 (R600_BIG_ENDIAN ? V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
748 } else {
749 rdraw.vgt_index_type = V_028A7C_VGT_INDEX_16 |
750 (R600_BIG_ENDIAN ? V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
751 }
752 rdraw.indices = (struct r600_resource*)ib.buffer;
753 rdraw.indices_bo_offset = ib.offset;
754 rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_DMA;
755 } else {
756 info.index_bias = info.start;
757 rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
758 if (info.count_from_stream_output) {
759 rdraw.vgt_draw_initiator |= S_0287F0_USE_OPAQUE(1);
760
761 r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info.count_from_stream_output);
762 }
763 }
764
765 rctx->vs_shader_so_strides = rctx->vs_shader->so_strides;
766
767 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
768
769 if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
770 rctx->vgt.id = R600_PIPE_STATE_VGT;
771 rctx->vgt.nregs = 0;
772 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, NULL, 0);
773 r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, NULL, 0);
774 r600_pipe_state_add_reg(&rctx->vgt, R_028400_VGT_MAX_VTX_INDX, ~0, NULL, 0);
775 r600_pipe_state_add_reg(&rctx->vgt, R_028404_VGT_MIN_VTX_INDX, 0, NULL, 0);
776 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias, NULL, 0);
777 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index, NULL, 0);
778 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart, NULL, 0);
779 #if 0
780 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, NULL, 0);
781 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance, NULL, 0);
782 #endif
783 r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0, NULL, 0);
784 r600_pipe_state_add_reg(&rctx->vgt, R_028814_PA_SU_SC_MODE_CNTL, 0, NULL, 0);
785 r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0, NULL, 0);
786 r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0x0, NULL, 0);
787 }
788
789 rctx->vgt.nregs = 0;
790 r600_pipe_state_mod_reg(&rctx->vgt, prim);
791 r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_target_mask & mask);
792 r600_pipe_state_mod_reg(&rctx->vgt, ~0);
793 r600_pipe_state_mod_reg(&rctx->vgt, 0);
794 r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
795 r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
796 r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
797 #if 0
798 r600_pipe_state_mod_reg(&rctx->vgt, 0);
799 r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
800 #endif
801
802 if (prim == V_008958_DI_PT_LINELIST)
803 ls_mask = 1;
804 else if (prim == V_008958_DI_PT_LINESTRIP)
805 ls_mask = 2;
806 r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
807
808 if (info.mode == PIPE_PRIM_QUADS || info.mode == PIPE_PRIM_QUAD_STRIP || info.mode == PIPE_PRIM_POLYGON) {
809 r600_pipe_state_mod_reg(&rctx->vgt, S_028814_PROVOKING_VTX_LAST(1) | rctx->pa_su_sc_mode_cntl);
810 } else {
811 r600_pipe_state_mod_reg(&rctx->vgt, rctx->pa_su_sc_mode_cntl);
812 }
813 r600_pipe_state_mod_reg(&rctx->vgt,
814 rctx->pa_cl_vs_out_cntl /*|
815 (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->shader.clip_dist_write)*/);
816 r600_pipe_state_mod_reg(&rctx->vgt,
817 rctx->pa_cl_clip_cntl /*|
818 (rctx->vs_shader->shader.clip_dist_write ||
819 rctx->vs_shader->shader.vs_prohibit_ucps ?
820 0 : rctx->rasterizer->clip_plane_enable & 0x3F)*/);
821
822 r600_context_pipe_state_set(rctx, &rctx->vgt);
823
824 rdraw.db_render_override = dsa->db_render_override;
825 rdraw.db_render_control = dsa->db_render_control;
826
827 /* Emit states. */
828 r600_need_cs_space(rctx, 0, TRUE);
829
830 LIST_FOR_EACH_ENTRY_SAFE(state, next_state, &rctx->dirty_states, head) {
831 r600_emit_atom(rctx, state);
832 }
833 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
834 r600_context_block_emit_dirty(rctx, dirty_block);
835 }
836 rctx->pm4_dirty_cdwords = 0;
837
838 /* Enable stream out if needed. */
839 if (rctx->streamout_start) {
840 r600_context_streamout_begin(rctx);
841 rctx->streamout_start = FALSE;
842 }
843
844 for (i = 0; i < NUM_TEX_UNITS; i++) {
845 if (rctx->ps_samplers.views[i])
846 r600_context_bo_reloc(rctx,
847 (struct r600_resource*)rctx->ps_samplers.views[i]->base.texture,
848 RADEON_USAGE_READ);
849 }
850
851 if (rctx->chip_class >= CAYMAN) {
852 evergreen_context_draw(rctx, &rdraw);
853 }
854
855 rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING;
856
857 if (rctx->framebuffer.zsbuf)
858 {
859 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture;
860 ((struct r600_resource_texture *)tex)->dirty_db = TRUE;
861 }
862
863 pipe_resource_reference(&ib.buffer, NULL);
864 }
865
866 void _r600_pipe_state_add_reg(struct r600_context *ctx,
867 struct r600_pipe_state *state,
868 uint32_t offset, uint32_t value,
869 uint32_t range_id, uint32_t block_id,
870 struct r600_resource *bo,
871 enum radeon_bo_usage usage)
872 {
873 struct r600_range *range;
874 struct r600_block *block;
875
876 if (bo) assert(usage);
877
878 range = &ctx->range[range_id];
879 block = range->blocks[block_id];
880 state->regs[state->nregs].block = block;
881 state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
882
883 state->regs[state->nregs].value = value;
884 state->regs[state->nregs].bo = bo;
885 state->regs[state->nregs].bo_usage = usage;
886
887 state->nregs++;
888 assert(state->nregs < R600_BLOCK_MAX_REG);
889 }
890
891 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
892 uint32_t offset, uint32_t value,
893 struct r600_resource *bo,
894 enum radeon_bo_usage usage)
895 {
896 if (bo) assert(usage);
897
898 state->regs[state->nregs].id = offset;
899 state->regs[state->nregs].block = NULL;
900 state->regs[state->nregs].value = value;
901 state->regs[state->nregs].bo = bo;
902 state->regs[state->nregs].bo_usage = usage;
903
904 state->nregs++;
905 assert(state->nregs < R600_BLOCK_MAX_REG);
906 }