src/gallium/drivers/radeonsi/r600_state_common.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *           2010 Jerome Glisse
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie <airlied@redhat.com>
  25  *          Jerome Glisse <jglisse@redhat.com>
  26  */
  27 #include "util/u_blitter.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_format.h"
  30 #include "pipebuffer/pb_buffer.h"
  31 #include "pipe/p_shader_tokens.h"
  32 #include "tgsi/tgsi_parse.h"
  33 #include "r600_hw_context_priv.h"
  34 #include "radeonsi_pipe.h"
  35 #include "sid.h"
  36
  37 static void r600_emit_surface_sync(struct r600_context *rctx, struct r600_atom *atom)
  38 {
  39         struct radeon_winsys_cs *cs = rctx->cs;
  40         struct r600_atom_surface_sync *a = (struct r600_atom_surface_sync*)atom;
  41
  42         cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
  43         cs->buf[cs->cdw++] = a->flush_flags;  /* CP_COHER_CNTL */
  44         cs->buf[cs->cdw++] = 0xffffffff;      /* CP_COHER_SIZE */
  45         cs->buf[cs->cdw++] = 0;               /* CP_COHER_BASE */
  46         cs->buf[cs->cdw++] = 0x0000000A;      /* POLL_INTERVAL */
  47
  48         a->flush_flags = 0;
  49 }
  50
  51 static void r600_emit_r6xx_flush_and_inv(struct r600_context *rctx, struct r600_atom *atom)
  52 {
  53         struct radeon_winsys_cs *cs = rctx->cs;
  54         cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
  55         cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
  56 }
  57
  58 static void r600_init_atom(struct r600_atom *atom,
  59                            void (*emit)(struct r600_context *ctx, struct r600_atom *state),
  60                            unsigned num_dw,
  61                            enum r600_atom_flags flags)
  62 {
  63         atom->emit = emit;
  64         atom->num_dw = num_dw;
  65         atom->flags = flags;
  66 }
  67
  68 void r600_init_common_atoms(struct r600_context *rctx)
  69 {
  70         r600_init_atom(&rctx->atom_surface_sync.atom,   r600_emit_surface_sync,         5, EMIT_EARLY);
  71         r600_init_atom(&rctx->atom_r6xx_flush_and_inv,  r600_emit_r6xx_flush_and_inv,   2, EMIT_EARLY);
  72 }
  73
  74 unsigned r600_get_cb_flush_flags(struct r600_context *rctx)
  75 {
  76         unsigned flags = 0;
  77
  78         if (rctx->framebuffer.nr_cbufs) {
  79                 flags |= S_0085F0_CB_ACTION_ENA(1) |
  80                          (((1 << rctx->framebuffer.nr_cbufs) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT);
  81         }
  82
  83         return flags;
  84 }
  85
  86 void r600_texture_barrier(struct pipe_context *ctx)
  87 {
  88         struct r600_context *rctx = (struct r600_context *)ctx;
  89
  90         rctx->atom_surface_sync.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx);
  91         r600_atom_dirty(rctx, &rctx->atom_surface_sync.atom);
  92 }
  93
  94 static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
  95 {
  96         static const int prim_conv[] = {
  97                 V_008958_DI_PT_POINTLIST,
  98                 V_008958_DI_PT_LINELIST,
  99                 V_008958_DI_PT_LINELOOP,
 100                 V_008958_DI_PT_LINESTRIP,
 101                 V_008958_DI_PT_TRILIST,
 102                 V_008958_DI_PT_TRISTRIP,
 103                 V_008958_DI_PT_TRIFAN,
 104                 V_008958_DI_PT_QUADLIST,
 105                 V_008958_DI_PT_QUADSTRIP,
 106                 V_008958_DI_PT_POLYGON,
 107                 -1,
 108                 -1,
 109                 -1,
 110                 -1
 111         };
 112
 113         *prim = prim_conv[pprim];
 114         if (*prim == -1) {
 115                 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
 116                 return false;
 117         }
 118         return true;
 119 }
 120
 121 /* common state between evergreen and r600 */
 122 void r600_bind_blend_state(struct pipe_context *ctx, void *state)
 123 {
 124         struct r600_context *rctx = (struct r600_context *)ctx;
 125         struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
 126         struct r600_pipe_state *rstate;
 127
 128         if (state == NULL)
 129                 return;
 130         rstate = &blend->rstate;
 131         rctx->states[rstate->id] = rstate;
 132         rctx->cb_target_mask = blend->cb_target_mask;
 133         rctx->cb_color_control = blend->cb_color_control;
 134
 135         r600_context_pipe_state_set(rctx, rstate);
 136 }
 137
 138 static void r600_set_stencil_ref(struct pipe_context *ctx,
 139                                  const struct r600_stencil_ref *state)
 140 {
 141         struct r600_context *rctx = (struct r600_context *)ctx;
 142         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 143
 144         if (rstate == NULL)
 145                 return;
 146
 147         rstate->id = R600_PIPE_STATE_STENCIL_REF;
 148         r600_pipe_state_add_reg(rstate,
 149                                 R_028430_DB_STENCILREFMASK,
 150                                 S_028430_STENCILTESTVAL(state->ref_value[0]) |
 151                                 S_028430_STENCILMASK(state->valuemask[0]) |
 152                                 S_028430_STENCILWRITEMASK(state->writemask[0]),
 153                                 NULL, 0);
 154         r600_pipe_state_add_reg(rstate,
 155                                 R_028434_DB_STENCILREFMASK_BF,
 156                                 S_028434_STENCILTESTVAL_BF(state->ref_value[1]) |
 157                                 S_028434_STENCILMASK_BF(state->valuemask[1]) |
 158                                 S_028434_STENCILWRITEMASK_BF(state->writemask[1]),
 159                                 NULL, 0);
 160
 161         free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
 162         rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
 163         r600_context_pipe_state_set(rctx, rstate);
 164 }
 165
 166 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 167                                const struct pipe_stencil_ref *state)
 168 {
 169         struct r600_context *rctx = (struct r600_context *)ctx;
 170         struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
 171         struct r600_stencil_ref ref;
 172
 173         rctx->stencil_ref = *state;
 174
 175         if (!dsa)
 176                 return;
 177
 178         ref.ref_value[0] = state->ref_value[0];
 179         ref.ref_value[1] = state->ref_value[1];
 180         ref.valuemask[0] = dsa->valuemask[0];
 181         ref.valuemask[1] = dsa->valuemask[1];
 182         ref.writemask[0] = dsa->writemask[0];
 183         ref.writemask[1] = dsa->writemask[1];
 184
 185         r600_set_stencil_ref(ctx, &ref);
 186 }
 187
 188 void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
 189 {
 190         struct r600_context *rctx = (struct r600_context *)ctx;
 191         struct r600_pipe_dsa *dsa = state;
 192         struct r600_pipe_state *rstate;
 193         struct r600_stencil_ref ref;
 194
 195         if (state == NULL)
 196                 return;
 197         rstate = &dsa->rstate;
 198         rctx->states[rstate->id] = rstate;
 199         rctx->alpha_ref = dsa->alpha_ref;
 200         rctx->alpha_ref_dirty = true;
 201         r600_context_pipe_state_set(rctx, rstate);
 202
 203         ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
 204         ref.ref_value[1] = rctx->stencil_ref.ref_value[1];
 205         ref.valuemask[0] = dsa->valuemask[0];
 206         ref.valuemask[1] = dsa->valuemask[1];
 207         ref.writemask[0] = dsa->writemask[0];
 208         ref.writemask[1] = dsa->writemask[1];
 209
 210         r600_set_stencil_ref(ctx, &ref);
 211 }
 212
 213 void r600_bind_rs_state(struct pipe_context *ctx, void *state)
 214 {
 215         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
 216         struct r600_context *rctx = (struct r600_context *)ctx;
 217
 218         if (state == NULL)
 219                 return;
 220
 221         rctx->sprite_coord_enable = rs->sprite_coord_enable;
 222         rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
 223         rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
 224         rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
 225         rctx->pa_cl_vs_out_cntl = rs->pa_cl_vs_out_cntl;
 226
 227         rctx->rasterizer = rs;
 228
 229         rctx->states[rs->rstate.id] = &rs->rstate;
 230         r600_context_pipe_state_set(rctx, &rs->rstate);
 231
 232         if (rctx->chip_class >= CAYMAN) {
 233                 cayman_polygon_offset_update(rctx);
 234         }
 235 }
 236
 237 void r600_delete_rs_state(struct pipe_context *ctx, void *state)
 238 {
 239         struct r600_context *rctx = (struct r600_context *)ctx;
 240         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
 241
 242         if (rctx->rasterizer == rs) {
 243                 rctx->rasterizer = NULL;
 244         }
 245         if (rctx->states[rs->rstate.id] == &rs->rstate) {
 246                 rctx->states[rs->rstate.id] = NULL;
 247         }
 248         free(rs);
 249 }
 250
 251 void r600_sampler_view_destroy(struct pipe_context *ctx,
 252                                struct pipe_sampler_view *state)
 253 {
 254         struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
 255
 256         pipe_resource_reference(&state->texture, NULL);
 257         FREE(resource);
 258 }
 259
 260 void r600_delete_state(struct pipe_context *ctx, void *state)
 261 {
 262         struct r600_context *rctx = (struct r600_context *)ctx;
 263         struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
 264
 265         if (rctx->states[rstate->id] == rstate) {
 266                 rctx->states[rstate->id] = NULL;
 267         }
 268         for (int i = 0; i < rstate->nregs; i++) {
 269                 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
 270         }
 271         free(rstate);
 272 }
 273
 274 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
 275 {
 276         struct r600_context *rctx = (struct r600_context *)ctx;
 277         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 278
 279         rctx->vertex_elements = v;
 280         if (v) {
 281                 r600_inval_shader_cache(rctx);
 282
 283                 rctx->states[v->rstate.id] = &v->rstate;
 284                 r600_context_pipe_state_set(rctx, &v->rstate);
 285         }
 286 }
 287
 288 void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
 289 {
 290         struct r600_context *rctx = (struct r600_context *)ctx;
 291         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 292
 293         if (rctx->states[v->rstate.id] == &v->rstate) {
 294                 rctx->states[v->rstate.id] = NULL;
 295         }
 296         if (rctx->vertex_elements == state)
 297                 rctx->vertex_elements = NULL;
 298         FREE(state);
 299 }
 300
 301
 302 void r600_set_index_buffer(struct pipe_context *ctx,
 303                            const struct pipe_index_buffer *ib)
 304 {
 305         struct r600_context *rctx = (struct r600_context *)ctx;
 306
 307         if (ib) {
 308                 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
 309                 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
 310         } else {
 311                 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
 312         }
 313 }
 314
 315 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 316                              const struct pipe_vertex_buffer *buffers)
 317 {
 318         struct r600_context *rctx = (struct r600_context *)ctx;
 319
 320         util_copy_vertex_buffers(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, count);
 321 }
 322
 323 void *si_create_vertex_elements(struct pipe_context *ctx,
 324                                 unsigned count,
 325                                 const struct pipe_vertex_element *elements)
 326 {
 327         struct r600_context *rctx = (struct r600_context *)ctx;
 328         struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
 329
 330         assert(count < 32);
 331         if (!v)
 332                 return NULL;
 333
 334         v->count = count;
 335         memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
 336
 337         return v;
 338 }
 339
 340 void *si_create_shader_state(struct pipe_context *ctx,
 341                              const struct pipe_shader_state *state)
 342 {
 343         struct si_pipe_shader *shader = CALLOC_STRUCT(si_pipe_shader);
 344
 345         shader->tokens = tgsi_dup_tokens(state->tokens);
 346         shader->so = state->stream_output;
 347
 348         return shader;
 349 }
 350
 351 void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
 352 {
 353         struct r600_context *rctx = (struct r600_context *)ctx;
 354
 355         if (rctx->ps_shader != state)
 356                 rctx->shader_dirty = true;
 357
 358         /* TODO delete old shader */
 359         rctx->ps_shader = (struct si_pipe_shader *)state;
 360         if (state) {
 361                 r600_inval_shader_cache(rctx);
 362                 r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
 363         }
 364 }
 365
 366 void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
 367 {
 368         struct r600_context *rctx = (struct r600_context *)ctx;
 369
 370         if (rctx->vs_shader != state)
 371                 rctx->shader_dirty = true;
 372
 373         /* TODO delete old shader */
 374         rctx->vs_shader = (struct si_pipe_shader *)state;
 375         if (state) {
 376                 r600_inval_shader_cache(rctx);
 377                 r600_context_pipe_state_set(rctx, &rctx->vs_shader->rstate);
 378         }
 379 }
 380
 381 void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
 382 {
 383         struct r600_context *rctx = (struct r600_context *)ctx;
 384         struct si_pipe_shader *shader = (struct si_pipe_shader *)state;
 385
 386         if (rctx->ps_shader == shader) {
 387                 rctx->ps_shader = NULL;
 388         }
 389
 390         free(shader->tokens);
 391         si_pipe_shader_destroy(ctx, shader);
 392         free(shader);
 393 }
 394
 395 void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
 396 {
 397         struct r600_context *rctx = (struct r600_context *)ctx;
 398         struct si_pipe_shader *shader = (struct si_pipe_shader *)state;
 399
 400         if (rctx->vs_shader == shader) {
 401                 rctx->vs_shader = NULL;
 402         }
 403
 404         free(shader->tokens);
 405         si_pipe_shader_destroy(ctx, shader);
 406         free(shader);
 407 }
 408
 409 static void r600_update_alpha_ref(struct r600_context *rctx)
 410 {
 411 #if 0
 412         unsigned alpha_ref;
 413         struct r600_pipe_state rstate;
 414
 415         alpha_ref = rctx->alpha_ref;
 416         rstate.nregs = 0;
 417         if (rctx->export_16bpc)
 418                 alpha_ref &= ~0x1FFF;
 419         r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref, NULL, 0);
 420
 421         r600_context_pipe_state_set(rctx, &rstate);
 422         rctx->alpha_ref_dirty = false;
 423 #endif
 424 }
 425
 426 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 427                               struct pipe_resource *buffer)
 428 {
 429         struct r600_context *rctx = (struct r600_context *)ctx;
 430         struct r600_resource *rbuffer = r600_resource(buffer);
 431         struct r600_pipe_state *rstate;
 432         uint64_t va_offset;
 433         uint32_t offset;
 434
 435         /* Note that the state tracker can unbind constant buffers by
 436          * passing NULL here.
 437          */
 438         if (buffer == NULL) {
 439                 return;
 440         }
 441
 442         r600_inval_shader_cache(rctx);
 443
 444         r600_upload_const_buffer(rctx, &rbuffer, &offset);
 445         va_offset = r600_resource_va(ctx->screen, (void*)rbuffer);
 446         va_offset += offset;
 447         //va_offset >>= 8;
 448
 449         switch (shader) {
 450         case PIPE_SHADER_VERTEX:
 451                 rstate = &rctx->vs_const_buffer;
 452                 rstate->nregs = 0;
 453                 r600_pipe_state_add_reg(rstate,
 454                                         R_00B130_SPI_SHADER_USER_DATA_VS_0,
 455                                         va_offset, rbuffer, RADEON_USAGE_READ);
 456                 r600_pipe_state_add_reg(rstate,
 457                                         R_00B134_SPI_SHADER_USER_DATA_VS_1,
 458                                         va_offset >> 32, NULL, 0);
 459                 break;
 460         case PIPE_SHADER_FRAGMENT:
 461                 rstate = &rctx->ps_const_buffer;
 462                 rstate->nregs = 0;
 463                 r600_pipe_state_add_reg(rstate,
 464                                         R_00B030_SPI_SHADER_USER_DATA_PS_0,
 465                                         va_offset, rbuffer, RADEON_USAGE_READ);
 466                 r600_pipe_state_add_reg(rstate,
 467                                         R_00B034_SPI_SHADER_USER_DATA_PS_1,
 468                                         va_offset >> 32, NULL, 0);
 469                 break;
 470         default:
 471                 R600_ERR("unsupported %d\n", shader);
 472                 return;
 473         }
 474
 475         r600_context_pipe_state_set(rctx, rstate);
 476
 477         if (buffer != &rbuffer->b.b)
 478                 pipe_resource_reference((struct pipe_resource**)&rbuffer, NULL);
 479 }
 480
 481 struct pipe_stream_output_target *
 482 r600_create_so_target(struct pipe_context *ctx,
 483                       struct pipe_resource *buffer,
 484                       unsigned buffer_offset,
 485                       unsigned buffer_size)
 486 {
 487         struct r600_context *rctx = (struct r600_context *)ctx;
 488         struct r600_so_target *t;
 489         void *ptr;
 490
 491         t = CALLOC_STRUCT(r600_so_target);
 492         if (!t) {
 493                 return NULL;
 494         }
 495
 496         t->b.reference.count = 1;
 497         t->b.context = ctx;
 498         pipe_resource_reference(&t->b.buffer, buffer);
 499         t->b.buffer_offset = buffer_offset;
 500         t->b.buffer_size = buffer_size;
 501
 502         t->filled_size = (struct r600_resource*)
 503                 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
 504         ptr = rctx->ws->buffer_map(t->filled_size->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
 505         memset(ptr, 0, t->filled_size->buf->size);
 506         rctx->ws->buffer_unmap(t->filled_size->cs_buf);
 507
 508         return &t->b;
 509 }
 510
 511 void r600_so_target_destroy(struct pipe_context *ctx,
 512                             struct pipe_stream_output_target *target)
 513 {
 514         struct r600_so_target *t = (struct r600_so_target*)target;
 515         pipe_resource_reference(&t->b.buffer, NULL);
 516         pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
 517         FREE(t);
 518 }
 519
 520 void r600_set_so_targets(struct pipe_context *ctx,
 521                          unsigned num_targets,
 522                          struct pipe_stream_output_target **targets,
 523                          unsigned append_bitmask)
 524 {
 525         struct r600_context *rctx = (struct r600_context *)ctx;
 526         unsigned i;
 527
 528         /* Stop streamout. */
 529         if (rctx->num_so_targets) {
 530                 r600_context_streamout_end(rctx);
 531         }
 532
 533         /* Set the new targets. */
 534         for (i = 0; i < num_targets; i++) {
 535                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
 536         }
 537         for (; i < rctx->num_so_targets; i++) {
 538                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
 539         }
 540
 541         rctx->num_so_targets = num_targets;
 542         rctx->streamout_start = num_targets != 0;
 543         rctx->streamout_append_bitmask = append_bitmask;
 544 }
 545
 546 static void r600_vertex_buffer_update(struct r600_context *rctx)
 547 {
 548         struct pipe_context *ctx = &rctx->context;
 549         struct r600_pipe_state *rstate = &rctx->vs_user_data;
 550         struct r600_resource *rbuffer, *t_list_buffer;
 551         struct pipe_vertex_buffer *vertex_buffer;
 552         unsigned i, count, offset;
 553         uint32_t *ptr;
 554         uint64_t va;
 555
 556         r600_inval_vertex_cache(rctx);
 557
 558         if (rctx->vertex_elements->vbuffer_need_offset) {
 559                 /* one resource per vertex elements */
 560                 count = rctx->vertex_elements->count;
 561         } else {
 562                 /* bind vertex buffer once */
 563                 count = rctx->nr_vertex_buffers;
 564         }
 565         assert(count <= 256 / 4);
 566
 567         t_list_buffer = (struct r600_resource*)
 568                 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM,
 569                                    PIPE_USAGE_IMMUTABLE, 4 * 4 * count);
 570         if (t_list_buffer == NULL)
 571                 return;
 572
 573         ptr = (uint32_t*)rctx->ws->buffer_map(t_list_buffer->cs_buf,
 574                                               rctx->cs,
 575                                               PIPE_TRANSFER_WRITE);
 576
 577         for (i = 0 ; i < count; i++, ptr += 4) {
 578                 struct pipe_vertex_element *velem = &rctx->vertex_elements->elements[i];
 579                 const struct util_format_description *desc;
 580                 unsigned data_format, num_format;
 581                 int first_non_void;
 582
 583                 if (rctx->vertex_elements->vbuffer_need_offset) {
 584                         /* one resource per vertex elements */
 585                         unsigned vbuffer_index;
 586                         vbuffer_index = rctx->vertex_elements->elements[i].vertex_buffer_index;
 587                         vertex_buffer = &rctx->vertex_buffer[vbuffer_index];
 588                         rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 589                         offset = rctx->vertex_elements->vbuffer_offset[i];
 590                 } else {
 591                         /* bind vertex buffer once */
 592                         vertex_buffer = &rctx->vertex_buffer[i];
 593                         rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 594                         offset = 0;
 595                 }
 596                 if (vertex_buffer == NULL || rbuffer == NULL)
 597                         continue;
 598                 offset += vertex_buffer->buffer_offset;
 599
 600                 va = r600_resource_va(ctx->screen, (void*)rbuffer);
 601                 va += offset;
 602
 603                 desc = util_format_description(velem->src_format);
 604                 first_non_void = util_format_get_first_non_void_channel(velem->src_format);
 605                 data_format = si_translate_vertexformat(ctx->screen,
 606                                                         velem->src_format,
 607                                                         desc, first_non_void);
 608
 609                 switch (desc->channel[first_non_void].type) {
 610                 case UTIL_FORMAT_TYPE_FIXED:
 611                         num_format = V_008F0C_BUF_NUM_FORMAT_USCALED; /* XXX */
 612                         break;
 613                 case UTIL_FORMAT_TYPE_SIGNED:
 614                         num_format = V_008F0C_BUF_NUM_FORMAT_SNORM;
 615                         break;
 616                 case UTIL_FORMAT_TYPE_UNSIGNED:
 617                         num_format = V_008F0C_BUF_NUM_FORMAT_UNORM;
 618                         break;
 619                 case UTIL_FORMAT_TYPE_FLOAT:
 620                 default:
 621                         num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
 622                 }
 623
 624                 /* Fill in T# buffer resource description */
 625                 ptr[0] = va & 0xFFFFFFFF;
 626                 ptr[1] = (S_008F04_BASE_ADDRESS_HI(va >> 32) |
 627                           S_008F04_STRIDE(vertex_buffer->stride));
 628                 ptr[2] = (vertex_buffer->buffer->width0 - offset) / vertex_buffer->stride;
 629                 /* XXX: Hardcoding RGBA */
 630                 ptr[3] = (S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
 631                           S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
 632                           S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
 633                           S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
 634                           S_008F0C_NUM_FORMAT(num_format) |
 635                           S_008F0C_DATA_FORMAT(data_format));
 636
 637                 r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ);
 638         }
 639
 640         rstate->nregs = 0;
 641
 642         va = r600_resource_va(ctx->screen, (void*)t_list_buffer);
 643         r600_pipe_state_add_reg(rstate,
 644                                 R_00B148_SPI_SHADER_USER_DATA_VS_6,
 645                                 va, t_list_buffer, RADEON_USAGE_READ);
 646         r600_pipe_state_add_reg(rstate,
 647                                 R_00B14C_SPI_SHADER_USER_DATA_VS_7,
 648                                 va >> 32,
 649                                 NULL, 0);
 650
 651         r600_context_pipe_state_set(rctx, rstate);
 652 }
 653
 654 static void si_update_derived_state(struct r600_context *rctx)
 655 {
 656         struct pipe_context * ctx = (struct pipe_context*)rctx;
 657
 658         if (!rctx->blitter->running) {
 659                 if (rctx->have_depth_fb || rctx->have_depth_texture)
 660                         r600_flush_depth_textures(rctx);
 661         }
 662
 663         if (rctx->shader_dirty) {
 664                 si_pipe_shader_destroy(&rctx->context, rctx->vs_shader);
 665         }
 666
 667         if (rctx->shader_dirty ||
 668             (rctx->ps_shader->shader.fs_write_all &&
 669              (rctx->ps_shader->shader.nr_cbufs != rctx->nr_cbufs)) ||
 670             (rctx->sprite_coord_enable &&
 671              (rctx->ps_shader->sprite_coord_enable != rctx->sprite_coord_enable))) {
 672                 si_pipe_shader_destroy(&rctx->context, rctx->ps_shader);
 673         }
 674
 675         if (rctx->alpha_ref_dirty) {
 676                 r600_update_alpha_ref(rctx);
 677         }
 678
 679         if (!rctx->vs_shader->bo) {
 680                 si_pipe_shader_vs(ctx, rctx->vs_shader);
 681
 682                 r600_context_pipe_state_set(rctx, &rctx->vs_shader->rstate);
 683         }
 684
 685         if (!rctx->ps_shader->bo) {
 686                 si_pipe_shader_ps(ctx, rctx->ps_shader);
 687
 688                 r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
 689         }
 690
 691         if (rctx->shader_dirty) {
 692                 si_update_spi_map(rctx);
 693                 rctx->shader_dirty = false;
 694         }
 695 }
 696
 697 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
 698 {
 699         struct r600_context *rctx = (struct r600_context *)ctx;
 700         struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
 701         struct pipe_draw_info info = *dinfo;
 702         struct r600_draw rdraw = {};
 703         struct pipe_index_buffer ib = {};
 704         unsigned prim, mask, ls_mask = 0;
 705         struct r600_block *dirty_block = NULL, *next_block = NULL;
 706         struct r600_atom *state = NULL, *next_state = NULL;
 707         int i;
 708
 709         if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
 710             (info.indexed && !rctx->index_buffer.buffer) ||
 711             !r600_conv_pipe_prim(info.mode, &prim)) {
 712                 return;
 713         }
 714
 715         if (!rctx->ps_shader || !rctx->vs_shader)
 716                 return;
 717
 718         si_update_derived_state(rctx);
 719
 720         r600_vertex_buffer_update(rctx);
 721
 722         rdraw.vgt_num_indices = info.count;
 723         rdraw.vgt_num_instances = info.instance_count;
 724
 725         if (info.indexed) {
 726                 /* Initialize the index buffer struct. */
 727                 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
 728                 ib.index_size = rctx->index_buffer.index_size;
 729                 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
 730
 731                 /* Translate or upload, if needed. */
 732                 r600_translate_index_buffer(rctx, &ib, info.count);
 733
 734                 if (ib.buffer->user_ptr) {
 735                         r600_upload_index_buffer(rctx, &ib, info.count);
 736                 }
 737
 738                 /* Initialize the r600_draw struct with index buffer info. */
 739                 if (ib.index_size == 4) {
 740                         rdraw.vgt_index_type = V_028A7C_VGT_INDEX_32 |
 741                                 (R600_BIG_ENDIAN ? V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
 742                 } else {
 743                         rdraw.vgt_index_type = V_028A7C_VGT_INDEX_16 |
 744                                 (R600_BIG_ENDIAN ? V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
 745                 }
 746                 rdraw.indices = (struct r600_resource*)ib.buffer;
 747                 rdraw.indices_bo_offset = ib.offset;
 748                 rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_DMA;
 749         } else {
 750                 info.index_bias = info.start;
 751                 rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
 752                 if (info.count_from_stream_output) {
 753                         rdraw.vgt_draw_initiator |= S_0287F0_USE_OPAQUE(1);
 754
 755                         r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info.count_from_stream_output);
 756                 }
 757         }
 758
 759         rctx->vs_shader_so_strides = rctx->vs_shader->so_strides;
 760
 761         mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
 762
 763         if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
 764                 rctx->vgt.id = R600_PIPE_STATE_VGT;
 765                 rctx->vgt.nregs = 0;
 766                 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, NULL, 0);
 767                 r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, NULL, 0);
 768                 r600_pipe_state_add_reg(&rctx->vgt, R_028400_VGT_MAX_VTX_INDX, ~0, NULL, 0);
 769                 r600_pipe_state_add_reg(&rctx->vgt, R_028404_VGT_MIN_VTX_INDX, 0, NULL, 0);
 770                 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias, NULL, 0);
 771                 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index, NULL, 0);
 772                 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart, NULL, 0);
 773 #if 0
 774                 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, NULL, 0);
 775                 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance, NULL, 0);
 776 #endif
 777                 r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0, NULL, 0);
 778                 r600_pipe_state_add_reg(&rctx->vgt, R_028814_PA_SU_SC_MODE_CNTL, 0, NULL, 0);
 779                 r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0, NULL, 0);
 780                 r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0x0, NULL, 0);
 781         }
 782
 783         rctx->vgt.nregs = 0;
 784         r600_pipe_state_mod_reg(&rctx->vgt, prim);
 785         r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_target_mask & mask);
 786         r600_pipe_state_mod_reg(&rctx->vgt, ~0);
 787         r600_pipe_state_mod_reg(&rctx->vgt, 0);
 788         r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
 789         r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
 790         r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
 791 #if 0
 792         r600_pipe_state_mod_reg(&rctx->vgt, 0);
 793         r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
 794 #endif
 795
 796         if (prim == V_008958_DI_PT_LINELIST)
 797                 ls_mask = 1;
 798         else if (prim == V_008958_DI_PT_LINESTRIP)
 799                 ls_mask = 2;
 800         r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
 801
 802         if (info.mode == PIPE_PRIM_QUADS || info.mode == PIPE_PRIM_QUAD_STRIP || info.mode == PIPE_PRIM_POLYGON) {
 803                 r600_pipe_state_mod_reg(&rctx->vgt, S_028814_PROVOKING_VTX_LAST(1) | rctx->pa_su_sc_mode_cntl);
 804         } else {
 805                 r600_pipe_state_mod_reg(&rctx->vgt, rctx->pa_su_sc_mode_cntl);
 806         }
 807         r600_pipe_state_mod_reg(&rctx->vgt,
 808                                 rctx->pa_cl_vs_out_cntl /*|
 809                                 (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->shader.clip_dist_write)*/);
 810         r600_pipe_state_mod_reg(&rctx->vgt,
 811                                 rctx->pa_cl_clip_cntl /*|
 812                                 (rctx->vs_shader->shader.clip_dist_write ||
 813                                  rctx->vs_shader->shader.vs_prohibit_ucps ?
 814                                  0 : rctx->rasterizer->clip_plane_enable & 0x3F)*/);
 815
 816         r600_context_pipe_state_set(rctx, &rctx->vgt);
 817
 818         rdraw.db_render_override = dsa->db_render_override;
 819         rdraw.db_render_control = dsa->db_render_control;
 820
 821         /* Emit states. */
 822         r600_need_cs_space(rctx, 0, TRUE);
 823
 824         LIST_FOR_EACH_ENTRY_SAFE(state, next_state, &rctx->dirty_states, head) {
 825                 r600_emit_atom(rctx, state);
 826         }
 827         LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
 828                 r600_context_block_emit_dirty(rctx, dirty_block);
 829         }
 830         rctx->pm4_dirty_cdwords = 0;
 831
 832         /* Enable stream out if needed. */
 833         if (rctx->streamout_start) {
 834                 r600_context_streamout_begin(rctx);
 835                 rctx->streamout_start = FALSE;
 836         }
 837
 838         for (i = 0; i < NUM_TEX_UNITS; i++) {
 839                 if (rctx->ps_samplers.views[i])
 840                         r600_context_bo_reloc(rctx,
 841                                               (struct r600_resource*)rctx->ps_samplers.views[i]->base.texture,
 842                                               RADEON_USAGE_READ);
 843         }
 844
 845         if (rctx->chip_class >= CAYMAN) {
 846                 evergreen_context_draw(rctx, &rdraw);
 847         }
 848
 849         rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING;
 850
 851         if (rctx->framebuffer.zsbuf)
 852         {
 853                 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture;
 854                 ((struct r600_resource_texture *)tex)->dirty_db = TRUE;
 855         }
 856
 857         pipe_resource_reference(&ib.buffer, NULL);
 858 }
 859
 860 void _r600_pipe_state_add_reg(struct r600_context *ctx,
 861                               struct r600_pipe_state *state,
 862                               uint32_t offset, uint32_t value,
 863                               uint32_t range_id, uint32_t block_id,
 864                               struct r600_resource *bo,
 865                               enum radeon_bo_usage usage)
 866 {
 867         struct r600_range *range;
 868         struct r600_block *block;
 869
 870         if (bo) assert(usage);
 871
 872         range = &ctx->range[range_id];
 873         block = range->blocks[block_id];
 874         state->regs[state->nregs].block = block;
 875         state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
 876
 877         state->regs[state->nregs].value = value;
 878         state->regs[state->nregs].bo = bo;
 879         state->regs[state->nregs].bo_usage = usage;
 880
 881         state->nregs++;
 882         assert(state->nregs < R600_BLOCK_MAX_REG);
 883 }
 884
 885 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
 886                                      uint32_t offset, uint32_t value,
 887                                      struct r600_resource *bo,
 888                                      enum radeon_bo_usage usage)
 889 {
 890         if (bo) assert(usage);
 891
 892         state->regs[state->nregs].id = offset;
 893         state->regs[state->nregs].block = NULL;
 894         state->regs[state->nregs].value = value;
 895         state->regs[state->nregs].bo = bo;
 896         state->regs[state->nregs].bo_usage = usage;
 897
 898         state->nregs++;
 899         assert(state->nregs < R600_BLOCK_MAX_REG);
 900 }