src/gallium/drivers/radeonsi/r600_state_common.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *           2010 Jerome Glisse
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie <airlied@redhat.com>
  25  *          Jerome Glisse <jglisse@redhat.com>
  26  */
  27 #include "util/u_blitter.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_format.h"
  30 #include "pipebuffer/pb_buffer.h"
  31 #include "pipe/p_shader_tokens.h"
  32 #include "tgsi/tgsi_parse.h"
  33 #include "r600_hw_context_priv.h"
  34 #include "radeonsi_pipe.h"
  35 #include "sid.h"
  36
  37 static void r600_emit_surface_sync(struct r600_context *rctx, struct r600_atom *atom)
  38 {
  39         struct radeon_winsys_cs *cs = rctx->cs;
  40         struct r600_atom_surface_sync *a = (struct r600_atom_surface_sync*)atom;
  41
  42         cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
  43         cs->buf[cs->cdw++] = a->flush_flags;  /* CP_COHER_CNTL */
  44         cs->buf[cs->cdw++] = 0xffffffff;      /* CP_COHER_SIZE */
  45         cs->buf[cs->cdw++] = 0;               /* CP_COHER_BASE */
  46         cs->buf[cs->cdw++] = 0x0000000A;      /* POLL_INTERVAL */
  47
  48         a->flush_flags = 0;
  49 }
  50
  51 static void r600_emit_r6xx_flush_and_inv(struct r600_context *rctx, struct r600_atom *atom)
  52 {
  53         struct radeon_winsys_cs *cs = rctx->cs;
  54         cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
  55         cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
  56 }
  57
  58 static void r600_init_atom(struct r600_atom *atom,
  59                            void (*emit)(struct r600_context *ctx, struct r600_atom *state),
  60                            unsigned num_dw,
  61                            enum r600_atom_flags flags)
  62 {
  63         atom->emit = emit;
  64         atom->num_dw = num_dw;
  65         atom->flags = flags;
  66 }
  67
  68 void r600_init_common_atoms(struct r600_context *rctx)
  69 {
  70         r600_init_atom(&rctx->atom_surface_sync.atom,   r600_emit_surface_sync,         5, EMIT_EARLY);
  71         r600_init_atom(&rctx->atom_r6xx_flush_and_inv,  r600_emit_r6xx_flush_and_inv,   2, EMIT_EARLY);
  72 }
  73
  74 unsigned r600_get_cb_flush_flags(struct r600_context *rctx)
  75 {
  76         unsigned flags = 0;
  77
  78         if (rctx->framebuffer.nr_cbufs) {
  79                 flags |= S_0085F0_CB_ACTION_ENA(1) |
  80                          (((1 << rctx->framebuffer.nr_cbufs) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT);
  81         }
  82
  83         return flags;
  84 }
  85
  86 void r600_texture_barrier(struct pipe_context *ctx)
  87 {
  88         struct r600_context *rctx = (struct r600_context *)ctx;
  89
  90         rctx->atom_surface_sync.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx);
  91         r600_atom_dirty(rctx, &rctx->atom_surface_sync.atom);
  92 }
  93
  94 static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
  95 {
  96         static const int prim_conv[] = {
  97                 V_008958_DI_PT_POINTLIST,
  98                 V_008958_DI_PT_LINELIST,
  99                 V_008958_DI_PT_LINELOOP,
 100                 V_008958_DI_PT_LINESTRIP,
 101                 V_008958_DI_PT_TRILIST,
 102                 V_008958_DI_PT_TRISTRIP,
 103                 V_008958_DI_PT_TRIFAN,
 104                 V_008958_DI_PT_QUADLIST,
 105                 V_008958_DI_PT_QUADSTRIP,
 106                 V_008958_DI_PT_POLYGON,
 107                 -1,
 108                 -1,
 109                 -1,
 110                 -1
 111         };
 112
 113         *prim = prim_conv[pprim];
 114         if (*prim == -1) {
 115                 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
 116                 return false;
 117         }
 118         return true;
 119 }
 120
 121 /* common state between evergreen and r600 */
 122 void r600_bind_blend_state(struct pipe_context *ctx, void *state)
 123 {
 124         struct r600_context *rctx = (struct r600_context *)ctx;
 125         struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
 126         struct r600_pipe_state *rstate;
 127
 128         if (state == NULL)
 129                 return;
 130         rstate = &blend->rstate;
 131         rctx->states[rstate->id] = rstate;
 132         rctx->cb_target_mask = blend->cb_target_mask;
 133         rctx->cb_color_control = blend->cb_color_control;
 134
 135         r600_context_pipe_state_set(rctx, rstate);
 136 }
 137
 138 static void r600_set_stencil_ref(struct pipe_context *ctx,
 139                                  const struct r600_stencil_ref *state)
 140 {
 141         struct r600_context *rctx = (struct r600_context *)ctx;
 142         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 143
 144         if (rstate == NULL)
 145                 return;
 146
 147         rstate->id = R600_PIPE_STATE_STENCIL_REF;
 148         r600_pipe_state_add_reg(rstate,
 149                                 R_028430_DB_STENCILREFMASK,
 150                                 S_028430_STENCILTESTVAL(state->ref_value[0]) |
 151                                 S_028430_STENCILMASK(state->valuemask[0]) |
 152                                 S_028430_STENCILWRITEMASK(state->writemask[0]),
 153                                 NULL, 0);
 154         r600_pipe_state_add_reg(rstate,
 155                                 R_028434_DB_STENCILREFMASK_BF,
 156                                 S_028434_STENCILTESTVAL_BF(state->ref_value[1]) |
 157                                 S_028434_STENCILMASK_BF(state->valuemask[1]) |
 158                                 S_028434_STENCILWRITEMASK_BF(state->writemask[1]),
 159                                 NULL, 0);
 160
 161         free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
 162         rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
 163         r600_context_pipe_state_set(rctx, rstate);
 164 }
 165
 166 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 167                                const struct pipe_stencil_ref *state)
 168 {
 169         struct r600_context *rctx = (struct r600_context *)ctx;
 170         struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
 171         struct r600_stencil_ref ref;
 172
 173         rctx->stencil_ref = *state;
 174
 175         if (!dsa)
 176                 return;
 177
 178         ref.ref_value[0] = state->ref_value[0];
 179         ref.ref_value[1] = state->ref_value[1];
 180         ref.valuemask[0] = dsa->valuemask[0];
 181         ref.valuemask[1] = dsa->valuemask[1];
 182         ref.writemask[0] = dsa->writemask[0];
 183         ref.writemask[1] = dsa->writemask[1];
 184
 185         r600_set_stencil_ref(ctx, &ref);
 186 }
 187
 188 void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
 189 {
 190         struct r600_context *rctx = (struct r600_context *)ctx;
 191         struct r600_pipe_dsa *dsa = state;
 192         struct r600_pipe_state *rstate;
 193         struct r600_stencil_ref ref;
 194
 195         if (state == NULL)
 196                 return;
 197         rstate = &dsa->rstate;
 198         rctx->states[rstate->id] = rstate;
 199         rctx->alpha_ref = dsa->alpha_ref;
 200         rctx->alpha_ref_dirty = true;
 201         r600_context_pipe_state_set(rctx, rstate);
 202
 203         ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
 204         ref.ref_value[1] = rctx->stencil_ref.ref_value[1];
 205         ref.valuemask[0] = dsa->valuemask[0];
 206         ref.valuemask[1] = dsa->valuemask[1];
 207         ref.writemask[0] = dsa->writemask[0];
 208         ref.writemask[1] = dsa->writemask[1];
 209
 210         r600_set_stencil_ref(ctx, &ref);
 211 }
 212
 213 void r600_bind_rs_state(struct pipe_context *ctx, void *state)
 214 {
 215         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
 216         struct r600_context *rctx = (struct r600_context *)ctx;
 217
 218         if (state == NULL)
 219                 return;
 220
 221         rctx->sprite_coord_enable = rs->sprite_coord_enable;
 222         rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
 223         rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
 224         rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
 225         rctx->pa_cl_vs_out_cntl = rs->pa_cl_vs_out_cntl;
 226
 227         rctx->rasterizer = rs;
 228
 229         rctx->states[rs->rstate.id] = &rs->rstate;
 230         r600_context_pipe_state_set(rctx, &rs->rstate);
 231
 232         if (rctx->chip_class >= CAYMAN) {
 233                 cayman_polygon_offset_update(rctx);
 234         }
 235 }
 236
 237 void r600_delete_rs_state(struct pipe_context *ctx, void *state)
 238 {
 239         struct r600_context *rctx = (struct r600_context *)ctx;
 240         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
 241
 242         if (rctx->rasterizer == rs) {
 243                 rctx->rasterizer = NULL;
 244         }
 245         if (rctx->states[rs->rstate.id] == &rs->rstate) {
 246                 rctx->states[rs->rstate.id] = NULL;
 247         }
 248         free(rs);
 249 }
 250
 251 void r600_sampler_view_destroy(struct pipe_context *ctx,
 252                                struct pipe_sampler_view *state)
 253 {
 254         struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
 255
 256         pipe_resource_reference(&state->texture, NULL);
 257         FREE(resource);
 258 }
 259
 260 void r600_delete_state(struct pipe_context *ctx, void *state)
 261 {
 262         struct r600_context *rctx = (struct r600_context *)ctx;
 263         struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
 264
 265         if (rctx->states[rstate->id] == rstate) {
 266                 rctx->states[rstate->id] = NULL;
 267         }
 268         for (int i = 0; i < rstate->nregs; i++) {
 269                 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
 270         }
 271         free(rstate);
 272 }
 273
 274 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
 275 {
 276         struct r600_context *rctx = (struct r600_context *)ctx;
 277         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 278
 279         rctx->vertex_elements = v;
 280         if (v) {
 281                 r600_inval_shader_cache(rctx);
 282                 u_vbuf_bind_vertex_elements(rctx->vbuf_mgr, state,
 283                                                 v->vmgr_elements);
 284
 285                 rctx->states[v->rstate.id] = &v->rstate;
 286                 r600_context_pipe_state_set(rctx, &v->rstate);
 287         }
 288 }
 289
 290 void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
 291 {
 292         struct r600_context *rctx = (struct r600_context *)ctx;
 293         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 294
 295         if (rctx->states[v->rstate.id] == &v->rstate) {
 296                 rctx->states[v->rstate.id] = NULL;
 297         }
 298         if (rctx->vertex_elements == state)
 299                 rctx->vertex_elements = NULL;
 300
 301         u_vbuf_destroy_vertex_elements(rctx->vbuf_mgr, v->vmgr_elements);
 302         FREE(state);
 303 }
 304
 305
 306 void r600_set_index_buffer(struct pipe_context *ctx,
 307                            const struct pipe_index_buffer *ib)
 308 {
 309         struct r600_context *rctx = (struct r600_context *)ctx;
 310
 311         u_vbuf_set_index_buffer(rctx->vbuf_mgr, ib);
 312 }
 313
 314 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 315                              const struct pipe_vertex_buffer *buffers)
 316 {
 317         struct r600_context *rctx = (struct r600_context *)ctx;
 318
 319         u_vbuf_set_vertex_buffers(rctx->vbuf_mgr, count, buffers);
 320 }
 321
 322 void *si_create_vertex_elements(struct pipe_context *ctx,
 323                                 unsigned count,
 324                                 const struct pipe_vertex_element *elements)
 325 {
 326         struct r600_context *rctx = (struct r600_context *)ctx;
 327         struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
 328
 329         assert(count < 32);
 330         if (!v)
 331                 return NULL;
 332
 333         v->count = count;
 334         v->vmgr_elements =
 335                 u_vbuf_create_vertex_elements(rctx->vbuf_mgr, count,
 336                                                   elements, v->elements);
 337
 338         return v;
 339 }
 340
 341 void *si_create_shader_state(struct pipe_context *ctx,
 342                              const struct pipe_shader_state *state)
 343 {
 344         struct si_pipe_shader *shader = CALLOC_STRUCT(si_pipe_shader);
 345
 346         shader->tokens = tgsi_dup_tokens(state->tokens);
 347         shader->so = state->stream_output;
 348
 349         return shader;
 350 }
 351
 352 void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
 353 {
 354         struct r600_context *rctx = (struct r600_context *)ctx;
 355
 356         if (rctx->ps_shader != state)
 357                 rctx->shader_dirty = true;
 358
 359         /* TODO delete old shader */
 360         rctx->ps_shader = (struct si_pipe_shader *)state;
 361         if (state) {
 362                 r600_inval_shader_cache(rctx);
 363                 r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
 364         }
 365 }
 366
 367 void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
 368 {
 369         struct r600_context *rctx = (struct r600_context *)ctx;
 370
 371         if (rctx->vs_shader != state)
 372                 rctx->shader_dirty = true;
 373
 374         /* TODO delete old shader */
 375         rctx->vs_shader = (struct si_pipe_shader *)state;
 376         if (state) {
 377                 r600_inval_shader_cache(rctx);
 378                 r600_context_pipe_state_set(rctx, &rctx->vs_shader->rstate);
 379         }
 380 }
 381
 382 void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
 383 {
 384         struct r600_context *rctx = (struct r600_context *)ctx;
 385         struct si_pipe_shader *shader = (struct si_pipe_shader *)state;
 386
 387         if (rctx->ps_shader == shader) {
 388                 rctx->ps_shader = NULL;
 389         }
 390
 391         free(shader->tokens);
 392         si_pipe_shader_destroy(ctx, shader);
 393         free(shader);
 394 }
 395
 396 void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
 397 {
 398         struct r600_context *rctx = (struct r600_context *)ctx;
 399         struct si_pipe_shader *shader = (struct si_pipe_shader *)state;
 400
 401         if (rctx->vs_shader == shader) {
 402                 rctx->vs_shader = NULL;
 403         }
 404
 405         free(shader->tokens);
 406         si_pipe_shader_destroy(ctx, shader);
 407         free(shader);
 408 }
 409
 410 static void r600_update_alpha_ref(struct r600_context *rctx)
 411 {
 412 #if 0
 413         unsigned alpha_ref;
 414         struct r600_pipe_state rstate;
 415
 416         alpha_ref = rctx->alpha_ref;
 417         rstate.nregs = 0;
 418         if (rctx->export_16bpc)
 419                 alpha_ref &= ~0x1FFF;
 420         r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref, NULL, 0);
 421
 422         r600_context_pipe_state_set(rctx, &rstate);
 423         rctx->alpha_ref_dirty = false;
 424 #endif
 425 }
 426
 427 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 428                               struct pipe_resource *buffer)
 429 {
 430         struct r600_context *rctx = (struct r600_context *)ctx;
 431         struct r600_resource *rbuffer = r600_resource(buffer);
 432         struct r600_pipe_state *rstate;
 433         uint64_t va_offset;
 434         uint32_t offset;
 435
 436         /* Note that the state tracker can unbind constant buffers by
 437          * passing NULL here.
 438          */
 439         if (buffer == NULL) {
 440                 return;
 441         }
 442
 443         r600_inval_shader_cache(rctx);
 444
 445         r600_upload_const_buffer(rctx, &rbuffer, &offset);
 446         va_offset = r600_resource_va(ctx->screen, (void*)rbuffer);
 447         va_offset += offset;
 448         //va_offset >>= 8;
 449
 450         switch (shader) {
 451         case PIPE_SHADER_VERTEX:
 452                 rstate = &rctx->vs_const_buffer;
 453                 rstate->nregs = 0;
 454                 r600_pipe_state_add_reg(rstate,
 455                                         R_00B138_SPI_SHADER_USER_DATA_VS_2,
 456                                         va_offset, rbuffer, RADEON_USAGE_READ);
 457                 r600_pipe_state_add_reg(rstate,
 458                                         R_00B13C_SPI_SHADER_USER_DATA_VS_3,
 459                                         va_offset >> 32, NULL, 0);
 460                 break;
 461         case PIPE_SHADER_FRAGMENT:
 462                 rstate = &rctx->ps_const_buffer;
 463                 rstate->nregs = 0;
 464                 r600_pipe_state_add_reg(rstate,
 465                                         R_00B030_SPI_SHADER_USER_DATA_PS_0,
 466                                         va_offset, rbuffer, RADEON_USAGE_READ);
 467                 r600_pipe_state_add_reg(rstate,
 468                                         R_00B034_SPI_SHADER_USER_DATA_PS_1,
 469                                         va_offset >> 32, NULL, 0);
 470                 break;
 471         default:
 472                 R600_ERR("unsupported %d\n", shader);
 473                 return;
 474         }
 475
 476         r600_context_pipe_state_set(rctx, rstate);
 477
 478         if (buffer != &rbuffer->b.b.b)
 479                 pipe_resource_reference((struct pipe_resource**)&rbuffer, NULL);
 480 }
 481
 482 struct pipe_stream_output_target *
 483 r600_create_so_target(struct pipe_context *ctx,
 484                       struct pipe_resource *buffer,
 485                       unsigned buffer_offset,
 486                       unsigned buffer_size)
 487 {
 488         struct r600_context *rctx = (struct r600_context *)ctx;
 489         struct r600_so_target *t;
 490         void *ptr;
 491
 492         t = CALLOC_STRUCT(r600_so_target);
 493         if (!t) {
 494                 return NULL;
 495         }
 496
 497         t->b.reference.count = 1;
 498         t->b.context = ctx;
 499         pipe_resource_reference(&t->b.buffer, buffer);
 500         t->b.buffer_offset = buffer_offset;
 501         t->b.buffer_size = buffer_size;
 502
 503         t->filled_size = (struct r600_resource*)
 504                 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
 505         ptr = rctx->ws->buffer_map(t->filled_size->buf, rctx->cs, PIPE_TRANSFER_WRITE);
 506         memset(ptr, 0, t->filled_size->buf->size);
 507         rctx->ws->buffer_unmap(t->filled_size->buf);
 508
 509         return &t->b;
 510 }
 511
 512 void r600_so_target_destroy(struct pipe_context *ctx,
 513                             struct pipe_stream_output_target *target)
 514 {
 515         struct r600_so_target *t = (struct r600_so_target*)target;
 516         pipe_resource_reference(&t->b.buffer, NULL);
 517         pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
 518         FREE(t);
 519 }
 520
 521 void r600_set_so_targets(struct pipe_context *ctx,
 522                          unsigned num_targets,
 523                          struct pipe_stream_output_target **targets,
 524                          unsigned append_bitmask)
 525 {
 526         struct r600_context *rctx = (struct r600_context *)ctx;
 527         unsigned i;
 528
 529         /* Stop streamout. */
 530         if (rctx->num_so_targets) {
 531                 r600_context_streamout_end(rctx);
 532         }
 533
 534         /* Set the new targets. */
 535         for (i = 0; i < num_targets; i++) {
 536                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
 537         }
 538         for (; i < rctx->num_so_targets; i++) {
 539                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
 540         }
 541
 542         rctx->num_so_targets = num_targets;
 543         rctx->streamout_start = num_targets != 0;
 544         rctx->streamout_append_bitmask = append_bitmask;
 545 }
 546
 547 static void r600_vertex_buffer_update(struct r600_context *rctx)
 548 {
 549         struct pipe_context *ctx = &rctx->context;
 550         struct r600_pipe_state *rstate = &rctx->vs_user_data;
 551         struct r600_resource *rbuffer, *t_list_buffer;
 552         struct pipe_vertex_buffer *vertex_buffer;
 553         unsigned i, count, offset;
 554         uint32_t *ptr;
 555         uint64_t va;
 556
 557         r600_inval_vertex_cache(rctx);
 558
 559         if (rctx->vertex_elements->vbuffer_need_offset) {
 560                 /* one resource per vertex elements */
 561                 count = rctx->vertex_elements->count;
 562         } else {
 563                 /* bind vertex buffer once */
 564                 count = rctx->vbuf_mgr->nr_real_vertex_buffers;
 565         }
 566         assert(count <= 256 / 4);
 567
 568         t_list_buffer = (struct r600_resource*)
 569                 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM,
 570                                    PIPE_USAGE_IMMUTABLE, 4 * 4 * count);
 571         if (t_list_buffer == NULL)
 572                 return;
 573
 574         ptr = (uint32_t*)rctx->ws->buffer_map(t_list_buffer->buf,
 575                                               rctx->cs,
 576                                               PIPE_TRANSFER_WRITE);
 577
 578         for (i = 0 ; i < count; i++, ptr += 4) {
 579                 struct pipe_vertex_element *velem = &rctx->vertex_elements->elements[i];
 580                 const struct util_format_description *desc;
 581                 unsigned data_format, num_format;
 582                 int first_non_void;
 583
 584                 if (rctx->vertex_elements->vbuffer_need_offset) {
 585                         /* one resource per vertex elements */
 586                         unsigned vbuffer_index;
 587                         vbuffer_index = rctx->vertex_elements->elements[i].vertex_buffer_index;
 588                         vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[vbuffer_index];
 589                         rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 590                         offset = rctx->vertex_elements->vbuffer_offset[i];
 591                 } else {
 592                         /* bind vertex buffer once */
 593                         vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[i];
 594                         rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 595                         offset = 0;
 596                 }
 597                 if (vertex_buffer == NULL || rbuffer == NULL)
 598                         continue;
 599                 offset += vertex_buffer->buffer_offset;
 600
 601                 va = r600_resource_va(ctx->screen, (void*)rbuffer);
 602                 va += offset;
 603
 604                 desc = util_format_description(velem->src_format);
 605                 first_non_void = util_format_get_first_non_void_channel(velem->src_format);
 606                 data_format = si_translate_vertexformat(ctx->screen,
 607                                                         velem->src_format,
 608                                                         desc, first_non_void);
 609
 610                 switch (desc->channel[first_non_void].type) {
 611                 case UTIL_FORMAT_TYPE_FIXED:
 612                         num_format = V_008F0C_BUF_NUM_FORMAT_USCALED; /* XXX */
 613                         break;
 614                 case UTIL_FORMAT_TYPE_SIGNED:
 615                         num_format = V_008F0C_BUF_NUM_FORMAT_SNORM;
 616                         break;
 617                 case UTIL_FORMAT_TYPE_UNSIGNED:
 618                         num_format = V_008F0C_BUF_NUM_FORMAT_UNORM;
 619                         break;
 620                 case UTIL_FORMAT_TYPE_FLOAT:
 621                 default:
 622                         num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
 623                 }
 624
 625                 /* Fill in T# buffer resource description */
 626                 ptr[0] = va & 0xFFFFFFFF;
 627                 ptr[1] = ((va >> 32) & 0xFFFF) |
 628                          (vertex_buffer->stride & 0x3FFF) << 16;
 629                 ptr[2] = (vertex_buffer->buffer->width0 - offset) / vertex_buffer->stride;
 630                 /* XXX: Hardcoding RGBA */
 631                 ptr[3] = 4 | 5 << 3 | 6 << 6 | 7 << 9 |
 632                         num_format << 12 | data_format << 15;
 633
 634                 r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ);
 635         }
 636
 637         rstate->nregs = 0;
 638
 639         va = r600_resource_va(ctx->screen, (void*)t_list_buffer);
 640         r600_pipe_state_add_reg(rstate,
 641                                 R_00B130_SPI_SHADER_USER_DATA_VS_0,
 642                                 va, t_list_buffer, RADEON_USAGE_READ);
 643         r600_pipe_state_add_reg(rstate,
 644                                 R_00B134_SPI_SHADER_USER_DATA_VS_1,
 645                                 va >> 32,
 646                                 NULL, 0);
 647
 648         r600_context_pipe_state_set(rctx, rstate);
 649 }
 650
 651 static void si_update_derived_state(struct r600_context *rctx)
 652 {
 653         struct pipe_context * ctx = (struct pipe_context*)rctx;
 654
 655         if (!rctx->blitter->running) {
 656                 if (rctx->have_depth_fb || rctx->have_depth_texture)
 657                         r600_flush_depth_textures(rctx);
 658         }
 659
 660         if (rctx->shader_dirty) {
 661                 si_pipe_shader_destroy(&rctx->context, rctx->vs_shader);
 662         }
 663
 664         if (rctx->shader_dirty ||
 665             (rctx->ps_shader->shader.fs_write_all &&
 666              (rctx->ps_shader->shader.nr_cbufs != rctx->nr_cbufs)) ||
 667             (rctx->sprite_coord_enable &&
 668              (rctx->ps_shader->sprite_coord_enable != rctx->sprite_coord_enable))) {
 669                 si_pipe_shader_destroy(&rctx->context, rctx->ps_shader);
 670         }
 671
 672         if (rctx->alpha_ref_dirty) {
 673                 r600_update_alpha_ref(rctx);
 674         }
 675
 676         if (!rctx->vs_shader->bo) {
 677                 si_pipe_shader_vs(ctx, rctx->vs_shader);
 678
 679                 r600_context_pipe_state_set(rctx, &rctx->vs_shader->rstate);
 680         }
 681
 682         if (!rctx->ps_shader->bo) {
 683                 si_pipe_shader_ps(ctx, rctx->ps_shader);
 684
 685                 r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
 686         }
 687
 688         if (rctx->shader_dirty) {
 689                 si_update_spi_map(rctx);
 690                 rctx->shader_dirty = false;
 691         }
 692 }
 693
 694 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
 695 {
 696         struct r600_context *rctx = (struct r600_context *)ctx;
 697         struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
 698         struct pipe_draw_info info = *dinfo;
 699         struct r600_draw rdraw = {};
 700         struct pipe_index_buffer ib = {};
 701         unsigned prim, mask, ls_mask = 0;
 702         struct r600_block *dirty_block = NULL, *next_block = NULL;
 703         struct r600_atom *state = NULL, *next_state = NULL;
 704         int i;
 705
 706         if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
 707             (info.indexed && !rctx->vbuf_mgr->index_buffer.buffer) ||
 708             !r600_conv_pipe_prim(info.mode, &prim)) {
 709                 return;
 710         }
 711
 712         if (!rctx->ps_shader || !rctx->vs_shader)
 713                 return;
 714
 715         si_update_derived_state(rctx);
 716
 717         u_vbuf_draw_begin(rctx->vbuf_mgr, &info);
 718         r600_vertex_buffer_update(rctx);
 719
 720         rdraw.vgt_num_indices = info.count;
 721         rdraw.vgt_num_instances = info.instance_count;
 722
 723         if (info.indexed) {
 724                 /* Initialize the index buffer struct. */
 725                 pipe_resource_reference(&ib.buffer, rctx->vbuf_mgr->index_buffer.buffer);
 726                 ib.index_size = rctx->vbuf_mgr->index_buffer.index_size;
 727                 ib.offset = rctx->vbuf_mgr->index_buffer.offset + info.start * ib.index_size;
 728
 729                 /* Translate or upload, if needed. */
 730                 r600_translate_index_buffer(rctx, &ib, info.count);
 731
 732                 if (u_vbuf_resource(ib.buffer)->user_ptr) {
 733                         r600_upload_index_buffer(rctx, &ib, info.count);
 734                 }
 735
 736                 /* Initialize the r600_draw struct with index buffer info. */
 737                 if (ib.index_size == 4) {
 738                         rdraw.vgt_index_type = V_028A7C_VGT_INDEX_32 |
 739                                 (R600_BIG_ENDIAN ? V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
 740                 } else {
 741                         rdraw.vgt_index_type = V_028A7C_VGT_INDEX_16 |
 742                                 (R600_BIG_ENDIAN ? V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
 743                 }
 744                 rdraw.indices = (struct r600_resource*)ib.buffer;
 745                 rdraw.indices_bo_offset = ib.offset;
 746                 rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_DMA;
 747         } else {
 748                 info.index_bias = info.start;
 749                 rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
 750                 if (info.count_from_stream_output) {
 751                         rdraw.vgt_draw_initiator |= S_0287F0_USE_OPAQUE(1);
 752
 753                         r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info.count_from_stream_output);
 754                 }
 755         }
 756
 757         rctx->vs_shader_so_strides = rctx->vs_shader->so_strides;
 758
 759         mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
 760
 761         if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
 762                 rctx->vgt.id = R600_PIPE_STATE_VGT;
 763                 rctx->vgt.nregs = 0;
 764                 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, NULL, 0);
 765                 r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, NULL, 0);
 766                 r600_pipe_state_add_reg(&rctx->vgt, R_028400_VGT_MAX_VTX_INDX, ~0, NULL, 0);
 767                 r600_pipe_state_add_reg(&rctx->vgt, R_028404_VGT_MIN_VTX_INDX, 0, NULL, 0);
 768                 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias, NULL, 0);
 769                 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index, NULL, 0);
 770                 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart, NULL, 0);
 771 #if 0
 772                 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, NULL, 0);
 773                 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance, NULL, 0);
 774 #endif
 775                 r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0, NULL, 0);
 776                 r600_pipe_state_add_reg(&rctx->vgt, R_028814_PA_SU_SC_MODE_CNTL, 0, NULL, 0);
 777                 r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0, NULL, 0);
 778                 r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0x0, NULL, 0);
 779         }
 780
 781         rctx->vgt.nregs = 0;
 782         r600_pipe_state_mod_reg(&rctx->vgt, prim);
 783         r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_target_mask & mask);
 784         r600_pipe_state_mod_reg(&rctx->vgt, ~0);
 785         r600_pipe_state_mod_reg(&rctx->vgt, 0);
 786         r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
 787         r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
 788         r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
 789 #if 0
 790         r600_pipe_state_mod_reg(&rctx->vgt, 0);
 791         r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
 792 #endif
 793
 794         if (prim == V_008958_DI_PT_LINELIST)
 795                 ls_mask = 1;
 796         else if (prim == V_008958_DI_PT_LINESTRIP)
 797                 ls_mask = 2;
 798         r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
 799
 800         if (info.mode == PIPE_PRIM_QUADS || info.mode == PIPE_PRIM_QUAD_STRIP || info.mode == PIPE_PRIM_POLYGON) {
 801                 r600_pipe_state_mod_reg(&rctx->vgt, S_028814_PROVOKING_VTX_LAST(1) | rctx->pa_su_sc_mode_cntl);
 802         } else {
 803                 r600_pipe_state_mod_reg(&rctx->vgt, rctx->pa_su_sc_mode_cntl);
 804         }
 805         r600_pipe_state_mod_reg(&rctx->vgt,
 806                                 rctx->pa_cl_vs_out_cntl /*|
 807                                 (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->shader.clip_dist_write)*/);
 808         r600_pipe_state_mod_reg(&rctx->vgt,
 809                                 rctx->pa_cl_clip_cntl /*|
 810                                 (rctx->vs_shader->shader.clip_dist_write ||
 811                                  rctx->vs_shader->shader.vs_prohibit_ucps ?
 812                                  0 : rctx->rasterizer->clip_plane_enable & 0x3F)*/);
 813
 814         r600_context_pipe_state_set(rctx, &rctx->vgt);
 815
 816         rdraw.db_render_override = dsa->db_render_override;
 817         rdraw.db_render_control = dsa->db_render_control;
 818
 819         /* Emit states. */
 820         r600_need_cs_space(rctx, 0, TRUE);
 821
 822         LIST_FOR_EACH_ENTRY_SAFE(state, next_state, &rctx->dirty_states, head) {
 823                 r600_emit_atom(rctx, state);
 824         }
 825         LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
 826                 r600_context_block_emit_dirty(rctx, dirty_block);
 827         }
 828         rctx->pm4_dirty_cdwords = 0;
 829
 830         /* Enable stream out if needed. */
 831         if (rctx->streamout_start) {
 832                 r600_context_streamout_begin(rctx);
 833                 rctx->streamout_start = FALSE;
 834         }
 835
 836         for (i = 0; i < NUM_TEX_UNITS; i++) {
 837                 if (rctx->ps_samplers.views[i])
 838                         r600_context_bo_reloc(rctx,
 839                                               (struct r600_resource*)rctx->ps_samplers.views[i]->base.texture,
 840                                               RADEON_USAGE_READ);
 841         }
 842
 843         if (rctx->chip_class >= CAYMAN) {
 844                 evergreen_context_draw(rctx, &rdraw);
 845         }
 846
 847         rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING;
 848
 849         if (rctx->framebuffer.zsbuf)
 850         {
 851                 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture;
 852                 ((struct r600_resource_texture *)tex)->dirty_db = TRUE;
 853         }
 854
 855         pipe_resource_reference(&ib.buffer, NULL);
 856         u_vbuf_draw_end(rctx->vbuf_mgr);
 857 }
 858
 859 void _r600_pipe_state_add_reg(struct r600_context *ctx,
 860                               struct r600_pipe_state *state,
 861                               uint32_t offset, uint32_t value,
 862                               uint32_t range_id, uint32_t block_id,
 863                               struct r600_resource *bo,
 864                               enum radeon_bo_usage usage)
 865 {
 866         struct r600_range *range;
 867         struct r600_block *block;
 868
 869         if (bo) assert(usage);
 870
 871         range = &ctx->range[range_id];
 872         block = range->blocks[block_id];
 873         state->regs[state->nregs].block = block;
 874         state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
 875
 876         state->regs[state->nregs].value = value;
 877         state->regs[state->nregs].bo = bo;
 878         state->regs[state->nregs].bo_usage = usage;
 879
 880         state->nregs++;
 881         assert(state->nregs < R600_BLOCK_MAX_REG);
 882 }
 883
 884 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
 885                                      uint32_t offset, uint32_t value,
 886                                      struct r600_resource *bo,
 887                                      enum radeon_bo_usage usage)
 888 {
 889         if (bo) assert(usage);
 890
 891         state->regs[state->nregs].id = offset;
 892         state->regs[state->nregs].block = NULL;
 893         state->regs[state->nregs].value = value;
 894         state->regs[state->nregs].bo = bo;
 895         state->regs[state->nregs].bo_usage = usage;
 896
 897         state->nregs++;
 898         assert(state->nregs < R600_BLOCK_MAX_REG);
 899 }