src/gallium/drivers/radeonsi/r600_texture.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  *      Corbin Simpson
  26  */
  27 #include <errno.h>
  28 #include "pipe/p_screen.h"
  29 #include "util/u_format.h"
  30 #include "util/u_format_s3tc.h"
  31 #include "util/u_math.h"
  32 #include "util/u_inlines.h"
  33 #include "util/u_memory.h"
  34 #include "pipebuffer/pb_buffer.h"
  35 #include "radeonsi_pipe.h"
  36 #include "r600_resource.h"
  37 #include "sid.h"
  38
  39 /* Copy from a full GPU texture to a transfer's staging one. */
  40 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  41 {
  42         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  43         struct pipe_resource *texture = transfer->resource;
  44
  45         ctx->resource_copy_region(ctx, rtransfer->staging_texture,
  46                                 0, 0, 0, 0, texture, transfer->level,
  47                                 &transfer->box);
  48 }
  49
  50
  51 /* Copy from a transfer's staging texture to a full GPU one. */
  52 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  53 {
  54         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  55         struct pipe_resource *texture = transfer->resource;
  56         struct pipe_box sbox;
  57
  58         sbox.x = sbox.y = sbox.z = 0;
  59         sbox.width = transfer->box.width;
  60         sbox.height = transfer->box.height;
  61         /* XXX that might be wrong */
  62         sbox.depth = 1;
  63         ctx->resource_copy_region(ctx, texture, transfer->level,
  64                                   transfer->box.x, transfer->box.y, transfer->box.z,
  65                                   rtransfer->staging_texture,
  66                                   0, &sbox);
  67 }
  68
  69 static unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
  70                                         unsigned level, unsigned layer)
  71 {
  72         return rtex->surface.level[level].offset +
  73                layer * rtex->surface.level[level].slice_size;
  74 }
  75
  76 static int r600_init_surface(struct radeon_surface *surface,
  77                              const struct pipe_resource *ptex,
  78                              unsigned array_mode)
  79 {
  80         surface->npix_x = ptex->width0;
  81         surface->npix_y = ptex->height0;
  82         surface->npix_z = ptex->depth0;
  83         surface->blk_w = util_format_get_blockwidth(ptex->format);
  84         surface->blk_h = util_format_get_blockheight(ptex->format);
  85         surface->blk_d = 1;
  86         surface->array_size = 1;
  87         surface->last_level = ptex->last_level;
  88         surface->bpe = util_format_get_blocksize(ptex->format);
  89         /* align byte per element on dword */
  90         if (surface->bpe == 3) {
  91                 surface->bpe = 4;
  92         }
  93         surface->nsamples = 1;
  94         surface->flags = 0;
  95         switch (array_mode) {
  96         case V_009910_ARRAY_1D_TILED_THIN1:
  97                 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
  98                 break;
  99         case V_009910_ARRAY_2D_TILED_THIN1:
 100                 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
 101                 break;
 102         case V_009910_ARRAY_LINEAR_ALIGNED:
 103                 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
 104                 break;
 105         case V_009910_ARRAY_LINEAR_GENERAL:
 106         default:
 107                 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
 108                 break;
 109         }
 110         switch (ptex->target) {
 111         case PIPE_TEXTURE_1D:
 112                 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
 113                 break;
 114         case PIPE_TEXTURE_RECT:
 115         case PIPE_TEXTURE_2D:
 116                 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
 117                 break;
 118         case PIPE_TEXTURE_3D:
 119                 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
 120                 break;
 121         case PIPE_TEXTURE_1D_ARRAY:
 122                 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
 123                 surface->array_size = ptex->array_size;
 124                 break;
 125         case PIPE_TEXTURE_2D_ARRAY:
 126                 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
 127                 surface->array_size = ptex->array_size;
 128                 break;
 129         case PIPE_TEXTURE_CUBE:
 130                 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
 131                 break;
 132         case PIPE_BUFFER:
 133         default:
 134                 return -EINVAL;
 135         }
 136         if (ptex->bind & PIPE_BIND_SCANOUT) {
 137                 surface->flags |= RADEON_SURF_SCANOUT;
 138         }
 139         if (util_format_is_depth_and_stencil(ptex->format)) {
 140                 surface->flags |= RADEON_SURF_ZBUFFER;
 141                 surface->flags |= RADEON_SURF_SBUFFER;
 142         }
 143
 144         return 0;
 145 }
 146
 147 static int r600_setup_surface(struct pipe_screen *screen,
 148                               struct r600_resource_texture *rtex,
 149                               unsigned array_mode,
 150                               unsigned pitch_in_bytes_override)
 151 {
 152         struct r600_screen *rscreen = (struct r600_screen*)screen;
 153         int r;
 154
 155         if (util_format_is_depth_or_stencil(rtex->real_format)) {
 156                 rtex->surface.flags |= RADEON_SURF_ZBUFFER;
 157                 rtex->surface.flags |= RADEON_SURF_SBUFFER;
 158         }
 159
 160         r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
 161         if (r) {
 162                 return r;
 163         }
 164         if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
 165                 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
 166                  * for those
 167                  */
 168                 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
 169                 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
 170                 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
 171                 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
 172                         rtex->surface.stencil_offset = rtex->surface.level[0].slice_size;
 173                 }
 174         }
 175         return 0;
 176 }
 177
 178 /* Figure out whether u_blitter will fallback to a transfer operation.
 179  * If so, don't use a staging resource.
 180  */
 181 static boolean permit_hardware_blit(struct pipe_screen *screen,
 182                                         const struct pipe_resource *res)
 183 {
 184         unsigned bind;
 185
 186         if (util_format_is_depth_or_stencil(res->format))
 187                 bind = PIPE_BIND_DEPTH_STENCIL;
 188         else
 189                 bind = PIPE_BIND_RENDER_TARGET;
 190
 191         /* hackaround for S3TC */
 192         if (util_format_is_compressed(res->format))
 193                 return TRUE;
 194
 195         if (!screen->is_format_supported(screen,
 196                                 res->format,
 197                                 res->target,
 198                                 res->nr_samples,
 199                                 bind))
 200                 return FALSE;
 201
 202         if (!screen->is_format_supported(screen,
 203                                 res->format,
 204                                 res->target,
 205                                 res->nr_samples,
 206                                 PIPE_BIND_SAMPLER_VIEW))
 207                 return FALSE;
 208
 209         switch (res->usage) {
 210         case PIPE_USAGE_STREAM:
 211         case PIPE_USAGE_STAGING:
 212                 return FALSE;
 213
 214         default:
 215                 return TRUE;
 216         }
 217 }
 218
 219 static boolean r600_texture_get_handle(struct pipe_screen* screen,
 220                                         struct pipe_resource *ptex,
 221                                         struct winsys_handle *whandle)
 222 {
 223         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 224         struct si_resource *resource = &rtex->resource;
 225         struct radeon_surface *surface = &rtex->surface;
 226         struct r600_screen *rscreen = (struct r600_screen*)screen;
 227
 228         rscreen->ws->buffer_set_tiling(resource->buf,
 229                                        NULL,
 230                                        surface->level[0].mode >= RADEON_SURF_MODE_1D ?
 231                                        RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
 232                                        surface->level[0].mode >= RADEON_SURF_MODE_2D ?
 233                                        RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
 234                                        surface->bankw, surface->bankh,
 235                                        surface->tile_split,
 236                                        surface->stencil_tile_split,
 237                                        surface->mtilea,
 238                                        surface->level[0].pitch_bytes);
 239
 240         return rscreen->ws->buffer_get_handle(resource->buf,
 241                                               surface->level[0].pitch_bytes, whandle);
 242 }
 243
 244 static void r600_texture_destroy(struct pipe_screen *screen,
 245                                  struct pipe_resource *ptex)
 246 {
 247         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 248         struct si_resource *resource = &rtex->resource;
 249
 250         if (rtex->flushed_depth_texture)
 251                 si_resource_reference((struct si_resource **)&rtex->flushed_depth_texture, NULL);
 252
 253         pb_reference(&resource->buf, NULL);
 254         FREE(rtex);
 255 }
 256
 257 static void *si_texture_transfer_map(struct pipe_context *ctx,
 258                                      struct pipe_resource *texture,
 259                                      unsigned level,
 260                                      unsigned usage,
 261                                      const struct pipe_box *box,
 262                                      struct pipe_transfer **ptransfer)
 263 {
 264         struct r600_context *rctx = (struct r600_context *)ctx;
 265         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 266         struct pipe_resource resource;
 267         struct r600_transfer *trans;
 268         int r;
 269         boolean use_staging_texture = FALSE;
 270         struct radeon_winsys_cs_handle *buf;
 271         enum pipe_format format = texture->format;
 272         unsigned offset = 0;
 273         char *map;
 274
 275         /* We cannot map a tiled texture directly because the data is
 276          * in a different order, therefore we do detiling using a blit.
 277          *
 278          * Also, use a temporary in GTT memory for read transfers, as
 279          * the CPU is much happier reading out of cached system memory
 280          * than uncached VRAM.
 281          */
 282         if (rtex->surface.level[level].mode != RADEON_SURF_MODE_LINEAR_ALIGNED &&
 283             rtex->surface.level[level].mode != RADEON_SURF_MODE_LINEAR)
 284                 use_staging_texture = TRUE;
 285
 286         /* XXX: Use a staging texture for uploads if the underlying BO
 287          * is busy.  No interface for checking that currently? so do
 288          * it eagerly whenever the transfer doesn't require a readback
 289          * and might block.
 290          */
 291         if ((usage & PIPE_TRANSFER_WRITE) &&
 292                         !(usage & (PIPE_TRANSFER_READ |
 293                                         PIPE_TRANSFER_DONTBLOCK |
 294                                         PIPE_TRANSFER_UNSYNCHRONIZED)))
 295                 use_staging_texture = TRUE;
 296
 297         if (!permit_hardware_blit(ctx->screen, texture) ||
 298                 (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
 299                 use_staging_texture = FALSE;
 300
 301         if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY))
 302                 return NULL;
 303
 304         trans = CALLOC_STRUCT(r600_transfer);
 305         if (trans == NULL)
 306                 return NULL;
 307         pipe_resource_reference(&trans->transfer.resource, texture);
 308         trans->transfer.level = level;
 309         trans->transfer.usage = usage;
 310         trans->transfer.box = *box;
 311         if (rtex->depth) {
 312                 /* XXX: only readback the rectangle which is being mapped?
 313                 */
 314                 /* XXX: when discard is true, no need to read back from depth texture
 315                 */
 316                 r = r600_texture_depth_flush(ctx, texture, FALSE);
 317                 if (r < 0) {
 318                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 319                         pipe_resource_reference(&trans->transfer.resource, NULL);
 320                         FREE(trans);
 321                         return NULL;
 322                 }
 323                 trans->transfer.stride = rtex->flushed_depth_texture->surface.level[level].pitch_bytes;
 324                 trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z);
 325         } else if (use_staging_texture) {
 326                 resource.target = PIPE_TEXTURE_2D;
 327                 resource.format = texture->format;
 328                 resource.width0 = box->width;
 329                 resource.height0 = box->height;
 330                 resource.depth0 = 1;
 331                 resource.array_size = 1;
 332                 resource.last_level = 0;
 333                 resource.nr_samples = 0;
 334                 resource.usage = PIPE_USAGE_STAGING;
 335                 resource.bind = 0;
 336                 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 337                 /* For texture reading, the temporary (detiled) texture is used as
 338                  * a render target when blitting from a tiled texture. */
 339                 if (usage & PIPE_TRANSFER_READ) {
 340                         resource.bind |= PIPE_BIND_RENDER_TARGET;
 341                 }
 342                 /* For texture writing, the temporary texture is used as a sampler
 343                  * when blitting into a tiled texture. */
 344                 if (usage & PIPE_TRANSFER_WRITE) {
 345                         resource.bind |= PIPE_BIND_SAMPLER_VIEW;
 346                 }
 347                 /* Create the temporary texture. */
 348                 trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource);
 349                 if (trans->staging_texture == NULL) {
 350                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 351                         pipe_resource_reference(&trans->transfer.resource, NULL);
 352                         FREE(trans);
 353                         return NULL;
 354                 }
 355
 356                 trans->transfer.stride = ((struct r600_resource_texture *)trans->staging_texture)
 357                                         ->surface.level[0].pitch_bytes;
 358                 if (usage & PIPE_TRANSFER_READ) {
 359                         r600_copy_to_staging_texture(ctx, trans);
 360                         /* Always referenced in the blit. */
 361                         radeonsi_flush(ctx, NULL, 0);
 362                 }
 363         } else {
 364                 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
 365                 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
 366                 trans->offset = r600_texture_get_offset(rtex, level, box->z);
 367         }
 368
 369         if (trans->staging_texture) {
 370                 buf = si_resource(trans->staging_texture)->cs_buf;
 371         } else {
 372                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 373
 374                 if (rtex->flushed_depth_texture)
 375                         buf = rtex->flushed_depth_texture->resource.cs_buf;
 376                 else
 377                         buf = si_resource(texture)->cs_buf;
 378
 379                 offset = trans->offset +
 380                         box->y / util_format_get_blockheight(format) * trans->transfer.stride +
 381                         box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
 382         }
 383
 384         if (!(map = rctx->ws->buffer_map(buf, rctx->cs, usage))) {
 385                 pipe_resource_reference(&trans->staging_texture, NULL);
 386                 pipe_resource_reference(&trans->transfer.resource, NULL);
 387                 FREE(trans);
 388                 return NULL;
 389         }
 390
 391         *ptransfer = &trans->transfer;
 392         return map + offset;
 393 }
 394
 395 static void si_texture_transfer_unmap(struct pipe_context *ctx,
 396                                       struct pipe_transfer* transfer)
 397 {
 398         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 399         struct r600_context *rctx = (struct r600_context*)ctx;
 400         struct radeon_winsys_cs_handle *buf;
 401         struct pipe_resource *texture = transfer->resource;
 402         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 403
 404         if (rtransfer->staging_texture) {
 405                 buf = si_resource(rtransfer->staging_texture)->cs_buf;
 406         } else {
 407                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 408
 409                 if (rtex->flushed_depth_texture) {
 410                         buf = rtex->flushed_depth_texture->resource.cs_buf;
 411                 } else {
 412                         buf = si_resource(transfer->resource)->cs_buf;
 413                 }
 414         }
 415         rctx->ws->buffer_unmap(buf);
 416
 417         if (rtransfer->staging_texture) {
 418                 if (transfer->usage & PIPE_TRANSFER_WRITE) {
 419                         r600_copy_from_staging_texture(ctx, rtransfer);
 420                 }
 421                 pipe_resource_reference(&rtransfer->staging_texture, NULL);
 422         }
 423
 424         if (rtex->depth && !rtex->is_flushing_texture) {
 425                 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture)
 426                         r600_blit_push_depth(ctx, rtex);
 427         }
 428
 429         pipe_resource_reference(&transfer->resource, NULL);
 430         FREE(transfer);
 431 }
 432
 433 static const struct u_resource_vtbl r600_texture_vtbl =
 434 {
 435         r600_texture_get_handle,        /* get_handle */
 436         r600_texture_destroy,           /* resource_destroy */
 437         si_texture_transfer_map,        /* transfer_map */
 438         u_default_transfer_flush_region,/* transfer_flush_region */
 439         si_texture_transfer_unmap,      /* transfer_unmap */
 440         NULL    /* transfer_inline_write */
 441 };
 442
 443 static struct r600_resource_texture *
 444 r600_texture_create_object(struct pipe_screen *screen,
 445                            const struct pipe_resource *base,
 446                            unsigned array_mode,
 447                            unsigned pitch_in_bytes_override,
 448                            unsigned max_buffer_size,
 449                            struct pb_buffer *buf,
 450                            boolean alloc_bo,
 451                            struct radeon_surface *surface)
 452 {
 453         struct r600_resource_texture *rtex;
 454         struct si_resource *resource;
 455         struct r600_screen *rscreen = (struct r600_screen*)screen;
 456         int r;
 457
 458         rtex = CALLOC_STRUCT(r600_resource_texture);
 459         if (rtex == NULL)
 460                 return NULL;
 461
 462         resource = &rtex->resource;
 463         resource->b.b = *base;
 464         resource->b.vtbl = &r600_texture_vtbl;
 465         pipe_reference_init(&resource->b.b.reference, 1);
 466         resource->b.b.screen = screen;
 467         rtex->pitch_override = pitch_in_bytes_override;
 468         rtex->real_format = base->format;
 469
 470         /* only mark depth textures the HW can hit as depth textures */
 471         if (util_format_is_depth_or_stencil(rtex->real_format) && permit_hardware_blit(screen, base))
 472                 rtex->depth = 1;
 473
 474         rtex->surface = *surface;
 475         r = r600_setup_surface(screen, rtex, array_mode, pitch_in_bytes_override);
 476         if (r) {
 477                 FREE(rtex);
 478                 return NULL;
 479         }
 480
 481         /* Now create the backing buffer. */
 482         if (!buf && alloc_bo) {
 483                 unsigned base_align = rtex->surface.bo_alignment;
 484                 unsigned size = rtex->surface.bo_size;
 485
 486                 base_align = rtex->surface.bo_alignment;
 487                 if (!si_init_resource(rscreen, resource, size, base_align, base->bind, base->usage)) {
 488                         FREE(rtex);
 489                         return NULL;
 490                 }
 491         } else if (buf) {
 492                 resource->buf = buf;
 493                 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
 494                 resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM;
 495         }
 496
 497         return rtex;
 498 }
 499
 500 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
 501                                         const struct pipe_resource *templ)
 502 {
 503         struct r600_screen *rscreen = (struct r600_screen*)screen;
 504         struct radeon_surface surface;
 505         unsigned array_mode = V_009910_ARRAY_LINEAR_ALIGNED;
 506         int r;
 507
 508 #if 0
 509         if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
 510             !(templ->bind & PIPE_BIND_SCANOUT)) {
 511                 if (permit_hardware_blit(screen, templ)) {
 512                         array_mode = V_009910_ARRAY_2D_TILED_THIN1;
 513                 }
 514         }
 515 #endif
 516
 517         r = r600_init_surface(&surface, templ, array_mode);
 518         if (r) {
 519                 return NULL;
 520         }
 521         r = rscreen->ws->surface_best(rscreen->ws, &surface);
 522         if (r) {
 523                 return NULL;
 524         }
 525         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 526                                                                   0, 0, NULL, TRUE, &surface);
 527 }
 528
 529 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
 530                                                 struct pipe_resource *texture,
 531                                                 const struct pipe_surface *surf_tmpl)
 532 {
 533         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 534         struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
 535         unsigned level = surf_tmpl->u.tex.level;
 536
 537         assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
 538         if (surface == NULL)
 539                 return NULL;
 540         /* XXX no offset */
 541 /*      offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
 542         pipe_reference_init(&surface->base.reference, 1);
 543         pipe_resource_reference(&surface->base.texture, texture);
 544         surface->base.context = pipe;
 545         surface->base.format = surf_tmpl->format;
 546         surface->base.width = rtex->surface.level[level].npix_x;
 547         surface->base.height = rtex->surface.level[level].npix_y;
 548         surface->base.usage = surf_tmpl->usage;
 549         surface->base.texture = texture;
 550         surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
 551         surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
 552         surface->base.u.tex.level = level;
 553
 554         return &surface->base;
 555 }
 556
 557 static void r600_surface_destroy(struct pipe_context *pipe,
 558                                  struct pipe_surface *surface)
 559 {
 560         pipe_resource_reference(&surface->texture, NULL);
 561         FREE(surface);
 562 }
 563
 564 struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen,
 565                                              const struct pipe_resource *templ,
 566                                              struct winsys_handle *whandle)
 567 {
 568         struct r600_screen *rscreen = (struct r600_screen*)screen;
 569         struct pb_buffer *buf = NULL;
 570         unsigned stride = 0;
 571         unsigned array_mode = V_009910_ARRAY_LINEAR_ALIGNED;
 572         enum radeon_bo_layout micro, macro;
 573         struct radeon_surface surface;
 574         int r;
 575
 576         /* Support only 2D textures without mipmaps */
 577         if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
 578               templ->depth0 != 1 || templ->last_level != 0)
 579                 return NULL;
 580
 581         buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
 582         if (!buf)
 583                 return NULL;
 584
 585         rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
 586                                        &surface.bankw, &surface.bankh,
 587                                        &surface.tile_split,
 588                                        &surface.stencil_tile_split,
 589                                        &surface.mtilea);
 590
 591         if (macro == RADEON_LAYOUT_TILED)
 592                 array_mode = V_009910_ARRAY_2D_TILED_THIN1;
 593         else if (micro == RADEON_LAYOUT_TILED)
 594                 array_mode = V_009910_ARRAY_1D_TILED_THIN1;
 595         else
 596                 array_mode = V_009910_ARRAY_LINEAR_ALIGNED;
 597
 598         r = r600_init_surface(&surface, templ, array_mode);
 599         if (r) {
 600                 return NULL;
 601         }
 602         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 603                                                                   stride, 0, buf, FALSE, &surface);
 604 }
 605
 606 int r600_texture_depth_flush(struct pipe_context *ctx,
 607                              struct pipe_resource *texture, boolean just_create)
 608 {
 609         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 610         struct pipe_resource resource;
 611
 612         if (rtex->flushed_depth_texture)
 613                 goto out;
 614
 615         resource.target = texture->target;
 616         resource.format = texture->format;
 617         resource.width0 = texture->width0;
 618         resource.height0 = texture->height0;
 619         resource.depth0 = texture->depth0;
 620         resource.array_size = texture->array_size;
 621         resource.last_level = texture->last_level;
 622         resource.nr_samples = texture->nr_samples;
 623         resource.usage = PIPE_USAGE_DYNAMIC;
 624         resource.bind = texture->bind | PIPE_BIND_DEPTH_STENCIL;
 625         resource.flags = R600_RESOURCE_FLAG_TRANSFER | texture->flags;
 626
 627         rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
 628         if (rtex->flushed_depth_texture == NULL) {
 629                 R600_ERR("failed to create temporary texture to hold untiled copy\n");
 630                 return -ENOMEM;
 631         }
 632
 633         ((struct r600_resource_texture *)rtex->flushed_depth_texture)->is_flushing_texture = TRUE;
 634 out:
 635         if (just_create)
 636                 return 0;
 637
 638         /* XXX: only do this if the depth texture has actually changed:
 639          */
 640         si_blit_uncompress_depth(ctx, rtex);
 641         return 0;
 642 }
 643
 644 void si_init_surface_functions(struct r600_context *r600)
 645 {
 646         r600->context.create_surface = r600_create_surface;
 647         r600->context.surface_destroy = r600_surface_destroy;
 648 }