2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "pipe/p_screen.h"
29 #include "util/u_format.h"
30 #include "util/u_format_s3tc.h"
31 #include "util/u_math.h"
32 #include "util/u_inlines.h"
33 #include "util/u_memory.h"
34 #include "pipebuffer/pb_buffer.h"
35 #include "radeonsi_pipe.h"
36 #include "r600_resource.h"
39 /* Copy from a full GPU texture to a transfer's staging one. */
40 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
42 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
43 struct pipe_resource
*texture
= transfer
->resource
;
45 ctx
->resource_copy_region(ctx
, rtransfer
->staging_texture
,
46 0, 0, 0, 0, texture
, transfer
->level
,
51 /* Copy from a transfer's staging texture to a full GPU one. */
52 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
54 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
55 struct pipe_resource
*texture
= transfer
->resource
;
58 sbox
.x
= sbox
.y
= sbox
.z
= 0;
59 sbox
.width
= transfer
->box
.width
;
60 sbox
.height
= transfer
->box
.height
;
61 /* XXX that might be wrong */
63 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
64 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
65 rtransfer
->staging_texture
,
69 static unsigned r600_texture_get_offset(struct r600_resource_texture
*rtex
,
70 unsigned level
, unsigned layer
)
72 return rtex
->surface
.level
[level
].offset
+
73 layer
* rtex
->surface
.level
[level
].slice_size
;
76 static int r600_init_surface(struct radeon_surface
*surface
,
77 const struct pipe_resource
*ptex
,
80 surface
->npix_x
= ptex
->width0
;
81 surface
->npix_y
= ptex
->height0
;
82 surface
->npix_z
= ptex
->depth0
;
83 surface
->blk_w
= util_format_get_blockwidth(ptex
->format
);
84 surface
->blk_h
= util_format_get_blockheight(ptex
->format
);
86 surface
->array_size
= 1;
87 surface
->last_level
= ptex
->last_level
;
88 surface
->bpe
= util_format_get_blocksize(ptex
->format
);
89 /* align byte per element on dword */
90 if (surface
->bpe
== 3) {
93 surface
->nsamples
= 1;
96 case V_009910_ARRAY_1D_TILED_THIN1
:
97 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_1D
, MODE
);
99 case V_009910_ARRAY_2D_TILED_THIN1
:
100 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
102 case V_009910_ARRAY_LINEAR_ALIGNED
:
103 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED
, MODE
);
105 case V_009910_ARRAY_LINEAR_GENERAL
:
107 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR
, MODE
);
110 switch (ptex
->target
) {
111 case PIPE_TEXTURE_1D
:
112 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
114 case PIPE_TEXTURE_RECT
:
115 case PIPE_TEXTURE_2D
:
116 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
118 case PIPE_TEXTURE_3D
:
119 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
121 case PIPE_TEXTURE_1D_ARRAY
:
122 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
123 surface
->array_size
= ptex
->array_size
;
125 case PIPE_TEXTURE_2D_ARRAY
:
126 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
127 surface
->array_size
= ptex
->array_size
;
129 case PIPE_TEXTURE_CUBE
:
130 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP
, TYPE
);
136 if (ptex
->bind
& PIPE_BIND_SCANOUT
) {
137 surface
->flags
|= RADEON_SURF_SCANOUT
;
139 if (util_format_is_depth_and_stencil(ptex
->format
)) {
140 surface
->flags
|= RADEON_SURF_ZBUFFER
;
141 surface
->flags
|= RADEON_SURF_SBUFFER
;
147 static int r600_setup_surface(struct pipe_screen
*screen
,
148 struct r600_resource_texture
*rtex
,
150 unsigned pitch_in_bytes_override
)
152 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
155 if (util_format_is_depth_or_stencil(rtex
->real_format
)) {
156 rtex
->surface
.flags
|= RADEON_SURF_ZBUFFER
;
157 rtex
->surface
.flags
|= RADEON_SURF_SBUFFER
;
160 r
= rscreen
->ws
->surface_init(rscreen
->ws
, &rtex
->surface
);
164 if (pitch_in_bytes_override
&& pitch_in_bytes_override
!= rtex
->surface
.level
[0].pitch_bytes
) {
165 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
168 rtex
->surface
.level
[0].nblk_x
= pitch_in_bytes_override
/ rtex
->surface
.bpe
;
169 rtex
->surface
.level
[0].pitch_bytes
= pitch_in_bytes_override
;
170 rtex
->surface
.level
[0].slice_size
= pitch_in_bytes_override
* rtex
->surface
.level
[0].nblk_y
;
171 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
172 rtex
->surface
.stencil_offset
= rtex
->surface
.level
[0].slice_size
;
178 /* Figure out whether u_blitter will fallback to a transfer operation.
179 * If so, don't use a staging resource.
181 static boolean
permit_hardware_blit(struct pipe_screen
*screen
,
182 const struct pipe_resource
*res
)
186 if (util_format_is_depth_or_stencil(res
->format
))
187 bind
= PIPE_BIND_DEPTH_STENCIL
;
189 bind
= PIPE_BIND_RENDER_TARGET
;
191 /* hackaround for S3TC */
192 if (util_format_is_compressed(res
->format
))
195 if (!screen
->is_format_supported(screen
,
202 if (!screen
->is_format_supported(screen
,
206 PIPE_BIND_SAMPLER_VIEW
))
209 switch (res
->usage
) {
210 case PIPE_USAGE_STREAM
:
211 case PIPE_USAGE_STAGING
:
219 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
220 struct pipe_resource
*ptex
,
221 struct winsys_handle
*whandle
)
223 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)ptex
;
224 struct si_resource
*resource
= &rtex
->resource
;
225 struct radeon_surface
*surface
= &rtex
->surface
;
226 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
228 rscreen
->ws
->buffer_set_tiling(resource
->buf
,
230 surface
->level
[0].mode
>= RADEON_SURF_MODE_1D
?
231 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
,
232 surface
->level
[0].mode
>= RADEON_SURF_MODE_2D
?
233 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
,
234 surface
->bankw
, surface
->bankh
,
236 surface
->stencil_tile_split
,
238 surface
->level
[0].pitch_bytes
);
240 return rscreen
->ws
->buffer_get_handle(resource
->buf
,
241 surface
->level
[0].pitch_bytes
, whandle
);
244 static void r600_texture_destroy(struct pipe_screen
*screen
,
245 struct pipe_resource
*ptex
)
247 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)ptex
;
248 struct si_resource
*resource
= &rtex
->resource
;
250 if (rtex
->flushed_depth_texture
)
251 si_resource_reference((struct si_resource
**)&rtex
->flushed_depth_texture
, NULL
);
253 pb_reference(&resource
->buf
, NULL
);
257 static void *si_texture_transfer_map(struct pipe_context
*ctx
,
258 struct pipe_resource
*texture
,
261 const struct pipe_box
*box
,
262 struct pipe_transfer
**ptransfer
)
264 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
265 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
266 struct pipe_resource resource
;
267 struct r600_transfer
*trans
;
269 boolean use_staging_texture
= FALSE
;
270 struct radeon_winsys_cs_handle
*buf
;
271 enum pipe_format format
= texture
->format
;
275 /* We cannot map a tiled texture directly because the data is
276 * in a different order, therefore we do detiling using a blit.
278 * Also, use a temporary in GTT memory for read transfers, as
279 * the CPU is much happier reading out of cached system memory
280 * than uncached VRAM.
282 if (rtex
->surface
.level
[level
].mode
!= RADEON_SURF_MODE_LINEAR_ALIGNED
&&
283 rtex
->surface
.level
[level
].mode
!= RADEON_SURF_MODE_LINEAR
)
284 use_staging_texture
= TRUE
;
286 /* XXX: Use a staging texture for uploads if the underlying BO
287 * is busy. No interface for checking that currently? so do
288 * it eagerly whenever the transfer doesn't require a readback
291 if ((usage
& PIPE_TRANSFER_WRITE
) &&
292 !(usage
& (PIPE_TRANSFER_READ
|
293 PIPE_TRANSFER_DONTBLOCK
|
294 PIPE_TRANSFER_UNSYNCHRONIZED
)))
295 use_staging_texture
= TRUE
;
297 if (!permit_hardware_blit(ctx
->screen
, texture
) ||
298 (texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
))
299 use_staging_texture
= FALSE
;
301 if (use_staging_texture
&& (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
304 trans
= CALLOC_STRUCT(r600_transfer
);
307 pipe_resource_reference(&trans
->transfer
.resource
, texture
);
308 trans
->transfer
.level
= level
;
309 trans
->transfer
.usage
= usage
;
310 trans
->transfer
.box
= *box
;
312 /* XXX: only readback the rectangle which is being mapped?
314 /* XXX: when discard is true, no need to read back from depth texture
316 r
= r600_texture_depth_flush(ctx
, texture
, FALSE
);
318 R600_ERR("failed to create temporary texture to hold untiled copy\n");
319 pipe_resource_reference(&trans
->transfer
.resource
, NULL
);
323 trans
->transfer
.stride
= rtex
->flushed_depth_texture
->surface
.level
[level
].pitch_bytes
;
324 trans
->offset
= r600_texture_get_offset(rtex
->flushed_depth_texture
, level
, box
->z
);
325 } else if (use_staging_texture
) {
326 resource
.target
= PIPE_TEXTURE_2D
;
327 resource
.format
= texture
->format
;
328 resource
.width0
= box
->width
;
329 resource
.height0
= box
->height
;
331 resource
.array_size
= 1;
332 resource
.last_level
= 0;
333 resource
.nr_samples
= 0;
334 resource
.usage
= PIPE_USAGE_STAGING
;
336 resource
.flags
= R600_RESOURCE_FLAG_TRANSFER
;
337 /* For texture reading, the temporary (detiled) texture is used as
338 * a render target when blitting from a tiled texture. */
339 if (usage
& PIPE_TRANSFER_READ
) {
340 resource
.bind
|= PIPE_BIND_RENDER_TARGET
;
342 /* For texture writing, the temporary texture is used as a sampler
343 * when blitting into a tiled texture. */
344 if (usage
& PIPE_TRANSFER_WRITE
) {
345 resource
.bind
|= PIPE_BIND_SAMPLER_VIEW
;
347 /* Create the temporary texture. */
348 trans
->staging_texture
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
349 if (trans
->staging_texture
== NULL
) {
350 R600_ERR("failed to create temporary texture to hold untiled copy\n");
351 pipe_resource_reference(&trans
->transfer
.resource
, NULL
);
356 trans
->transfer
.stride
= ((struct r600_resource_texture
*)trans
->staging_texture
)
357 ->surface
.level
[0].pitch_bytes
;
358 if (usage
& PIPE_TRANSFER_READ
) {
359 r600_copy_to_staging_texture(ctx
, trans
);
360 /* Always referenced in the blit. */
361 radeonsi_flush(ctx
, NULL
, 0);
364 trans
->transfer
.stride
= rtex
->surface
.level
[level
].pitch_bytes
;
365 trans
->transfer
.layer_stride
= rtex
->surface
.level
[level
].slice_size
;
366 trans
->offset
= r600_texture_get_offset(rtex
, level
, box
->z
);
369 if (trans
->staging_texture
) {
370 buf
= si_resource(trans
->staging_texture
)->cs_buf
;
372 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
374 if (rtex
->flushed_depth_texture
)
375 buf
= rtex
->flushed_depth_texture
->resource
.cs_buf
;
377 buf
= si_resource(texture
)->cs_buf
;
379 offset
= trans
->offset
+
380 box
->y
/ util_format_get_blockheight(format
) * trans
->transfer
.stride
+
381 box
->x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
384 if (!(map
= rctx
->ws
->buffer_map(buf
, rctx
->cs
, usage
))) {
385 pipe_resource_reference(&trans
->staging_texture
, NULL
);
386 pipe_resource_reference(&trans
->transfer
.resource
, NULL
);
391 *ptransfer
= &trans
->transfer
;
395 static void si_texture_transfer_unmap(struct pipe_context
*ctx
,
396 struct pipe_transfer
* transfer
)
398 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
399 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
400 struct radeon_winsys_cs_handle
*buf
;
401 struct pipe_resource
*texture
= transfer
->resource
;
402 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
404 if (rtransfer
->staging_texture
) {
405 buf
= si_resource(rtransfer
->staging_texture
)->cs_buf
;
407 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)transfer
->resource
;
409 if (rtex
->flushed_depth_texture
) {
410 buf
= rtex
->flushed_depth_texture
->resource
.cs_buf
;
412 buf
= si_resource(transfer
->resource
)->cs_buf
;
415 rctx
->ws
->buffer_unmap(buf
);
417 if (rtransfer
->staging_texture
) {
418 if (transfer
->usage
& PIPE_TRANSFER_WRITE
) {
419 r600_copy_from_staging_texture(ctx
, rtransfer
);
421 pipe_resource_reference(&rtransfer
->staging_texture
, NULL
);
424 if (rtex
->depth
&& !rtex
->is_flushing_texture
) {
425 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtex
->flushed_depth_texture
)
426 r600_blit_push_depth(ctx
, rtex
);
429 pipe_resource_reference(&transfer
->resource
, NULL
);
433 static const struct u_resource_vtbl r600_texture_vtbl
=
435 r600_texture_get_handle
, /* get_handle */
436 r600_texture_destroy
, /* resource_destroy */
437 si_texture_transfer_map
, /* transfer_map */
438 u_default_transfer_flush_region
,/* transfer_flush_region */
439 si_texture_transfer_unmap
, /* transfer_unmap */
440 NULL
/* transfer_inline_write */
443 static struct r600_resource_texture
*
444 r600_texture_create_object(struct pipe_screen
*screen
,
445 const struct pipe_resource
*base
,
447 unsigned pitch_in_bytes_override
,
448 unsigned max_buffer_size
,
449 struct pb_buffer
*buf
,
451 struct radeon_surface
*surface
)
453 struct r600_resource_texture
*rtex
;
454 struct si_resource
*resource
;
455 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
458 rtex
= CALLOC_STRUCT(r600_resource_texture
);
462 resource
= &rtex
->resource
;
463 resource
->b
.b
= *base
;
464 resource
->b
.vtbl
= &r600_texture_vtbl
;
465 pipe_reference_init(&resource
->b
.b
.reference
, 1);
466 resource
->b
.b
.screen
= screen
;
467 rtex
->pitch_override
= pitch_in_bytes_override
;
468 rtex
->real_format
= base
->format
;
470 /* only mark depth textures the HW can hit as depth textures */
471 if (util_format_is_depth_or_stencil(rtex
->real_format
) && permit_hardware_blit(screen
, base
))
474 rtex
->surface
= *surface
;
475 r
= r600_setup_surface(screen
, rtex
, array_mode
, pitch_in_bytes_override
);
481 /* Now create the backing buffer. */
482 if (!buf
&& alloc_bo
) {
483 unsigned base_align
= rtex
->surface
.bo_alignment
;
484 unsigned size
= rtex
->surface
.bo_size
;
486 base_align
= rtex
->surface
.bo_alignment
;
487 if (!si_init_resource(rscreen
, resource
, size
, base_align
, base
->bind
, base
->usage
)) {
493 resource
->cs_buf
= rscreen
->ws
->buffer_get_cs_handle(buf
);
494 resource
->domains
= RADEON_DOMAIN_GTT
| RADEON_DOMAIN_VRAM
;
500 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
501 const struct pipe_resource
*templ
)
503 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
504 struct radeon_surface surface
;
505 unsigned array_mode
= V_009910_ARRAY_LINEAR_ALIGNED
;
509 if (!(templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
) &&
510 !(templ
->bind
& PIPE_BIND_SCANOUT
)) {
511 if (permit_hardware_blit(screen
, templ
)) {
512 array_mode
= V_009910_ARRAY_2D_TILED_THIN1
;
517 r
= r600_init_surface(&surface
, templ
, array_mode
);
521 r
= rscreen
->ws
->surface_best(rscreen
->ws
, &surface
);
525 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
, array_mode
,
526 0, 0, NULL
, TRUE
, &surface
);
529 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
530 struct pipe_resource
*texture
,
531 const struct pipe_surface
*surf_tmpl
)
533 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
534 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
535 unsigned level
= surf_tmpl
->u
.tex
.level
;
537 assert(surf_tmpl
->u
.tex
.first_layer
== surf_tmpl
->u
.tex
.last_layer
);
541 /* offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
542 pipe_reference_init(&surface
->base
.reference
, 1);
543 pipe_resource_reference(&surface
->base
.texture
, texture
);
544 surface
->base
.context
= pipe
;
545 surface
->base
.format
= surf_tmpl
->format
;
546 surface
->base
.width
= rtex
->surface
.level
[level
].npix_x
;
547 surface
->base
.height
= rtex
->surface
.level
[level
].npix_y
;
548 surface
->base
.usage
= surf_tmpl
->usage
;
549 surface
->base
.texture
= texture
;
550 surface
->base
.u
.tex
.first_layer
= surf_tmpl
->u
.tex
.first_layer
;
551 surface
->base
.u
.tex
.last_layer
= surf_tmpl
->u
.tex
.last_layer
;
552 surface
->base
.u
.tex
.level
= level
;
554 return &surface
->base
;
557 static void r600_surface_destroy(struct pipe_context
*pipe
,
558 struct pipe_surface
*surface
)
560 pipe_resource_reference(&surface
->texture
, NULL
);
564 struct pipe_resource
*si_texture_from_handle(struct pipe_screen
*screen
,
565 const struct pipe_resource
*templ
,
566 struct winsys_handle
*whandle
)
568 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
569 struct pb_buffer
*buf
= NULL
;
571 unsigned array_mode
= V_009910_ARRAY_LINEAR_ALIGNED
;
572 enum radeon_bo_layout micro
, macro
;
573 struct radeon_surface surface
;
576 /* Support only 2D textures without mipmaps */
577 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
578 templ
->depth0
!= 1 || templ
->last_level
!= 0)
581 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
);
585 rscreen
->ws
->buffer_get_tiling(buf
, µ
, ¯o
,
586 &surface
.bankw
, &surface
.bankh
,
588 &surface
.stencil_tile_split
,
591 if (macro
== RADEON_LAYOUT_TILED
)
592 array_mode
= V_009910_ARRAY_2D_TILED_THIN1
;
593 else if (micro
== RADEON_LAYOUT_TILED
)
594 array_mode
= V_009910_ARRAY_1D_TILED_THIN1
;
596 array_mode
= V_009910_ARRAY_LINEAR_ALIGNED
;
598 r
= r600_init_surface(&surface
, templ
, array_mode
);
602 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
, array_mode
,
603 stride
, 0, buf
, FALSE
, &surface
);
606 int r600_texture_depth_flush(struct pipe_context
*ctx
,
607 struct pipe_resource
*texture
, boolean just_create
)
609 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
610 struct pipe_resource resource
;
612 if (rtex
->flushed_depth_texture
)
615 resource
.target
= texture
->target
;
616 resource
.format
= texture
->format
;
617 resource
.width0
= texture
->width0
;
618 resource
.height0
= texture
->height0
;
619 resource
.depth0
= texture
->depth0
;
620 resource
.array_size
= texture
->array_size
;
621 resource
.last_level
= texture
->last_level
;
622 resource
.nr_samples
= texture
->nr_samples
;
623 resource
.usage
= PIPE_USAGE_DYNAMIC
;
624 resource
.bind
= texture
->bind
| PIPE_BIND_DEPTH_STENCIL
;
625 resource
.flags
= R600_RESOURCE_FLAG_TRANSFER
| texture
->flags
;
627 rtex
->flushed_depth_texture
= (struct r600_resource_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
628 if (rtex
->flushed_depth_texture
== NULL
) {
629 R600_ERR("failed to create temporary texture to hold untiled copy\n");
633 ((struct r600_resource_texture
*)rtex
->flushed_depth_texture
)->is_flushing_texture
= TRUE
;
638 /* XXX: only do this if the depth texture has actually changed:
640 si_blit_uncompress_depth(ctx
, rtex
);
644 void si_init_surface_functions(struct r600_context
*r600
)
646 r600
->context
.create_surface
= r600_create_surface
;
647 r600
->context
.surface_destroy
= r600_surface_destroy
;